improving multiple-cmp systems with token coherence

(C) 2005 Multifacet Project

Improving Multiple-CMP Systems with Token

Coherence

Mike Marty1, Jesse Bingham2, Mark Hill1, Alan Hu2, Milo Martin3, and David Wood1

1University of Wisconsin-Madison2University of British Columbia

3University of Pennsylvania

Thanks to Intel, NSERC, NSF, and Sun

Improving Multiple-CMP Systems using Token Coherence

Summary

• Microprocessor Chip Multiprocessor (CMP)• Symmetric Multiprocessor (SMP) Multiple CMPs

• Problem: Coherence with Multiple CMPs

• Old Solution: Hierarchical Protocol Complex & Slow

• New Solution: Apply Token Coherence– Developed for glueless multiprocessor [ISCA 2003]– Keep: Flat for Correctness– Exploit: Hierarchical for performance

• Less Complex & Faster than Hierarchical Directory


Outline

• Motivation and Background– Coherence in Multiple-CMP Systems– Example: DirectoryCMP

• Token Coherence: Flat for Correctness

• Token Coherence: Hierarchical for Performance

• Evaluation


Coherence in Multiple-CMP Systems

CMP 3 CMP 4

CMP 2CMP 1

interconnect

I D I D I D I D

P P P P

L2 L2 L2 L2

• Chip Multiprocessors (CMPs) emerging• Larger systems will be built with Multiple CMPs

interconnect


Problem: Hierarchical Coherence

Inter-CMP Coherence

Intra-CMP Coherence

• Intra-CMP protocol for coherence within CMP• Inter-CMP protocol for coherence between CMPs• Interactions between protocols increase complexity

– explodes state space

CMP 3 CMP 4

CMP 2CMP 1

interconnect


Improving Multiple CMP Systems with Token Coherence

• Token Coherence allows Multiple-CMP systems to be...– Flat for correctness, but– Hierarchical for performance

Correctness Substrate

PerformanceProtocol

Low ComplexityFast

interconnect

CMP 3 CMP 4

CMP 2CMP 1


Memory/Directory

Example: DirectoryCMP

CMP 0

P0Store B

CMP 1

L1 I&D

Shared L2 / directory

P1L1 I&D

P2L1 I&D

P3L1 I&D

P4L1 I&D

P5L1 I&D

P6L1 I&D

P7L1 I&D

getx

getxfwd

fwd invinvinv

Shared L2 / directory

ackack ackdata/ack

data/ack

data/ack

S

O SSS

2-level MOESI Directory

getxWB

getx

WB

RACE CONDITIONS!

Store B

Memory/Directory

B: [S O] B: [M I]


Outline

• Motivation and Background

• Token Coherence: Flat for Correctness– Safety– Starvation Avoidance


• Evaluation


Store BLoad B

Example: Token Coherence [ISCA 2003]

Load B

• Each memory block initialized with T tokens• Tokens stored in memory, caches, & messages• At least one token to read a block• All tokens to write a block

P0L1 I&D

L2

P1L1 I&D

L2

P2L1 I&D

L2

P3L1 I&D

L2

interconnect

Store B

mem 0 mem 3


Extending to Multiple-CMP System

P0L1 I&D

L2

P1L1 I&D

L2

P2L1 I&D

L2

P3L1 I&D

L2

interconnectmem 0 mem 1

CMP 0

interconnect

Shared L2

CMP 1

interconnect

Shared L2


mem 0

Extending to Multiple-CMP SystemCMP 0

interconnect

P0

interconnect

P1

mem 1

CMP 1

interconnect

P2 P3

• Token counting remains flat• Tokens to caches

– Handles shared caches and other complex hierarchies

Shared L2 Shared L2

L1 I&D L1 I&D L1 I&D L1 I&D

Store BStore B


mem 0

Starvation AvoidanceCMP 0

interconnect

P0Store B

interconnect

P1

mem 1

CMP 1

interconnect

P2Store B

P3

• Tokens move freely in the system– Transient requests can miss in-flight tokens– Incorrect speculation, filters, prediction, etc

Shared L2 Shared L2

Store B

GETXGETX GETX



mem 0

Starvation AvoidanceCMP 0

interconnect

P0

interconnect

P1

mem 1

CMP 1

interconnect

P2 P3

Shared L2 Shared L2


• Solution: issue Persistent Request– Heavyweight request guaranteed to succeed– Methods: Centralized [2003] and Distributed (New)

Store B Store BStore B


mem 0

Old Scheme: Central Arbiter [2003]CMP 0

interconnect

P0Store B

interconnect

P1

mem 1

CMP 1

interconnect

P2Store B

P3

– Processors issue persistent requests

Shared L2 Shared L2

Store B


arbiter 0arbiter 0B: P0

B: P2B: P1

timeout timeout timeout


mem 0


interconnect

P0Store B

interconnect

P1

mem 1

CMP 1

interconnect

P2Store B

P3

– Processors issue persistent requests– Arbiter orders and broadcasts activate

Shared L2 Shared L2

Store B


arbiter 0arbiter 0B: P0

B: P2B: P1

B: P0

B: P0 B: P0 B: P0 B: P0

B: P0

Store B


mem 0


interconnect

P0

interconnect

P1

mem 1

CMP 1

interconnect

P2Store B

P3

– Processor sends deactivate to arbiter– Arbiter broadcasts deactivate (and next activate)– Bottom Line: handoff is 3 message latencies

Shared L2 Shared L2

Store B


arbiter 0arbiter 0

B: P2B: P1

B: P0

B: P0 B: P0 B: P0 B: P0

B: P0

B: P2

B: P2

B: P2 B: P2

B: P2

B: P2B: P2

Store B

B: P0

1 2

3


mem 0

Improved Scheme: Distributed Arbitration [NEW]CMP 0

interconnect

P0Store B

interconnect

P1: BP2: B

P0: B

P1: BP2: B

P0: B P1 P1: BP2: B

P0: B

mem 1

CMP 1

interconnect

P2Store B

P1: BP2: B

P0: B

P1: BP2: B

P0: B P3P1: BP2: B

P0: B

P1: BP2: B

P0: B

– Processors broadcast persistent requests

Shared L2 Shared L2

Store B



mem 0


interconnect

P0Store B

interconnect

P1: BP2: B

P0: B

P1: BP2: B

P0: B P1 P1: BP2: B

P0: B

mem 1

CMP 1

interconnect

P2Store B

P1: BP2: B

P0: B

P1: BP2: B

P0: B P3P1: BP2: B

P0: B

P1: BP2: B

P0: B

– Processors broadcast persistent requests– Fixed priority (processor number)

Store BP0: B P0: B

P0: B

P0: B

P0: B P0: B

P0: BShared L2Shared L2



mem 0


interconnect

P0

interconnect

P1: BP2: B

P0: B

P1: BP2: B

P0: B P1 P1: BP2: B

P0: B

mem 1

CMP 1

interconnect

P2Store B

P1: BP2: B

P0: B

P1: BP2: B

P0: B P3P1: BP2: B

P0: B

P1: BP2: B

P0: B

Shared L2 Shared L2

Store B

– Processors broadcast persistent requests– Fixed priority (processor number)– Processors broadcast deactivate

P1: B P1: B P1: B P1: B

P1: B

P1: B P1: B

L1 I&D L1 I&D L1 I&D L1 I&D1


mem 0


interconnect

P0

interconnect

P1: BP2: B

P1: BP2: B

P1 P1: BP2: B

mem 1

CMP 1

interconnect

P2

P1: BP2: B

P1: BP2: B

P3P1: BP2: B

P1: BP2: B

Shared L2 Shared L2

– Bottom line: Handoff is a single message latency• Subtle point: P0 and P1 must wait until next “wave”

P1: B P1: B P1: B P1: B

P1: B

P1: B P1: B

L1 I&D L1 I&D L1 I&D L1 I&D1


Outline




• Evaluation


Hierarchical for Performance: TokenCMP

• Target System:– 2-8 CMPs– Private L1s, shared L2 per CMP– Any interconnect, but high-bandwidth

• Performance Policy Goals: – Aggressively acquire tokens– Exploit on-chip locality and bandwidth– Respect cache hierarchy– Detecting and handling missed tokens


Hierarchical for Performance: TokenCMP

• Approach:– On L1 miss, broadcast within own CMP

• Local cache responds if possible– On L2 miss, broadcast to other CMPs– Appropriate L2 bank responds or broadcasts within its CMP

• Optionally filter – Responses between CMPs carry extra tokens

for future locality

• Handling missed tokens:– Timeout after average memory latency – Invoke persistent request (no retries)

• Larger systems can use filters, multicast, soft-state directories


Outline




• Evaluation– Model checking– Performance w/ commercial workloads– Robustness


TokenCMP Evaluation

• Simple?– Model checking

• Fast?– Full-system simulation w/ commercial workloads

• Robust?– Micro-benchmarks to simulate high contention


Complexity Evaluation with Model Checking

• Methods:– TLA+ and TLC– DirectoryCMP omits all intra-CMP details– TokenCMP’s correctness substrate modeled

• Result:– Complexity similar between TokenCMP and non-hierarchical

DirectoryCMP

– Correctness Substrate verified to be correct and deadlock-free

• Small configuration, varied parameters

– All possible performance protocols correct


Performance Evaluation

• Target System:– 4 CMPs, 4 procs/cmp– 2GHz OoO SPARC, 8MB shared L2 per chip– Directly connected interconnect

• Methods: Multifacet GEMS simulator– Simics augmented with timing models– Released soon: http://www.cs.wisc.edu/gems– ISCA 2005 Tutorial!

• Benchmarks:– Performance: Apache, Spec, OLTP– Robustness: Locking uBenchmark

http://www.cs.wisc.edu/gems


Full-system Simulation: Runtime

– TokenCMP performs 9-50% faster than DirectoryCMP


Full-system Simulation: Runtime

– TokenCMP performs 9-50% faster than DirectoryCMP

DRAM DirectoryPerfect L2


Full-system Simulation: Traffic

– TokenCMP traffic is reasonable (or better)

• DirectoryCMP control overhead greater than broadcast for small system


Performance RobustnessLocking micro-benchmark

less contentionmore contention

(correctness substrate only)


Performance RobustnessLocking micro-benchmark

less contentionmore contention


Summary

• Microprocessor Chip Multiprocessor (CMP)• Symmetric Multiprocessor (SMP) Multiple CMPs

• Problem: Coherence with Multiple CMPs

• Old Solution: Hierarchical Protocol Complex & Slow

• New Solution: Apply Token Coherence– Developed for glueless multiprocessor [2003]– Keep: Flat for Correctness– Exploit: Hierarchical for performance

• Less Complex & Faster than Hierarchical Directory


Full-system Simulation: Traffic


Full-system Simulation: Intra-CMP Traffic

improving multiple-cmp systems with token coherence

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