improved on-resistance measurement at wafer probe using a ......vgs. takahashi, toyoda present...

Improved ON-resistance Measurement at Wafer Probe using a "DARUMA" stage

Masatomo TAKAHASHIACCRETECH, Japan

Nobuyuki TOYODATESEC, Japan

Overview

2

• Solution– DARUMA– Overview of DARUMA Chuck– Advantage of DARUMA Chuck etc.

• Verification– Measurement by “DARUMA”– Comparison with standard stage– Simulation

• Conclusion

Takahashi, Toyoda

• Background– Trend of MOSFET– Transition of low ON resistance

(Rds(on)) products• Present situation

– Measurement by Standard stage

– Matter of concern– Suspected root cause

Trends of MOSFET• Application and Criteria

– Load switch for DC Supply-unit in server• Low On-Resistance (Rds(on))• Low Thermal Resistance (Rθjc, etc.)• Wide Safe Operating Area (SOA)

– Switching device for switched-mode power supply (SMPS)• Low Rds(on)

• Low Gate Charge (Qg)– Motor control

• Low Reverse Recovery Time (trr)3Takahashi, Toyoda

Trends of MOSFET• Purpose vs Representative Characteristics

– Energy savings ⇒ Low On-Resistance(Low loss)

– Fast switching ⇒ Low gate Capacitance(High speed)

– High reliability ⇒ Wide Safe Operating Area,(High performance) High breakdown resistance

– Miniaturization ⇒ Enhancement of Heat-resisting property(Small packaging)

4Takahashi, Toyoda

Graphs from Toshiba Review Vol.65No.1 (2010)

5

Breakdown volt (V)

Gan marginalSic marginal

Si marginal

Transition of low ON resistor products

Takahashi, Toyoda

Less than 1m ohm

Present situation

• Standard System connection

6

TESEC431-TTDiscreteDC Tester

Test Station

AccretechUF2000Wafer Prober

Takahashi, Toyoda

VI-SMU inside

Gate Force(GI),Gate Sense(GV),Source Force(SI),Source Sense(SV)

Drain Force(DI),Drain Sense(DV)

Present situation

• Simplified Schematics for Rds(on) testing at wafer probe

7

VPulse Current

Pulse Voltage GateSource

Drain

VoltmeterA

Ammeter

IDS

VGS

VDSIDS

DUT

Takahashi, Toyoda

Present situation

• Simplified Schematics for Rds(on) to check waveform

8

VPulse Current

Pulse Voltage GateSource

Drain

VoltmeterA

Ammeter

IDS

VGS

VDSIDS

DUT

Current Sense Transformer

DSO

Waveform Monitoron the Tester

IDS,VGS

VDS

Takahashi, Toyoda

Present situation

• Timing chart

9

IDS

VGS

100uS 300uS

Takahashi, Toyoda

[Measurement result-1]Test condition : Rds(on), IDS=200A, Test time=500uSStage type : Standard

10

IDS

VGS

Takahashi, Toyoda

Present situation

Instability @500uS

500uS500uS

100uS100uS

11

IDS

VGS

[Measurement result-2]Test condition : Rds(on), IDS=200A, Test time=1000uSStage type : Standard

Takahashi, Toyoda

Present situation

1000uS1000uS

Stable after 500uS, but still gradually cut-down

100uS100uS

Matters of concern

12Takahashi, Toyoda

Measurement waveform is unstable(Need longer test time to be stabilize)

Increases Forcing time of test current

Increases temperature of the tested device

Decreases the test accuracy and production quality

Matters of concern

• Ideal test environment (Temperature)– Exists when the channel(Junction) and case (package)

temp are the same.– Requires “Very short pulse” during on-resistance test to

achieve temperature parity between Junction and Case– Characteristic of MOSFETs, the on-resistance will rise as

the device temp is increased in an attempt to protect the device itself (as the resistance increases, the current decreases)

– Therefore, when testing Rds(on) , controlling the temperature rise is critical to measurement stability.

– To control the temp during test,

“minimize the test time”

13Takahashi, Toyoda

From Fuji Electric AN-079 Rev.1.1

ON resistance vs Channel temperature

Expected root cause

• Ls (Stray Inductance)– Self inductance of wire loop (round trip)

Diameter of the wire to be ‘2a’,When the current is uniformly distributed in the electric wire,and the conductor is nonmagnetic.L = 4 * log(d/a) * 10^-7 [H/m]

14Takahashi, Toyoda

dI

I

Expected root cause

• Ls (Stray Inductance)– Mutual inductance between parallel wires

Pair of parallel wires,When l >> d , and in the air atmosphere.M = 2 * l * (log(2 * l / d) -1) * 10^-7 [H]

15Takahashi, Toyoda

d

l

Expected root cause• VDS waveform is NOT stable.– Influence of the Stray Inductance (Ls)

of the wiring between DUT andsource & measurement circuits.

– Ls increases as the wire loop increases.

16

Source

DrainV

A

Stage

Wafer

Takahashi, Toyoda

Expected root cause

• The cause of the VDS “Spiking” is in Ls.ΔV=Ls(di/dt)

17

IDS

VGS

Takahashi, Toyoda

• The Daruma doll, is a hollow, round, Japanese traditional doll modeled after Bodhidharma (Dharma), the founder of the Zen sect of Buddhism. Daruma has a design that is rich in symbolism and is regarded more as a talisman of good luck to the Japanese.

• When purchased, the eyes are white so a person can decide on a goal or wish and paint one eye in. Once the goal is achieved, the second eye is filled in.

18Takahashi, Toyoda

“DARUMA”

Overview of DARUMA Chuck (1)

19Takahashi, Toyoda

Standard connection

Over 2m

To Tester

Wire

DARUMA connection

To Tester

Several cmMetal Plate

Overview of DARUMA Chuck (2)

20Takahashi, Toyoda

Pogo Block

Wafer Chuck

DARUMA Chuck

Z Unit

Needles

Probe Card

Advantage of DARUMA Chuck

21Takahashi, Toyoda

200mm

DARUMA Chuck

Pogo Pins

Wafer Chuck

Probe Card

Tester

Maintain same distance

Wafer Chuck

DARUMA Chuck

Front

Back

@ Front side of wafer

Wafer Chuck DARUMA Chuck

@ Back side of wafer

Wafer Chuck DARUMA Chuck

Alignment for Pogo Pins

22Takahashi, Toyoda

Search pogo pin height and check the difference using alignment camera. Then calculate the best over drive point for contacting to the DARUMA chuck.

Probe to pad alignment camera

Maintenance

23Takahashi, Toyoda

Remove chuck Remove chuck Install chuck Planarity check

Required periodical chuck top maintenance

• Turn ON voltage/Contact resistance <- Chuck surface condition• Large current/Inductive load test -> Deteriorating chuck top

Overview of Evaluation Setup

24Takahashi, Toyoda

Verification

• DARUMA System connection

25


Test Station


Takahashi, Toyoda

VI-SMU inside

Drain Sense(DV)

Gate Force(GI),Gate Sense(GV),Source Force(SI),Source Sense(SV),Drain Force(DI)

Verification

26

IDS

VGS

[Measurement result-1]Test condition : Rds(on), IDS=200A, Test time=500uS

Stage type : DARUMA

Takahashi, Toyoda

500uS100uS500uS100uS

Stable @500uS

27

IDS

VGS

Verification

Takahashi, Toyoda

[Measurement result-2]Test condition : Rds(on), IDS=200A, Test time=1000uS

Stage type : DARUMA1000uS100uS

1000uS100uS

Furthermore stable @1000uS

28

Test condition : Rds(on), IDS=200A, Test time=1000uSStandard connection DARUMA connection

Comparison with standard stage

Takahashi, Toyoda

29


Takahashi, Toyoda

Standard

DARUMA


• Standard system connection

30


Test Station


Takahashi, Toyoda

VI-SMU inside

Gate Force(GI),Gate Sense(GV),Source Force(SI),Source Sense(SV)

Drain Force(DI),Drain Sense(DV)


• DARUMA system connection

31


Test Station


Takahashi, Toyoda

VI-SMU inside

Drain Sense(DV)

Gate Force(GI),Gate Sense(GV),Source Force(SI),Source Sense(SV),Drain Force(DI)


32

Standard

Takahashi, Toyoda

V

SI

SV

GI

GV

DI

DV

DARUMAPogo Pins

V

SI

SV

GI

GV

DI

DV

North

South

EastWest

North

South

EastWest

• Point of interest



33

Standard DARUMAGV Probe Card GI Probe Card SV Probe Card SI Probe Card

DV South Eastof the Stage

Southof the Stage

DINorth West of the Stagevia 2m Wire

North of the Stage

via DARUMA

Device Connection Comparison TableStandard vs DARUMA

Takahashi, Toyoda



34

DIDV

R1 R2

R3

R1 and R2 do not affect to VDSON value.R3 is added to VDSON.It is only R3 that increases VDSON.Measurement values are almost independent of location.

R3 is Contact resistance between Wafer and Stage.

Takahashi, Toyoda

Simulation

• Simulated model Schematics for Standard connection

35Takahashi, Toyoda

V

A

Tester, Station and Wiring (Outside of the Prober) Inside of the Prober

R9 = Rds(on)

Simulation

• Waveform Simulated vs Actual, @Standard

36Takahashi, Toyoda

Actual Standard

IDS

VDS

Simulated Standard

Simulation

• Simulated model Schematics for DARUMA connection

37

V

A

Tester, Station and Wiring (Outside of the Prober) Inside of the Prober

Takahashi, Toyoda

R9 = Rds(on)

Simulation

• Waveform Simulated vs Actual, @DARUMA

38Takahashi, Toyoda

Actual DARUMA

IDS

VDS

Simulated DARUMA

Simulation

• Simulated Waves comparison Standard vs DARUMA

39Takahashi, Toyoda

IDS

VDS

Simulated Standard

IDS

VDS

Simulated DARUMA

Conclusion• Demand for higher-efficiency of Mobile and Automotive devices, is

driving the need for MOSFETs with even lower Rds(on) .

• Improving measurement accuracy while at the same time reducing device stress will continue to be test challenges for the future.

• However, by employing a “DARUMA” stage, these test challenges can be met at wafer probe when testing (Rds(on)) on MOSFETs. Ls will be minimized to enable reduced test time (especially at high current). By reducing test time, temperature rise will be reduced producing less stress on the DUT also resulting in more stable and accurate measurements.

40Takahashi, Toyoda

AcknowledgementsWe would like to thank the following colleagues for supporting this workshop.

Yuji SHIGESAWA Yuichi KAKIZAKITomoyuki MYOJO Kiyoaki KOYAMAShoji TERADA Muneo ISHINOHACHI

Masashi HOSHINO

• We hope these efforts bring further development of products that will contribute to societal advancements.

41Takahashi, Toyoda

Thank you

42

improved on-resistance measurement at wafer probe using a ......vgs. takahashi, toyoda present...

Documents