Improved Migration-Enhanced Epitaxy for Self-Aligned InGaAs

Devices

Electronic Materials Conference (EMC), 6-25-2009

Mark A. Wistey

University of California, Santa BarbaraNow at University of Notre Dame

mwistey@nd.edu

mwistey@nd.edu

U. Singisetti, G. Burek, A. Baraskar, V. Jain, B. Thibault, A. Nelson, E. Arkun, C. Palmstrøm, J. Cagnon, S. Stemmer, A. Gossard, M. RodwellUniversity of California Santa Barbara

P. McIntyre, B. Shin, E. KimStanford UniversityS. BankUniversity of Texas Austin Y.-J. LeeIntel Funding: SRC

2Wistey, EMC 2009

Outline: Channels for Future CMOS

•Motivation for Self-Aligned Regrowth

•Facets, Gaps, Arsenic Flux and MEE

•Si doping and MEE•Scalable III-V MOSFETs•The Shape of Things to Come

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Motivation for Self-Aligned Regrowth

• 3D nanofabrication

Qi Xinag, ECS 2004, AMD

AlGaAsGaAs

InGaAsGaAs

AlGaAsGaAs

Blanket layers

?

• Device properties–Heat transfer–Contacts–Current blocking

Air gap VCSEL,Dave Buell thesis

Buried het laser,C-W Hu JECS 2007

W.K. Liu et al., J. Crystal Growth v. 311, p. 1979 (2009)

• Integration: III-V’s on Si

• Heteroepitaxy• Selective area growth

• And III-V MOSFETs...

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Motivation for Regrowth: Scalable III-V FETs

Classic III-V FET (details vary):

ChannelBottom BarrierInAlAs Barrier

Top Barrier or Oxide

Gate

Low doping

GapSource Drain

Large Rc {

Large Area Contacts{

• Advantages of III-V’s

• Disadvantages of III-V’s

III-V FET with Self-Aligned Regrowth:

ChannelIn(Ga)P Etch StopBottom Barrier

High-k

Gate

n+ Regrowth

High Velocity Channel

Implant: straggle,

short channel effects

Small RaccessSmall

Rc

Self-aligned

High doping: 1013 cm-2 avoids source exhaustion

2D injection avoids source starvation

Dopants active as-grown

High mobilityaccess regions

High barrier

Ultrathin 5nm doping layer

}

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Process Flow Prior to Regrowth

Pattern gate metalSelective dry etches

SiNx or SiO2 sidewallsEncapsulate gate metals

Controlled recess etch (optional)Slow facet planesNot needed for depletion-mode FETs

Surface cleanUV ozone, 1:10 HCl:water dip & rinse, UHV deox (hydrogen or thermal)

Regrowth

In(Ga)P etch stop

InAlAs barrier

InP substrate

Metals

high-k

Channel

SiO2,SiNx

Fabrication details: U. Singisetti, PSSC 2009

Rodwell IPRM 2008

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MBE Regrowth: Bad at any Temperature?

• Low growth temperature (<400°C):

–Smooth in far field–Gap near gate (“shadowing”)–No contact to channel (bad)

GateGate

200nm Gap

Source-DrainRegrowth

Source-DrainRegrowth

SEMs: Uttam Singisetti

Metals

Channel

SiO2

high-k GateGate

Source-DrainRegrowth

Source-DrainRegrowth

Regrowth: 50nm InGaAs:Si, 5nm InAs:Si. Si=8E19/cm3, 20nm Mo, V/III=35, 0.5 µm/hr.

•High growth temperature (>490°C):– Selective/preferential epi on InGaAs– No gaps near gate

– Rough far field – High resistance

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Gap-free Regrowth by MEE

Migration-Enhanced Epitaxy (MEE) conditions:490-560°C (pyrometer)As flux constant ~ 1x10-6 Torr: V/III~3, not interrupted.0.5nm InGaAs:Si pulses (3.7 sec), 10-15 sec As soak

Original Interface

InGaAs Regrowth

SiO2 dummy gate

SEM: Greg Burek•Smaller gapCrosshatching—relaxation?

•High Si activation (4x1019 cm-3).

SEM: Uttam Singisetti

InGaAs Regrowth

SEM Cross Section

SiO2 dummy gate

SEM Side View

Top of gate: amorphous

InGaAs

Wistey, MBE 2008

RHEED: 4x2 ==> 1x2 or 2x4 ==> 4x2 with each pulse.

•Quasi-selective growth

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560C

490C460C

SiO2 dummy

gate

SiO2 dummy

gate

540C

No gaps, but faceting next

to gates

Gap

High Temperature MEE: Smooth & No Gaps

Smooth regrowth

Note faceting: surface kinetics, not shadowing.In=9.7E-8, Ga=5.1E-8 Torr

Wistey EMC 2009 9

Shadowing and Facet Competition

[111]

[100]

Fast surface diffusion = slow facet growth

Slow diffusion = rapid facet

growth

Shen & Nishinaga, JCG 1995

[111] faster

[100] faster

•Shen JCG 1995 says:Increased As favors [111] growth

SiO2

[111]

[100]

Slow diffusion

=fast growth

Fast surface diffusion = slow facet growthS

iO2

Good fill next to gate.

•But gap persists

Wistey EMC 2009 10

Gate Changes Local Kinetics

[100]

2. Local enrichmen

t of III/V ratio

4. Low-angle planes grow instead

SiO2

1. Excess In & Ga don’t stick

to SiO2

• Diffusion of Group III’s away from gate• Solution: Override local enrichment of Group III’s

3. Increased surface mobility

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Control of Facets by Arsenic Flux

SiO2

WCr

Increasing As flux

SEM of single-wafer growth series varying As flux

Original Interface

InAlAsmarker

sInGaAs

• InGaAs Experiment:

• Vary As flux• InAlAs marker layers

• Find best fill near gate 0.5x10-6

1x10-62x10-6

5x10-6

• Lowest arsenic flux → “rising tide fill”

• No gaps near gate or SiO2/SiNx• Tunable facet competition

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Scalable InGaAs MOSFETs

InGaAs Channel, NID

10 nm InAlAs Setback, NID

Semi-insulating InP Substrate

5 nm Al2O3

50 nm W

300 nm SiO2 Cap

SiN

x

5 nm InAlAs, Si=8x1019 cm-3

200 nm InAlAs buffer

50 nm Cr

n++ regrowth

Mo Mo

n++ regrowth3 nm InGaP Etch Stop, NID

Top view SEM Obliqueview

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Scalable InGaAs MOSFETs

InGaAs Channel, NID

10 nm InAlAs Setback, NID

Semi-insulating InP Substrate

5 nm Al2O3

50 nm W

300 nm SiO2 Cap

SiN

x

5 nm InAlAs, Si=8x1019 cm-3

200 nm InAlAs buffer

50 nm Cr

n++ regrowth

Mo Mo

n++ regrowth3 nm InGaP Etch Stop, NID

•Conservative doping design:•[Si] = 4x1013 cm-2

•Bulk n = 1x1013 cm-2 >> Dit

•Large setback + high doping = Can’t turn off

•High Rsource > 350 Ω-µm

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TechniqueShutter Pattern

(Arsenic always open)[Si] (cm-3)

n (cm-3)

µ (cm2V-1s-1)

Conventional MBE 8x1019 4.8x1019 847

Si during Group III MEE pulse

8x1019 4.3x1019 1258

Si during As soak

8x1019 4.2x1019 1295

Double Si doping 16x1019 -- --

Wistey, EMC 2009

Silicon Doping in MEE

• Electron concentration nearly constant

• Si prefers Group III site even under As-poor conditions

• Increased mobility by MEE

Ga

Si

Ga

Si

Ga

Si

Ga

Si

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Regrown InAs S/D FETs

side of gate

top of gate

Mo S/D metal with N+ InAs underneath

4.7 nm Al203, 5×1012 cm-2 pulse doping

In=9.7E-8, Ga=5.1E-8 Torr

SEM: Uttam Singisetti

• Gallium-free= improved selectivity in regrowth

InAsregrowth

• InAs native defects are donors.1

• Reduces surface depletion. • Decreased As flux works for InAs too.

1 Bhargava et al , APL 1997

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InAs Source-Drain Access Resistance**Wistey et al, NAMBE 2009

4.7 nm Al203, InAs S/D E-FET. TLMs corrected for metal resistance.

Slide: Uttam Singisetti, DRC 2009

• Total Ron = 600 Ω-μm ➡ Rs < 300 Ω−μm.• gm << 1/Rs ~ 3.3 mS/μm -- Not source-limited. InAs contacts no longer limit MOSFET performance.

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The Shape of Things to Come

Generalized Self-Aligned Regrowth Designs:

ChannelBack BarrierSubstrate

Top Barrier

Gate

n+ Regrowth

• Self-aligned regrowth can also be used for:

• GaN HEMTs (with Nidhi in Mishra group, EMC 2009)

• InGaAs HBTs and HEMTs

• Selective III-V on Si — remove gaps

• THz and high speed III-V electronics

Back BarrierSubstrate

Top Barrier

GateRecessedRaised

Channel

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Conclusions

• Reducing As flux improves filling near gate

• Self-aligned regrowth: a roadmap for scalable III-V FETs

–Provides III-V’s with a salicide equivalent

–Can improve GaN and GaAs FETs too

• Silicon doping impervious to MEE technique

• InAs regrown contacts improve InGaAs MOSFETs...

–Not limited by source resistance @ 1 mA/µm

–Comparable to other III-V FETs... but now scalable

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Acknowledgements

• Rodwell & Gossard Groups (UCSB): Uttam Singisetti, Greg Burek, Ashish Baraskar, Vibhor Jain...

• McIntyre Group (Stanford): Eunji Kim, Byungha Shin, Paul McIntyre

• Stemmer Group (UCSB): Joël Cagnon, Susanne Stemmer

• Palmstrøm Group (UCSB): Erdem Arkun, Chris Palmstrøm

• SRC/GRC funding

• UCSB Nanofab: Brian Thibeault, NSF