implementing digital circuits lecture l3.1. implementing digital circuits transistors and integrated...

Implementing Digital Circuits

Lecture L3.1


• Transistors and Integrated Circuits

• Transistor-Transistor Logic (TTL)

• Programmable Logic Devices– PLDs and CPLDs

• Field Programmable Gate Arrays (FPGAs)– The Xilinx Spartan 3– The Xilinx Virtex Family

Discovery of the Electron -- 1898

J. J. ThomsonCathode Tube

Cavendish Labs

Electric Field -- “corpuscle”

The Vacuum Tube

The FirstPoint-Contact

Transistor1947

Bell Labs Museum

The FirstJunction Transistor

1951

Bell Labs

Lab model

M1752Outside the Lab

Texas Instrument’s First IC -- 1958

Jack Kilby

Robert NoyceFairchildIntel

Moore’s Law

Moore's Law(As predicted by Gordon E. Moore in 1965)

1

100

10000

1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975

Year

Tra

nsi

sto

rs

Moore’s Law

Moore's Law(Doubling every 2 years)

0.001

0.01

0.1

1

10

100

1000

10000

1974 1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010

Year

Tra

nsi

sto

rs (

in m

illio

ns

)

8080

286

486 Pentium

Pentium II

Pentium 4

64K

1M

4M

16M

Memory

Microprocessor

Transistor-Transistor Logic (TTL)

• Developed in mid-1960s

• Large family (74xx) of chips from basic gates to arithmetic logic units

• Becoming obsolete with the development of programmable logic devices (PLDs)

Transistor-Transistor Logic (TTL)

Diode-Transistor LogicDTL Transistor-Transistor Logic (TTL)

"Totem Pole" output

TTL Chips

1 2 3 4 5 6 7

8 9 1011121314

1 2 3 4 5 6 7

8 9 1011121314

1 2 3 4 5 6 7

8 9 1011121314

7404 Hex Inverters

7408 Quad 2-Input AND Gates

7432 Quad 2-Input OR Gates

TTL NAND, NOR, XOR

1 2 3 4 5 6 7

8 9 1011121314

1 2 3 4 5 6 7

8 9 1011121314

1 2 3 4 5 6 7

8 9 1011121314

7400 Quad 2-Input NAND Gates

7402 Quad 2-Input NOR Gates

7486 Quad 2-Input EXCLUSIVE-OR Gates

TTL Multiple-input Gates

1 2 3 4 5 6 7

8 9 1011121314

1 2 3 4 5 6 7

8 9 1011121314

7421 Dual 4-Input AND Gates

7430 8-Input NAND Gate

Small-Scale Integrated (SSI) Circuits

• 1 to 10 gates

• NAND gate has 4 transistors

Medium-Scale Integrated (MSI) Circuits

• 10-100 gates

• Adders

• Comparators

• Multiplexers

• Decoders

Large-Scale Integrated (LSI) Circuits

• 100-1000 gates

• Arithmetic Logic Units

Very-Large-Scale Integrated (VLSI) Circuits

• >1000 gates

• Microprocessors

• Programmable Logic Devices (PLDs)

• Complex Programmable Logic Devices (CPLDs)

• Field Programmable Gate Arrays (FPGAs)

A Programmable Logic DeviceX Y

X !X Y !Y

A

B

1

2

Z

removable jumpers


X !X Y !Y

A

B

1

2

Z

removable jumpers

A = X & !X & Y & !Y = 0 & 0 = 0


X !X Y !Y

A

B

1

2

Z

removable jumpers

A = X & !X & Y & !Y = 0 & 0 = 0

Z = A # B = 0 # B = B

Alternate PLD RepresentationX Y

X !X Y !Y

A

B

Z X X X X

X X X X

1

2

Make PLD Connections for ANDX Y

X !X Y !Y

A

B

Z 1

2

XX

X X X X

Make PLD Connections for ORX Y

X !X Y !Y

A

B

Z 1

2 X

X

Make PLD Connections for NANDX Y

X !X Y !Y

A

B

Z 1

2 X

X

Make PLD Connections for NORX Y

X !X Y !Y

A

B

Z 1

2

XX

XXXX

Make PLD Connections for XNORX Y

X !X Y !Y

A

B

Z 1

2

XX

X XA B C0 0 10 1 01 0 01 1 1

Make PLD Connections for XORX Y

X !X Y !Y

A

B

Z 1

2

XX

X XA B C0 0 00 1 11 0 11 1 0

The GAL 16V8

1

2

3

4

5

6

7

9

10 11

12

8

19

20

17

18

15

16

13

14

GND

Vcc I/CLK I I/O

I I

I

I

I

I

I

I/OE

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GAL 16V8

Structure of the GAL 16V8 PLDX X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

Pin 2

Pin 3

Pin 19

X

Y

Z

GAL 16V8 Polarity Control

OE

X

A

B

C

X closed B = 0 C = A open B = 1 C = !A

Polarity

Pin

Typical PLD Flip-Flops

X Polarity

OE

Pin CLK

D Q

!Q

CLK

CLK Feedback

Structure of the GAL 16V8 PLDX X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

Pin 2

Pin 3

Pin 19

X

Y

Z

XC9500 CPLDs

• 5 volt in-system programmable (ISP) CPLDs

• 5 ns pin-to-pin• 36 to 288

macrocells (6400 gates)

• Industry’s best pin-locking architecture

• 10,000 program/erase cycles

• Complete IEEE 1149.1 JTAG capability

FunctionBlock 1

JTAGController

FunctionBlock 2

I/O

FunctionBlock 4

3

Global Tri-

States 2 or 4

FunctionBlock 3

I/O

In-SystemProgramming Controller

FastCONNECTSwitch Matrix

JTAG Port

3

I/O

I/O

Global Set/Reset

Global Clocks

I/OBlocks

1

XC9500 Function Block

ToFastCONNECT

FromFastCONNECT

2 or 43 GlobalTri-State

GlobalClocks

I/O

I/O

36

Product-Term

Allocator

Macrocell 1

ANDArray

Macrocell 18

Each function block is like a 36V18 !

XC9500 Product Family

9536

Macrocells

Usable Gates

tPD (ns)

Registers

Max I/O

36 72 108 144 216

800 1600 2400 3200 4800

5 7.5 7.5 7.5 10

36 72 108 144 216

34 72 108 133 166

Packages VQ44PC44 PC44

PC84TQ100PQ100

PC84TQ100PQ100PQ160

PQ100PQ160

288

6400

10

288

192

HQ208BG352

PQ160HQ208BG352

9572 95108 95144 95216 95288

PLDT-3

XilinxXC95108 CPLD

7 segment display

Switches

LEDs

Buttons

Xilinx 95108

• 6 function blocks– Each contains 18 macro cells– Each macro cell behaves like a GAL32V18

• AND-OR array for sum-of-products

• 32 inputs and 18 outputs

Architecture of the Xilinx XC95108 CPLD

Each Xilinx 95108 macrocell contains a D flip-flop

Controlled inverter

Each Xilinx 95108 macrocell contains a D flip-flop

Note asynchronouspreset

x

Note asynchronousreset

y

z

Block diagram of Xilinx Spartan-3 FPGA

Each Spartan-3 CLB contains four CLB slices

Left-hand SliceSLICEM

Top of Left-hand Slice SLICEM

16 x 1 SRAM Lookup Table

Look Up Tables

Capacity is limited by number of inputs, not complexity

Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM

• Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB

• Example:

A B C D Z

0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1 . . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

Look Up Table

Combinatorial Logic

AB

CD

Z

4-bit address

GFunc.Gen.

G4G3G2G1

WE

2(2 )4

= 64K !

Center of Left-hand Slice SLICEM

Bottom of Left-hand Slice SLICEM

Xilinx Spartan-3 FPGAs

Block RAM

Digital Clock Manager (DCM)

Delay-Locked Loop (DLL)

Virtex FPGAs

For info on Virtex 1000 boards, seehttp://www.zarx.info/

Virtex-II FPGAs

Virtex-II Pro FPGAs

CPLDs vs. FPGAs

Virtex-4 FPGAs

implementing digital circuits lecture l3.1. implementing digital circuits transistors and integrated...

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