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Impact of SiOC Low K Materials on DualDamascene Patterning

Impact of SiOC Low K Materials on DualDamascene Patterning

Gary Ray, Ph.D Steve LassigDirector, Integration Sr. Manager, IntegrationNovellus Systems, Inc. Lam Research, Inc.

Gary Ray, Ph.D Steve LassigDirector, Integration Sr. Manager, IntegrationNovellus Systems, Inc. Lam Research, Inc.

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AcknowledgementAcknowledgement

The members of the integration organizations ofLam Research, Inc. and Novellus Systems, Inc.

The members of the integration organizations ofLam Research, Inc. and Novellus Systems, Inc.

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Presentation OutlinePresentation Outline

➤ Dual damascene process flow.➤ Dual damascene etch challenges.➤ Photoresist poisoning.➤ Trench etch.➤ Via etch.➤ Trench-over-via etch.➤ Barrier open etch.➤ Summary

➤ Dual damascene process flow.➤ Dual damascene etch challenges.➤ Photoresist poisoning.➤ Trench etch.➤ Via etch.➤ Trench-over-via etch.➤ Barrier open etch.➤ Summary

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Dual Damascene Process FlowVia First

Cu CMPTa(N) CMP

dielectric buff CMPpost-CMP clean

Cu

PR stripwet clean

Cu

surface treatment

Cu

dielectric CVDCu

Resist Resist

via lithographyCu

Resist Resist

via etchCu

Resist

line lithographyCu

BARC

Resist Resist

line etchCu

BARC

Resist

PR stripwet clean

barrier open

Cu

precleanPVD Ta(N) barrier

Cu

PVD Cu seedCu

Cu Electrofillanneal

Cu

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Dual Damascene Etch ChallengesDual Damascene Etch Challenges

➤ Profile control➤ Trench bottom profile➤ Striations

➤ Etch selectivity

➤ Microloading

➤ No endpoint

➤ Uniformity

➤ Veils

➤ Strips selective to dielectrics

➤ k increase

General Dual Damascene Etch Challenges CVD SiOC Low k Film Issues➤ Carbon content➤ Chemical reactivity➤ Reduced density

Cu

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DUV Resist PoisoningDUV Resist Poisoning

➤ Amines poison DUV photoresist, preventing development.➤ Amines enter dielectric stacks from a number of sources.➤ The phenomenon has been reported for most classes of low k films.➤ Amines diffuse rapidly in low density low k films.

➤ Amines poison DUV photoresist, preventing development.➤ Amines enter dielectric stacks from a number of sources.➤ The phenomenon has been reported for most classes of low k films.➤ Amines diffuse rapidly in low density low k films.

poisoned resist

X-section view

via structureafter trenchlithography

After trench etch.

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DUV Resist PoisoningDUV Resist Poisoning

➤ Nitrogen in dielectric deposition processes (N2O, NH3) is theprimary cause of DUV resist poisoning.

➤ Nitrogen can enter SiOC layers during barrier film pre-deposition set-up steps and during the actual depositions.

➤ Etch and strip steps are of secondary importance at best.➤ The source material, as well as the reactor must not inject N2

into the process chamber.

➤ Nitrogen in dielectric deposition processes (N2O, NH3) is theprimary cause of DUV resist poisoning.

➤ Nitrogen can enter SiOC layers during barrier film pre-deposition set-up steps and during the actual depositions.

➤ Etch and strip steps are of secondary importance at best.➤ The source material, as well as the reactor must not inject N2

into the process chamber.ILD stack with NHx contamination NHx eliminated from stack

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Trench Etch - Metal 1Trench Etch - Metal 1

➤ Metal 1 trench etch is the least demanding process.• Low aspect ratios.• Etch stops used.

➤ M1 Etch Issues• CD control.• Profile control.• Microloading.• Uniformity.• Selectivity to barrier film.

➤ Followed by barrier open step to expose W plugs.

➤ Metal 1 trench etch is the least demanding process.• Low aspect ratios.• Etch stops used.

➤ M1 Etch Issues• CD control.• Profile control.• Microloading.• Uniformity.• Selectivity to barrier film.

➤ Followed by barrier open step to expose W plugs.

SiC

SiOC

SiCCu

M1 Lines in SiOC low k film.

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Trench Etch - Metal 1Electrical Data versus Process PerformanceTrench Etch - Metal 1Electrical Data versus Process Performance

SiC

SiOC

SiCCu

M1 lines in SiOC low k film.Optimized process.

SiC

SiOC

SiC

Cu

M1 lines in SiOC low k film.Bowing and cusping.

Optimized process

Optimized process

10

12

14

16

18

20

0 5 10 15 20 25 30 35 40

M1

serp

. res

ista

nce

(k)

56789

101112131415

0 5 10 15 20 25 30 35 40

M1

com

b ca

paci

tanc

e (p

F)

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Via Etch ChallengesEtch StopVia Etch ChallengesEtch Stop

➤ The carbon content of CVD SiOC films can cause “etch stop.”• Attainable etch depth is dependent on etch selectivity.• Multi-step via etches are often employed.• Independent control of plasma density and ion energy is desirable.

➤ The carbon content of CVD SiOC films can cause “etch stop.”• Attainable etch depth is dependent on etch selectivity.• Multi-step via etches are often employed.• Independent control of plasma density and ion energy is desirable.

Resist

ARL

Coral

SiC:H

0.25 Via “etch-stopped”at a depth of ~0.6µm

0

5

10

15

20

1 1.2 1.4 1.6

etch stop depth, µm

Cor

al:b

arrie

r sel

ectiv

ity

SiNSiC

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Via Etch ChallengesChemical ReactivityVia Etch ChallengesChemical Reactivity

➤ The Si-CH3 groups in CVD SiOC films are susceptible toattack by fluorine and oxygen atoms.

➤ Protective polymer thickens toward the via bottoms.➤ Overetch process must be optimized for minimal bowing.

➤ The Si-CH3 groups in CVD SiOC films are susceptible toattack by fluorine and oxygen atoms.

➤ Protective polymer thickens toward the via bottoms.➤ Overetch process must be optimized for minimal bowing.

Resist

ARL

Coral

SiC:H

0.25 Via etched to adepth of 1.0µm

Via bowing caused byoveretch step.

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Trench-over-Via Etch: The most demandingprocess.Trench-over-Via Etch: The most demandingprocess.

Many demands must be metsimultaneously.

➤ Trench profile and CDcontrol.

➤ Smooth trench bottom.➤ Protection of barriers in vias.➤ Via profile maintenance.➤ Control of “terracing” and

veil formation.

Many demands must be metsimultaneously.

➤ Trench profile and CDcontrol.

➤ Smooth trench bottom.➤ Protection of barriers in vias.➤ Via profile maintenance.➤ Control of “terracing” and

veil formation.

SiO2

SiOC

SiC

Progression of T/V etch in 0.25µm via chain feature,Resist and I-line plugs have been stripped in-situ.

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Trench-over-Via Etch: Barrier ProtectionTrench-over-Via Etch: Barrier Protection

➤ Dual damascene processes with oxide or FSG ILDsoften rely on spin-on “BARCs” to protect etchstop/diffusion barriers.

➤ SiOC:barrier selectivity is too low for this scheme towork.

➤ Dual damascene processes with oxide or FSG ILDsoften rely on spin-on “BARCs” to protect etchstop/diffusion barriers.

➤ SiOC:barrier selectivity is too low for this scheme towork.

After M2 Lithography

PRSiO2SiOCSiCSiOCSiC

After BARC etch

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Trench-over-Via Etch: Barrier ProtectionTrench-over-Via Etch: Barrier Protection

➤ An alternative is to form thick plugs oforganic material in the vias.• Trench etch may be optimized for trench

properties rather than selectivity tobarrier.

• Via profile can be maintained withoutetch stop layer.

• Veils and terraces may also becontrolled.

➤ Control of plug height is important.

➤ An alternative is to form thick plugs oforganic material in the vias.• Trench etch may be optimized for trench

properties rather than selectivity tobarrier.

• Via profile can be maintained withoutetch stop layer.

• Veils and terraces may also becontrolled.

➤ Control of plug height is important.

I-line resist Spin Plug Etch

Trench Litho Trench Etch

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Trench-over-Via Etch: No trench etch stoplayer.Trench-over-Via Etch: No trench etch stoplayer.

➤ Advanced dual damasceneprocesses do not use etchstop layers.• Reduced cost.• Reduced effective k.

➤ Trench bottom profile anddepth control challenging.

➤ Via profile protectionchallenging.• Low density SiOC films

sputter more easily.

➤ Advanced dual damasceneprocesses do not use etchstop layers.• Reduced cost.• Reduced effective k.

➤ Trench bottom profile anddepth control challenging.

➤ Via profile protectionchallenging.• Low density SiOC films

sputter more easily.

PRSiO2SiOCSiC

SiO2SiOCSiC

Vias in SiOC films taperrapidly during trenchetch.

FSG DD withSiN trenchstop layer.

FSG DD withouttrench stop layer.

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0.25µ 0.50µVia chains

An Optimized Process FlowTrench etch, deveil, resist strip, barrier open in-situ.

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Various trench dimensions over 0.25µ vias

An Optimized Process FlowTrench etch, deveil, resist strip, barrier open in-situ.

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Barrier Open Etch: Profile AlterationBarrier Open Etch: Profile Alteration

➤ Seemingly simple etch, however excessive sputterenhanced feature tapering can• Alter CDs• Reduce yield

➤ Seemingly simple etch, however excessive sputterenhanced feature tapering can• Alter CDs• Reduce yield

SiC barrier etch with excessive SiOC tapering.

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Barrier Open Etch: UndercutBarrier Open Etch: Undercut

➤ Isotropic barrier open processes compromise• Barrier and seed step coverage.• ECD copper fill.

➤ Isotropic barrier open processes compromise• Barrier and seed step coverage.• ECD copper fill.

Directional barrier etch allowsgood via fill by ECD Cu.

Isotropic barrier etch causespoor barrier/seed step coverage

and voids in ECD Cu.

Vias with Cu voids fail duringnormal thermal cycling.

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Dual Damascene Electrical DataDual Damascene Electrical Data

56789

101112131415

0 10 20 30 40 50 60

M1

com

b ca

paci

tanc

e (p

F)

Target value - 8.5 pF56789

101112131415

0 10 20 30 40 50 60 70 80 90

M2

com

b ca

paci

tanc

e (p

F)

Target value - 8.0 pF

0.25 µm 2-level Metal Structures

Pt Coating

ViaM2

M1

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SummarySummary

➤ The introduction of the dual damascene architectureeliminated old challenges,• Aluminum etch• Dielectric gap fill

➤ And replaced them with the new dielectric etchchallenges that were discussed here.

➤ New challenges are here,• 193nm photoresist• Thinner barriers• Porous dielectrics

➤ The introduction of the dual damascene architectureeliminated old challenges,• Aluminum etch• Dielectric gap fill

➤ And replaced them with the new dielectric etchchallenges that were discussed here.

➤ New challenges are here,• 193nm photoresist• Thinner barriers• Porous dielectrics