imag€¦ · motivationapplication modeldeployment using smtsymmetry eliminationdistributed memory...

Motivation Application Model Deployment using SMT Symmetry elimination Distributed memory scheduling SMT Solving Conclusions

Mapping and Scheduling StreamingApplications using SMT Solvers

Pranav Tendulkar

Supervisors:Dr. Oded Maler Dr. Peter Poplavko

Verimag, FRANCE

13 October 2014

Tendulkar Mapping/scheduling for many-core 1 / 52

Multi-core Processors Everywhere

Phones

Space-shuttle

Tablets Laptops

Cameras

Smart-TV

source : http://www.csl.cornell.edu/courses/ece5745/handouts.html

Multi-core systems

How To:

Deploy the application to the platform

Decide number of processors to use?

Allocate tasks to processors and schedule them

Multi-core systems

How To:

Multi-core systems

How To:

Multi-core systems

How To:

Our Deployment Framework

Constraints

Performance

Platform Model

Application Model

OptimizationTechniques

CodeSolution

Constraints

Performance

Platform ModelApplication Model

CodeSolution

Constraints

Performance

CodeSolution

Constraints

Performance

CodeSolution

Constraints

Performance

Solution

Constraints

Performance

CodeSolution

Application Model

Task Graph

Tasks : Software procedure

Edges : Precedence relationsannotated with execution time

Application Model

Task Graph

Edges : Precedence relationsannotated with execution time

Application Model

Task Graph

Edges : Precedence relations

annotated with execution time

Application Model

Task Graph

annotated with execution time

Deployment Problem

Task Graph

Deployment Solution

C F E D H J

A B G I

Mapping : Task⇒ Processor

Scheduling : Task⇒ Time

Deployment Problem

Task Graph

Deployment Solution

C F E D H J

A B G I

Deployment Problem

Task Graph

Deployment Solution

C F E D H J

A B G I

Deployment Problem

Solution1:

C F E D H J

A B G I

Solution2:

A B C D E F G H I J

Deployment Problem

Solution1:

C F E D H J

A B G I

Solution2:

A B C D E F G H I J

Solution space is large

Deployment problem

How to:find optimal solutions in exponential design space.

model complex hardware which has Processors, Network, DMA

evaluate multiple criteriaLatencyMemory usedProcessors used...

Deployment problem

Outline

1 Motivation

2 Application Model

3 Deployment using SMT

4 Symmetry elimination

5 Distributed memory scheduling

6 SMT Solving

7 Conclusions

Overview

1 Motivation

2 Application Model

6 SMT Solving

7 Conclusions

Model of Computation

Synchronous Dataflow graphs (SDF)by Edward Lee and David Messerschmitt in 1987

represents Streaming Applications

Computation

Input output

Computation

Input output

Computation

Input output

Synchronous DataFlow

images images

Pre Blur Post

SDF Graph

4 1 1 4

Task Graph

Actors

Pre Blur Post

SDF Graph

4 1 1 4Pre Blur Post

Task Graph

Actors

Pre Blur Post

SDF Graph

4 1 1 4

Task Graph

Actors

Pre Blur Post

SDF Graph

4 1 1 4

Task Graph

Actors

Pre Blur Post

SDF Graph

4 1 1 4

Task Graph

Actors

Actor Blur is compact representation of data parallel tasks.

All Blur tasks have same properties such as execution time.

Pre Blur Post

SDF Graph

4 1 1 4

Task Graph

Actors

Actor Blur is compact representation of data parallel tasks.All Blur tasks have same properties such as execution time.

Split-Join Graphswe use split-join graphs : restriction of SDF

still covering perhaps 90% of use cases in the literature

a simple example:

A B Cα 1/α

α : spawn and split

1/α: wait and join

Bα−1

a simple example:

A B Cα 1/α

1/α: wait and join

Bα−1

a simple example:

A B Cα 1/α

1/α: wait and join

Bα−1

Restrictions compared to general SDF

Split-join does not support:

Stateful actors

Non-proportional rates

Initial tokens and cyclic paths

Stateful actors

A B2 3

Stateful actors

A B2 3

Overview

1 Motivation

2 Application Model

6 SMT Solving

7 Conclusions

SATisfiability solver (SAT / SMT)

Boolean variablesin0, in1, in2 ...out0, out1, out2 ...

Constraintsout0 = in0 ∨ in1 ⊕ in2 ...

SAT solver

variables

constraints

out0 = true&

out1 = trueUNSAT

out0 = false&

out1 = trueSAT

in0 = true,in1 = false, ...

SAT solver

variables

constraints

out0 = true&

out1 = trueUNSAT

out0 = false&

out1 = trueSAT

SAT solver

variables

constraints

out0 = true&

out1 = trueUNSAT

out0 = false&

out1 = trueSAT

SAT solver

variables

constraints

out0 = true&

out1 = trueUNSAT

out0 = false&

out1 = trueSAT

SAT solver

variables

constraints

out0 = true&

out1 = true

UNSATout0 = false

&out1 = true

SATin0 = true,

in1 = false, ...

SAT solver

variables

constraints

out0 = true&

out1 = trueUNSAT

out0 = false&

out1 = trueSAT

SAT solver

variables

constraints

out0 = true&

out1 = trueUNSAT

out0 = false&

out1 = true

SATin0 = true,

in1 = false, ...

SAT solver

variables

constraints

out0 = true&

out1 = trueUNSAT

out0 = false&

out1 = trueSAT

SAT solver

variables

constraints

out0 = true&

out1 = trueUNSAT

out0 = false&

out1 = trueSAT

SMT extends SAT by numeric variables and constants

Encoding deployment with constraints

Task Graph

Actor A B CTasks A0 B0 B1 B2 B3 C0

Description Variables

Start time xA0 xB0 xB1 xB2 xB3 xC0

Allocated proc. pA0 pB0 pB1 pB2 pB3 pC0

Duration dA dB dC

Precedence ConstraintsxB0 ≥ (xA0 + dA)

Mutual Exclusion Constraintsif (pB1 = pB2) then

xB1 ≥ (xB2 + dB) ∨ xB2 ≥ (xB1 + dB)

Latency CostLatency = (xC0 + dC)

Task Graph

Description VariablesStart time xA0 xB0 xB1 xB2 xB3 xC0

Duration dA dB dC

xB1 ≥ (xB2 + dB) ∨ xB2 ≥ (xB1 + dB)

Task Graph

Duration dA dB dC

xB1 ≥ (xB2 + dB) ∨ xB2 ≥ (xB1 + dB)

Task Graph

Duration dA dB dC

xB1 ≥ (xB2 + dB) ∨ xB2 ≥ (xB1 + dB)

Task Graph

Duration dA dB dC

xB1 ≥ (xB2 + dB) ∨ xB2 ≥ (xB1 + dB)

Task Graph

Duration dA dB dC

xB1 ≥ (xB2 + dB) ∨ xB2 ≥ (xB1 + dB)

Task Graph

Duration dA dB dC

xB1 ≥ (xB2 + dB) ∨ xB2 ≥ (xB1 + dB)

A0 B0 B2

B1 B3 C0

Latency

Multi-criteria Problem

A0 B0 B2

B1 B3 C0

Latency = 4#Proc = 2

Latency

(3,4)Pareto Set

A0 B0 B2

B1 B3 C0

Latency

Pareto Set

A0 B0 B2

B1 B3 C0

Latency

Pareto Set

Conflicting Criteria

A0 B0 B2

B1 B3 C0

Latency

(3,4)Pareto Set

Problem Monotonicity

Upper Bound UpperB

Latency

A0 B0 B2

B1 B3 C0

Upper Bound UpperB

Latency

A0 B0 B2

B1 B3 C0

Upper Bound UpperB

Latency

A0 B0 B2

B1 B3 C0

Upper Bound UpperB

Latency

Not Possible

Upper Bound UpperB

Latency

Not Possible

Also Not Possible

Upper Bound UpperB

Latency

Not Possible

Also Not Possible

Upper Bound UpperB

Latency

Design Space Exploration

Split-join Graph

SMT Constraints SMT Solver

Design SpaceExploration Algorithm

costconstraints

solutions

(x1, y1)

(x2, y2)

(x3, y3)

?TIMEOUT

Timeout:Cannot decide SAT / UNSAT in a given TIME-BUDGET.

Split-join Graph

SMT Constraints

SMT Solver

costconstraints

solutions

(x1, y1)

(x2, y2)

(x3, y3)

?TIMEOUT

Split-join Graph

costconstraints

solutions

(x1, y1)

(x2, y2)

(x3, y3)

?TIMEOUT

Split-join Graph

costconstraints

solutions

(x1, y1)

(x2, y2)

(x3, y3)

?TIMEOUT

Split-join Graph

costconstraints

solutions

(x1, y1)

(x2, y2)

(x3, y3)

?TIMEOUT

Split-join Graph

costconstraints

solutions

(x1, y1)

(x2, y2)

(x3, y3)

?TIMEOUT

Split-join Graph

costconstraints

solutions

(x1, y1)

(x2, y2)

(x3, y3)

?TIMEOUT

Split-join Graph

costconstraints

solutions

(x1, y1)

(x2, y2)

(x3, y3)

?TIMEOUT

Split-join Graph

costconstraints

solutions

(x1, y1)

(x2, y2)

(x3, y3)

?TIMEOUT

Exploration Algorithm

Divide cost space using grids

One SMT query per point on the grid

Finer grid after every iteration

Don’t query in known area

sat points unsat points not yet explored points

Overview

1 Motivation

2 Application Model

6 SMT Solving

7 Conclusions

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

all instances of actor C are similar (symmetric)

No change in latency !

Huge number of such symmetric solutions

Add constraints to eliminate all but one

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

a lexicographic schedule

B1 C01 C10 C11 D1 E

A0 B0 C00 D0

lexicographic order : C00 � C01 � C10 � C11

enforce lexicographic order in schedule:s(u) ≤ s(u′) for u� u′

s(C00) ≤ s(C01) ≤ s(C10) ≤ s(C11)

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

B1 C01 C10 C11 D1 E

A0 B0 C00 D0

s(C00) ≤ s(C01) ≤ s(C10) ≤ s(C11)

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

B1 C01 C10 C11 D1 E

A0 B0 C00 D0

s(C00) ≤ s(C01) ≤ s(C10) ≤ s(C11)

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

B1 C01 C10 C11 D1 E

A0 B0 C00 D0

s(C00) ≤ s(C01) ≤ s(C10) ≤ s(C11)

Task Symmetry

task graph

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

B1 C01 C10 C11 D1 E

A0 B0 C00 D0

s(C00) ≤ s(C01) ≤ s(C10) ≤ s(C11)

Task Symmetry : Theorem

Lexicographic Schedule

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

Theorem : Every group has a lexicographic schedule

Corollary : No feasible cost is lost

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

a schedule

B1 C10 C01 C00 D0 E0

A0 B0 C11 D1

C01 C00

a permuted schedule

B1 C10 C00 C01 D0 E0

A0 B0 C11 D1

C00 C01

Processor Symmetry

task graph

B0 C00

schedule

B0 C00

swapped P1 and P2

Processor Symmetry

task graph

B0 C00

schedule

B0 C00

swapped P1 and P2

Processor Symmetry

task graph

B0 C00

schedule

B0 C00

swapped P1 and P2

Pareto Exploration

0 5 10 15 20 25 30

Latency

Sat Points Unsat Points Pareto Curve

without symmetry breaking

0 5 10 15 20 25 30

Latency

with symmetry breaking

0 8 16 24 32 40 48 56

Takes no time Times out

Exploration : Processors vs Latency α = 30

Solver PerformanceTimeouts reduce !The gap between SAT and UNSAT points is smaller.

Pareto Exploration

0 5 10 15 20 25 30

Latency

0 5 10 15 20 25 30

Latency

0 8 16 24 32 40 48 56

Pareto Exploration

0 5 10 15 20 25 30

Latency

0 5 10 15 20 25 30

Latency

0 8 16 24 32 40 48 56

Pareto Exploration

0 5 10 15 20 25 30

Latency

0 5 10 15 20 25 30

Latency

0 8 16 24 32 40 48 56

Solver PerformanceTimeouts reduce !The gap between SAT and UNSAT points is smaller.Tendulkar Mapping/scheduling for many-core 30 / 52

Video Decoder3D cost space (CL,CP ,CB) exploration, CB - total buffer size

MPEG video decoder:

122 Tasks

Latency(.10 3)

Buffer

[5,367,91]

[24,276,1]

[14,276,122]

[14,333,62]

[10,323,122]

[17,182,122]

[7,205,122]

[24,182,1]

[19,182,31]

[10,229,31]

With symmetry Without symmetry

Better Pareto points in same TIME-Budget !

MPEG video decoder:

122 TasksLatency(.10 3)

Buffer

[5,367,91]

[24,276,1]

[14,276,122]

[14,333,62]

[10,323,122]

[17,182,122]

[7,205,122]

[24,182,1]

[19,182,31]

[10,229,31]

MPEG video decoder:

Buffer

[5,367,91]

[24,276,1]

[14,276,122]

[14,333,62]

[10,323,122]

[17,182,122]

[7,205,122]

[24,182,1]

[19,182,31]

[10,229,31]

Latency(.10 3)

Buffer

[5,367,91]

[24,276,1]

[14,276,122]

[14,333,62]

[10,323,122]

[17,182,122]

[7,205,122]

[24,182,1]

[19,182,31]

[10,229,31]

Latency(.10 3)

24Buff

erSize

[5,367,91]

[24,276,1]

[14,276,122]

[14,333,62]

[10,323,122]

[17,182,122]

[7,205,122]

[24,182,1]

[19,182,31]

[10,229,31]

MPEG video decoder:

Buffer

[5,367,91]

[24,276,1]

[14,276,122]

[14,333,62]

[10,323,122]

[17,182,122]

[7,205,122]

[24,182,1]

[19,182,31]

[10,229,31]

Better Pareto points

in same TIME-Budget !

MPEG video decoder:

Buffer

[5,367,91]

[24,276,1]

[14,276,122]

[14,333,62]

[10,323,122]

[17,182,122]

[7,205,122]

[24,182,1]

[19,182,31]

[10,229,31]

Distributed memory scheduling

So far we ignored the communication costs

For distributed memory, communication needs to be modeled

Distributed memory scheduling

So far we ignored the communication costs

For distributed memory, communication needs to be modeled

Overview

1 Motivation

2 Application Model

6 SMT Solving

7 Conclusions

Kalray MPPA-256512KB

QuadCore

USMC PCIe inter laken DDR

Interlaken

GPIOs PCIe interlaken

QuadCore

SharedMemory

D-NocRouter

syst.core

C-NocRouter

P10 P11

P12 P13

P14 P15

16 compute clusters16 processors2 MB Shared MemoryDMA

Toroidal 2D network

QuadCore

Interlaken

QuadCore

SharedMemory

D-NocRouter

syst.core

C-NocRouter

P10 P11

P12 P13

P14 P15

16 compute clusters

16 processors2 MB Shared MemoryDMA

Toroidal 2D network

QuadCore

Interlaken

QuadCore

SharedMemory

D-NocRouter

syst.core

C-NocRouter

P10 P11

P12 P13

P14 P15

16 compute clusters

16 processors2 MB Shared MemoryDMA

Toroidal 2D network

QuadCore

Interlaken

QuadCore

SharedMemory

D-NocRouter

syst.core

C-NocRouter

P10 P11

P12 P13

P14 P15

16 compute clusters16 processors

2 MB Shared MemoryDMA

Toroidal 2D network

QuadCore

Interlaken

QuadCore

SharedMemory

D-NocRouter

syst.core

C-NocRouter

P10 P11

P12 P13

P14 P15

16 compute clusters16 processors2 MB Shared Memory

Toroidal 2D network

QuadCore

Interlaken

QuadCore

SharedMemory

D-NocRouter

syst.core

C-NocRouter

P10 P11

P12 P13

P14 P15

Toroidal 2D network

QuadCore

Interlaken

QuadCore

SharedMemory

D-NocRouter

syst.core

C-NocRouter

P10 P11

P12 P13

P14 P15

Toroidal 2D network

The problem?

Which cluster to allocate?

Which processor to allocate?

Connected tasks in same or different cluster?

Communicating tasks if to be added, which DMA?

And the constraintsPrecedence

Mutual Exclusion

For 10 tasks, 256 processors,

1.20892582× 1024 potential solutions!

The problem?

Which cluster to allocate?

Which processor to allocate?

Connected tasks in same or different cluster?

Communicating tasks if to be added, which DMA?

And the constraintsPrecedence

Mutual Exclusion

For 10 tasks, 256 processors,

1.20892582× 1024 potential solutions!

Split the problem into sub-problems.

Design FlowApplication

Partitioning

Placement

Multi-clusterScheduling

Partitioning

Placement

Group the Actors

Partitioning

Placement

Group the Actors

GoalsLoad balance the groupsMinimize data exchange

Partitioning

Placement

Place the Groups

Partitioning

Placement

Place the Groups

GoalsMinimize distance between communicating groups

Partitioning

Placement

transfer

ScheduleTasks

Transfer

Partitioning

Placement

transfer

ScheduleTasks

Transfer

GoalsMinimize LatencyMinimize Buffer size

Output of Design Flow

Tasks and Transfers

Cluster Mapping

Processor and DMA Mapping

Start time

EdgesCommunication buffer size

ApplicationLatency

Tasks and TransfersCluster Mapping

Start time

ApplicationLatency

Start time

ApplicationLatency

Start time

ApplicationLatency

Start time

ApplicationLatency

Start time

ApplicationLatency

DMA Model

Tasks communicating via DMA:

A I G B

Task Description Resources used Task duration

I Initialization Processor and DMA Constant

G Network Transfer Only DMA Transfer size dependent

DMA Model

A I G B

DMA Model

A I G B

DMA Model

A I G B

Model TransformationAn example application graph:

A B[α, ω]

Partition-Aware graph:

A Iwr Gwr Bewt : [1, w

↑] ewn : [1] ert : [α, ω]

Buffer-Aware graph:

A Iwr Gwr

IrdGrd

ewt : [1, w↑] ewn : [1] ert : [α, ω]

ews: [1]

ewb : [1, 0, b(e

e rs:[1]

ern : [1]

erb : [α −1

, 0, b(ert )]

DMA : Data

DMA : flow-controlDMA-Completion

A B[α, ω]

↑] ewn : [1] ert : [α, ω]

Buffer-Aware graph:

A Iwr Gwr

IrdGrd

ewt : [1, w↑] ewn : [1] ert : [α, ω]

ews: [1]

ewb : [1, 0, b(e

e rs:[1]

ern : [1]

erb : [α −1

, 0, b(ert )]

DMA : Data

A B[α, ω]

↑] ewn : [1] ert : [α, ω]

Buffer-Aware graph:

A Iwr Gwr

IrdGrd

ewt : [1, w↑] ewn : [1] ert : [α, ω]

ews: [1]

ewb : [1, 0, b(e

e rs:[1]

ern : [1]

erb : [α −1

, 0, b(ert )]

DMA : Data

A B[α, ω]

↑] ewn : [1] ert : [α, ω]

Buffer-Aware graph:

A Iwr Gwr

IrdGrd

ewt : [1, w↑] ewn : [1] ert : [α, ω]

ews: [1]

ewb : [1, 0, b(e

e rs:[1]

ern : [1]

erb : [α −1

, 0, b(ert )]

DMA : Data

A B[α, ω]

↑] ewn : [1] ert : [α, ω]

Buffer-Aware graph:

A Iwr Gwr

IrdGrd

ewt : [1, w↑] ewn : [1] ert : [α, ω]

ews: [1]

ewb : [1, 0, b(e

e rs:[1]

ern : [1]

erb : [α −1

, 0, b(ert )]

DMA : Data

A B[α, ω]

↑] ewn : [1] ert : [α, ω]

Buffer-Aware graph:

A Iwr Gwr

IrdGrd

ewt : [1, w↑] ewn : [1] ert : [α, ω]

ews: [1]

ewb : [1, 0, b(e

e rs:[1]

ern : [1]

erb : [α −1

, 0, b(ert )]

DMA : Data

DMA : flow-control

DMA-Completion

A B[α, ω]

↑] ewn : [1] ert : [α, ω]

Buffer-Aware graph:

A Iwr Gwr

IrdGrd

ewt : [1, w↑] ewn : [1] ert : [α, ω]

ews: [1]

ewb : [1, 0, b(e

e rs:[1]

ern : [1]

erb : [α −1

, 0, b(ert )]

DMA : Data

JPEG Decoder Example

VLD IQ/IDCT COLOR

VLD : Variable Length Decoder

IQ / IDCT : Inverse Quantization / Inverse Discrete Cosine Transform

Color : Color Conversion

VLD IQ/IDCT COLOR

JPEGDecoder

Partitioning

Placement

Partitioning

Placement

Partitioning Solutions:

Cz : No. of Groups

Cη : Total communication cost

Cτ : Max. workload per group

Allocated group Exploration CostSolution vld iq color Cz Cη Cτ

Ps0 0 1 2 3 12384 424012Ps1 0 0 1 2 2736 758116Ps2 0 0 0 1 0 934288Ps3 0 1 1 2 9648 510276

Scheduling Solutions:

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

Ps0 Ps1 Ps2 Ps3

JPEGDecoder

Partitioning

Placement

Partitioning

Placement

Cz : No. of Groups

Ps0 0 1 2 3 12384 424012Ps1 0 0 1 2 2736 758116Ps2 0 0 0 1 0 934288Ps3 0 1 1 2 9648 510276

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

Ps0 Ps1 Ps2 Ps3

JPEGDecoder

Partitioning

Placement

Partitioning

Placement

Cz : No. of Groups

Ps0 0 1 2 3 12384 424012Ps1 0 0 1 2 2736 758116Ps2 0 0 0 1 0 934288Ps3 0 1 1 2 9648 510276

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

Ps0 Ps1 Ps2 Ps3

JPEGDecoder

Partitioning

Placement

Partitioning

Placement

Cz : No. of Groups

Ps0 0 1 2 3 12384 424012Ps1 0 0 1 2 2736 758116Ps2 0 0 0 1 0 934288Ps3 0 1 1 2 9648 510276

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

Ps0 Ps1 Ps2 Ps3

JPEGDecoder

Partitioning

Placement

Partitioning

Placement

Cz : No. of Groups

Ps0 0 1 2 3 12384 424012Ps1 0 0 1 2 2736 758116Ps2 0 0 0 1 0 934288Ps3 0 1 1 2 9648 510276

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

Ps0 Ps1 Ps2 Ps3

JPEGDecoder

Partitioning

Placement

Partitioning

Placement

Cz : No. of Groups

Ps0 0 1 2 3 12384 424012Ps1 0 0 1 2 2736 758116Ps2 0 0 0 1 0 934288Ps3 0 1 1 2 9648 510276

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

Ps0 Ps1 Ps2 Ps3

JPEG decoder latency measured on Kalray platform

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

model measured-min. measured-max.

Maximum prediction error of 9%

JPEG decoder latency measured on Kalray platform

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

0.4 0.5 0.6 0.7 0.8 0.9 1

Latency (cycles)

model measured-min. measured-max.

Maximum prediction error of 9%

StreamIt Benchmarks

tion Sor

Dct1 Dct2 Dct3 Dct4 Dct5 Dct6 Dct7 Dct8

DctCoa

DctFine

Matrix

#Solutions %error

StreamIt Benchmarks

tion Sor

Dct1 Dct2 Dct3 Dct4 Dct5 Dct6 Dct7 Dct8

DctCoa

DctFine

Matrix

#Solutions %error

Overview

1 Motivation

2 Application Model

6 SMT Solving

7 Conclusions

Lessons learnt from SMT solver

lower bound upper boundoptimal

lower bound upper boundoptimal SAT

TIMEOUT

foundoptimal

TIMEOUT

foundoptimal

TIMEOUT

foundoptimal

TIMEOUT

foundoptimal

P3 Optimized Schedule

Such constraints makes the problem harder for SMT

Two-step optimization

Get a loose schedule from the solver

Optimize it for:LatencyProcessors used

Upper Bound UpperB

LatencyP

LooseSolution

Upper Bound UpperB

LatencyP

LooseSolution

Upper Bound UpperB

LatencyP

LooseSolution

optimized

Upper Bound UpperB

LatencyP

LooseSolution

optimized

Overview

1 Motivation

2 Application Model

6 SMT Solving

7 Conclusions

Conclusions and Future Work

Conclusions:

Symmetry elimination finds better solutions

Combined Optimization with Communication modeling

Automated design flow for distributed memory

Conclusions:

References

P. Tendulkar, P. Poplavko, and O. Maler. “Symmetry Breaking forMulti-criteria Mapping and Scheduling on Multicores”. In:FORMATS. 2013

P. Tendulkar, P. Poplavko, I. Galanommatis, and O. Maler.“Many-Core Scheduling of Data Parallel Applications using SMTSolvers”. In: DSD. 2014

P. Tendulkar, P. Poplavko, and O. Maler. Strictly PeriodicScheduling of Acyclic Synchronous Dataflow Graphs using SMTSolvers. Tech. rep. Verimag Research Report, 2014

Thank You

Questions?

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