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III B.Tech. IISem (R15) ECE : Microprocessors and Microcontrollers : UNIT -1 1

UNIT – 1

• Introduction • 8086 Architecture-Block Diagram• Register Organization• Flag Register• Pin Diagram• Timing and Control Signals• System Timing Diagrams,• Memory Segmentation• Interrupt structure of 8086 and Interrupt Vector Table.• Memory organization and memory banks accessing.

INTRODUCTION TO MICROPROCESSORS:

A simple block diagram for microcomputer is shown in fig.1.The major parts are the CPU, memory, and input and output circuitry or I/O. Three sets of parallel lines are used to connect these parts are called buses. The buses are the address bus, the data bus, and the control bus.

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Memory: It is a medium that stores binary information. The memory section usually consists of a mixture of RAM and ROM. It may also have magnetic floppy disks, magnetic hard disks, or optical disks. Memory has two purposes .The first purpose is to store the binary code for the sequences instructions you want the computer to carry out. The second purpose of the memory is to store the binary coded data with which the computer is going to be working.

Input: It is a device that allows the computer to take in data from the outside world.

Output: It is a device that allows the computer to send date to the outside world.

Peripherals such as keyboards, video display terminals, printers, and modems are connected to the I/O section. These allow the user and the computer to communicate with each other. The actual physical devices used to interface the computer buses to external systems are often called Ports. An input port allows data from keyboard, an A/D converter, or some other source to be read into the computer under control of the CPU. An output port is used to send data from the computer to some peripheral, such as video display terminal printer, or a D/A converter.

CPU: The Central Processing Unit or CPU controls the operation of the computer. In a microcomputer the CPU is a microprocessor. The CPU or Microprocessor fetches binary ceded instructions from the memory, decodes the instructions into a series of simple actions, and carries out these actions in sequence of steps.

Address bus: The address bus consists of 16, 20, 24, or 32… parallel signal lines. These address lines are used to send a address of the memory location or a device address from the microprocessor unit to the memory or the peripheral. The address bus always unidirectional. Address always goes out of the microprocessor. The number of memory locations that the microprocessor can address is determined by the number of address lines. If the microprocessor has N address lines, then it can directly address 2N memory locations. For ex: a microprocessor with 16 address lines can address 216 or 65,536 memory locations.

Data bus: The data bus consists of 8,16,or 32…parallel lines .A group of lines used to transfer a data between the microprocessor and peripherals(or memory).The data bus is always bi-directional.

Control bus: The control bus consists of 4 to 10 parallel signal lines. The microprocessor sends out signals on the control bus to enable the outputs of addressed memory devices or port devices. Typical control bus signals are Memory Read, Memory Write, I/O Read, and I/O Write.

SOME IMPORTANT TERMS:

Microprocessor:It is a semiconductor device which is manufactured by using LSI or VLSI technology, which includes ALU, Control unit and a group of Registers in a single Integrated circuit.

Microcontroller: It is a device that includes microprocessor, memory, and I/O signal lines on a single chip, fabricated using VLSI technology.



Microcomputer: A digital computer having a microprocessor as its Central Processing Unit is called Microcomputer. So, a microprocessor combined with memory, an input device and an output device forms a microcomputer.

Bus: A group of wires or lines used to transfer bits between the microprocessor and other components of the computer system. Or a path used to carry signals, such as connection between memory and the microprocessor in a digital computer.

Hardware: The physical devices and circuitry of the computer is called Hardware.

Software: The programs written for the computer is referred to as software.

Firmware: The programs stored in ROMs or in other devices which permanently keep their stored information are referred as Firmware.

Ingeneral the width of the data bus is equal to the bit capacity of the microprocessor.

In general the internal architecture of the microprocessor depends on the bit capacity of the microprocessor.

Bit-a binary digit.0 or 1

Nibble-a group of four bits

Byte-a group of eight bits

Word-a group of 16 bits or a group of bits the computer recognizes and processes at a time.

Double word-a group of 32 bits.

Instruction: A command in binary that is recognized and executed by the computer to accomplish a task. Some instructions are designed with one word, and some require multiple words.

Mnemonic: A combination of letters to suggest the operation of an instruction.

Program: A set of instructions written in specific sequence for the computer to accomplish a given task.

Machine language: The binary medium of communication with a computer through a designed set of instructions specific to each computer.



Assembly language: A medium of communication with a computer in which programs are written in mnemonics.

Low-level language: A medium of communication that is machine-dependant or specific to a given computer.

The machine and the assembly languages of a computer are considered low level languages. Programs written in these languages are not transferable to different types of machines.

High-level language: A medium of communication that is independent of a given computer. Programs are written in English like words, and they can be executed on a machine using translator (a compiler or interpreter).

Source code: A program written either in mnemonics of as assembly language or in English like statements of high level language (before it is assembled or compiled).

Assembler: A computer program that translates an assembly language program from mnemonics to the binary machine code of a computer.

Compiler: A program that translates English-like words of a high level language into the machine language of a computer.

Interpreter: A program that translates the English –like statements of a high level language into the machine language of a computer.

Operating System: A set of programs that manages interaction between hardware and software.

ASCII: American Standard Code for Information Interchange. This is 7-bit alphanumeric code with 128 combinations.

ARCHITECTURE OF 8086 MICROPROCESSOR:

Features:Intel released its first 16-bit microprocessor 8086 in 1978.The Intel 8086 is a 16-bit processor ,which is fabricated using HMOS technology and it has 40 pins ,packaged in DIP .

It has 16-bit data bus & 20-bit address bus It can address 220 locations = 1 M bytes of memory It uses segmented memory The 8086 can generate 16-bit I/O address, hence it can access 216=65536 I/O ports. The 8086 provides fourteen 16-bit registers. The 8086 has multiplexed address and data bus which reduces the number of pins needed,

but does slow down the transfer of data. The 8086 requires clock with a 33% duty cycle to provide optimized internal timing. The 8086 microprocessor available in three clock rates: 5 MHz (8086), 8 MHz (8086-2) and

10 MHz (8085-1). The Intel 8086 is designed to operate in two modes: minimum mode and maximum mode.



Minimum mode: When only one 8086 CPU is to be used in a microcomputer system, the 8086 is used in the minimum mode of operation.

Maximum mode: More than one processor (multiprocessor) is used in the system, the 8086 is used in the maximum mode of operation.

An interesting feature of the 8086 is that it fetches up to 6 instruction bytes from memory and queue stores them in order to speed up instruction execution.

It requires +5V single power supply.

Architecture:The internal architecture of 8086 microprocessor is shown in figure below.As below by the

block diagram in figure, the 8086 processor is divided into two independent functional parts, the Bus Interfacing Unit (BIU), and the Execution Unit (EU). Dividing the work between these two units speeds up processing.



The BIU sends out addresses, fetches instructions from memory, reads data from ports and memory, and writes data to ports and memory. In other words, the BIU handles all transfers of data and addresses on the buses for the execution.

The EU of the 8086 tells the BIU where to fetch instructions or data from, decodes instructions, and executes instructions. 1. Bus Interfacing Unit: The bus interfacing unit in 8086 provides the interface to the outside world. This unit is responsible for performing all external bus operations like fetches instructions from memory, reads data from ports and memory, and writes data to ports and memory.

The queue: To speed up program execution, the BIU fetches six instruction bytes ahead of time from the memory. The BIU stores these perfected bytes in a first-in-first-out register set called a queue. When the EU is ready for its next instruction, it simply reads the instruction byte for the instruction from the queue in the BIU. This is much faster than sending out an address to the system memory and waiting for memory to send back the next instruction byte or bytes. The process is analogous to the way a bricklayer’s assistant fetches bricks ahead of time and keeps a queue of bricks lined up so that the brick layer can just reach out and grab a brick when necessary. Except in the cases of JMP and CALL instructions, where the queue must be damped and then reloaded starting from a new address. So, the queue operates on the principle first in first out (FIFO).So that the execution unit gets the instructions for execution in the order they are fetched. This prefetch-and-queue scheme greatly speeds up processing. Fetches the next instruction while the current instruction executes is called pipelining.20-bit Physical address Calculation :

The 20-bit Physical address is produced by adding Offset address to the Starting address of the segment.

For example, if CS= 2000H and IP= 5678H thenSegment base = CS*10 = 20000HOffset address = IP = 5678H

20-bit Physical address = Segment base + Offset = 25678H.

We represent the 20-bit Physical address in the form of Segment base : Offset = CS:IP = 2000:5678 H

2. Execution Unit: The EU of 8086 tells the BIU from where to fetch instructions or data, decodes instructions and executes instructions. As shown in figure, the EU contains: control unit, decoder, ALU and a registers. Control unit: This directs internal operations. Decoder: A decoder inthe EU translates instructions fetched from memory into a series of actions which the EU carries out.16-bit ALU: The EU consists of 16-bit ALU which can perform Arithmetic operations (such as Addition, Subtraction, Multiplication, Division, Increment, Decrement,….. ) and Logic operations (such as Logic AND, OR, NOT, Ex-OR, Shift, Rotate,…..etc).



REGISTER ORGANIZATION:

General purpose registers:

The EU has four 16-bit general purpose registers labeled as AX, BX, CX, and DX. These registers can be used temporary storage of 16 -bit data.

AX (Accumulator): The register AX is used to store the result produced by the ALU. So, it is called as Accumulator.

BX (Base Register): The register BX is used as offset storage for generating physical addresses in case of certain addressing modes.

CX (Counter Register): The register CX is used as default counter in case of string and loop instructions.

DX (Data Register): The register DX is used as destination (store the result data) in case of multiplication and division instructions.

Segment registers:

The segment registers in BIU are used to define the starting address of logical segment. It holds the upper 16-bits of starting address of logical segment.

There are 4- segment registers: 1. Code Segment register (CS)

2. Data Segment register (DS)

3. Extra Segment register(ES)

4. Stack Segment register(SS)

Code Segment register:

The CS register is used to hold the upper 16-bits of starting address of the Code segment. The BIU inserts ZERO’s for lower 4-bits of 20-bit starting address.

For example, if CS=2000H then the Code segment starts at 20,000H.



Data Segment register:

The DS register is used to hold the upper 16-bits of starting address of the Data segment. The BIU inserts ZERO’s for lower 4-bits of 20-bit starting address.

The data segment is a section of memory that contains data variables and constants of the program. Data are accessed from Data segment by an Offset address. The SI, DI, BX, BP registers are used to store the Offset address for data segment.

Extra Segment register:

The ES register is used to hold the upper 16-bits of starting address of the Extra segment. The Extra segment is an additional data segment used in String operations. The DI, SI, BX, BP registers are used to store the Offset address for extra segment.

Stack Segment register:

The SS register is used to hold the upper 16-bits of starting address of the Stack segment. The Stack segment defines the area of memory used for stack.

The Stack Pointer (SP) register holds the address of Stack top.

Instruction Pointer (IP):

The IP register holds the Offset address of the next instruction to be fetched from Code segment.

The Offset address/ Effective address is the distance of Operandfrom the Starting address of the Segment.

Flag registers:A flag is a flip-flop which indicates some condition produced by the execution of an instruction or controls certain operations of EU. The flag register contains nine active flags.

Flag Register:

Conditional Flags / Status Flags Indicate some condition produced by an instruction execution.

These flags are Set or Reset according to the condition produced after the execution of an instruction.

6- conditional flags CF, PF, AF, ZF, SF, OF



Control flags These flags control the operation of the processor.3- control flags DF, IF, TF

Conditional Flags:

CF : Carry Flag is set to 1 , if a carry is generated in an Addition (or) Subtraction

PF : Parity Flag is set to 1, if the result of an operation contains even number of 1’s

AF: Auxiliary carry Flag is set to 1, if addition of lower nibble generates a carry. It is used in BCD operations

ZF : Zero Flag is set to 1, if the result of an operation is ZERO.

SF : Sign Flag is used with signed numbers only. It is set to 1, if the MSB of the result is 1.

SF=1 for negative results and SF =0 for positive results.

OF: Overflow Flag is set to 1, if the result of an operation exceeds the register capacity.

Example : AX = 78H = 0111 1001 BX = 98H = 1001 1000

The status of flags, after the execution of ADD AX, BX

Control flags:

DF : Directional Flag is used in string operations to select increment/decrement mode for SI and DI

If DF = 1, The SI & DI registers are automatically decremented after the execution of every string instruction

If DF = 0, The SI & DI registers are automatically incremented after the execution of every string instruction IF: Interrupt Flag

If IF = 1, all the maskable interrupts are recognized by the CPU.Otherwise, the maskable interrupts are ignored/ not processed by CPU.

TF : Trap Flag is used for debugging purposeIf TF = 1, The processor enters the ‘ Single step execution mode ‘.

i.e., if TF=1, the 8086 gets interrupted automatically at the end of every instruction execution.

Memory Segmentation:



Memory in an 8086/8088 based system is organized as segmented memory. In this scheme, the complete physically available memory may be divided into a number of logical segments. Each segment is 64K bytes in size and is addressed by one of the segment registers. The 16-bit contents of the segment register actually point to the starting location of a particular segment. Each segment has Offset addresses .

The complete 1M bytes of memory can be divided into 16 segments. each of 64Kbytes size. The addresses of the segments may be assigned as 0000H to F000H respectively. The offset address values are from 0000H to FFFFH . So that the physical addresses range from 00000H to FFFFFH.

In the above said case, the segments are called non-overlapping segments. The non-overlapping segments are shown in Fig. 1.3(a). In some cases, however, the segments may be overlapping. Suppose a segment starts at a particular address and its maximum size can be 64Kbytes. But. if another segment starts before this 64Kbytes locations of the first segment, the two segments are said to be overlapping segments. The area of memory from the start of the second segment to the possible end of the first segment is called an overlapped segment area Figure 1.3(b)

The main advantages of the segmented memory scheme are as follows:1. Allows the memory capacity to be 1Mbytes although the actual addresses to be handled are of 16-bit size 2. Allows the placing of code,data and stack portions of the same program in different parts (segments) of memory, for data and code protection 3. Permits a program and/or its data to be put into different areas of memory each time the program is executed, i.e. provision for relocation is done.

PHYSICAL MEMORY ORGANIZATION:



In an 8086 based system, the 1M bytes memory is physically organized as an odd bank and an even bank, each of 512 Kbytes, addressed in parallel by the processor. Byte data with an even address is transferred on D7-D0 , while the byte data with an odd address is transferred on D15-D8 lines. The processor provides two enable signals, BHE and A0 for selection of either even or odd or both the banks. 8086 is a l6-bit microprocessor and hence can access two bytes of data in one memory or I/O read or write Operation. But the commercially available memory chips are only byte size i e they can store only one byte in a memory location. Obviously, to store 16-bit data, two successive memory locations are used and the lower byte of 16-bit data can be stored in the first memory location while the second byte is stored in-the next location. In a sixteen bit read or write operation both of these bytes will be read or written in a Single machine cycle. A map of an 8086 memory system starts at 00000H and ends at FFFFFH. 8086 being a 16-bit processor is expected to access 16-bit data to / from 8-bit commercially available memory chips in parallel, as shown below in Fig

The lower byte of a 16-bit data is stored at the first address of the map 00000H and it is to be transferred over D0 - D7 of the microprocessor bus so 00000H must be in 8-bit memory (2). Higher byte of the 16-bit data is stored in the next address 00001 H; it is to be transferred over D8 - D15 of the microprocessor bus so the address 00001H must be in 8-bit memory (1) of Fig. On similar lines, for the next 16-bit data stored in the memory. immediately after the previous one, the lower byte will be stored at the next address 00002H and it must be in 8-bit memory (2) while the higher byte will be stored at the next address 00003H that must be in 8-bit memory (1 ). Thus, if it is imagined that the complete memory map of 8086 is filled with 16-bit data, all the lower bytes (D0-D7) will be stored in the 8-bit memory bank (2) and all the higher bytes (D8-D15,) will be stored in the 8-bit memory (1 ). Consequently, it can be observed that all the lower bytes have to be stored at even addresses and all the higher bytes have to be stored at odd addresses. Thus, the 8-bit memory bank (1) will be called an odd address bank and the 8-bit memory bank (2) will be called an even address bank.



Certain locations in memory are reserved for specific CPU operations. The locations from FFFF0 H to FFFFF H are reserved for operations including jump to initialization program and I/O-processor initialization. The locations 00000H to 003FFH are reserved for interrupt vector table. The interrupt structure provides space for a total of 256 interrupt vectors. The vectors, i.e. CS and [P for each interrupt routine requires 4 bytes for storing it in the interrupt vector table. Hence, 256 types of interrupt require 256 * 4 = 03FF H (lKbyte) locations for the complete interrupt vector table.

PIN DIAGRAM OF 8086 MICROPROCESSOR:

The Microprocessor 8086 is a 16-bit MICROPROCESSOR available in different clock rates (5, 8, 10 MHz) and packaged in a 40 pin DIP or plastic package. The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode) and other function in maximum mode configuration (multiprocessor mode).The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a single microprocessor configuration. The maximum mode is selected by applying logic 0 to the MN / MX input pin. This is a multi micro processors configuration. The figure below shows the pins/signals of 8086 processor. Here the pins within the brackets (minimum mode pins) are minimum mode pins.

Signal description:

The 8086 signals can be categorized in three groups. The first are the signal having common functions in minimum as well as maximum mode. The second are the signals which have special functions for minimum mode. Third are the signals which have special functions for maximum mode.



The following signal descriptions are common for both modes:

Vcc: It requires +5V single power supply for the operation of the internal circuit.

GND: ground for the internal circuit.AD15-AD0: These are the time multiplexed memory I/O address and data lines. These lines serve two functions. The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 LSB. When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller.

A19/S6, A18/S5, A17/S4, and A16/S3:These are the time multiplexed address and status lines. During T1 these are the most significant address lines for memory operations. During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for T2, T3, Tw and T4. The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. Thestatus is displayed on S5pin. The S4 and S3 combinedly indicate which segment register is presently being used for memory accesses as in below fig. The last status bit S6 is always at the logic 0 level.The address bits are separated from the status bit using latches controlled by the ALE signal.

BHE/S7:The bus high enable is used to indicate the transfer of data over the higher order (D15-D8) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus.

RD(Read): This signal on low indicates the peripheral that the processor is performing s memory or I/O read operation. RDis active low and shows the state for T2, T3, and Tw of any read cycle. The signal remains tristated during the hold acknowledge.READY:This is the acknowledgement from the slow device or memory that they have completed the data transfer. This signal is provided by an external clock generator device and can be supplied



by the memory or I/O subsystem to signal the 8086 when they are ready to permit the data transfer to be completed.NMI-Non maskable interrupt: This is an edge triggered input which causes a type2 interrupt. The NMI is not maskable internally by software. A transition from low to high initiates the interrupt response at the end of the current instruction.

INTR: INTR is an input to the 8086 that can be used by an external device to signal that it needs to be serviced.Logic 1 at INTR represents an active interrupt request. When an interrupt request has been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0 at the INTA output.

TEST : This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state.

CLK: Clock Input: The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle.

RESET: This input causes the processor to terminate the current activity and start execution from FFFF0H.

MN/MX : The logic level at this pin decides whether the processor is to operate in either minimum or maximum mode.

The following pin functions are for the minimum mode operation of 8086:

M/IO: This is a status line logically equivalent to S2 in maximum mode.The logic level of M/ IO tells external circuitry whether a memory or I/O transfer is taking place over the bus. When it is low, it indicates the processor is having an I/O operation, and when it is high, it indicates that the processor is having a memory operation.

WR: The signal write WR indicates that a write bus cycle is in progress. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus.

INTA: (Interrupt Acknowledge)-This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt.

ALE – Address Latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated.

DT/R – Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low.



DEN– Data Enable: This signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal.HOLD and HLDA: The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA signals. When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.

The following pin functions are applicable for maximum mode operation of 8086:S2 S1 S 0– Status Lines: These are the status lines which reflect the type of operation, being carried out by the processor.

LOCK: This output pin indicates that other system bus master will be prevented from gaining the system bus, while the LOCK signal is low.

QS1, QS0 – Queue Status: These lines give information about the status of the code-prefetch queue.Two new signals that are produced by the 8086 in the maximum-mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0. Following table shows the four different queue status.



RQ0/GT0, RQ1/GT1 – Request/Grant: These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle. Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.

Minimum Mode 8086 System: The microprocessor 8086 is operated in minimum mode by applying MN/MX pin to logic

1. In this mode, all the control signals are given out by the microprocessor chip itself. There is

a single microprocessor in the minimum mode system. The remaining components in the system are latches, transceivers, clock generator, memory

and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system.

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system. •Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086..Transreceivers are the bidirectional buffers and sometimes they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals. They are controlled by two signals namely, DEN and DT/R. The DT/R signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. •Usually, EPROM is used for monitor storage, while RAM for user’s program storage. A system may contain I/O devices. •The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations.



•The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle.

Read Cycle: The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also

M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus.

The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation.

At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD) control signal is also activated in T2.

The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus.

The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers.



Write Cycle: A write cycle also begins with the assertion of ALE and the emission of the address. The M/

IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location.

The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).

The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write.

Maximum mode:

When the 8086 is set for the maximum-mode configuration, it provides signals for implementing a multiprocessor / coprocessor system environment. By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program. Usually in this type of system environment, there are some system resources that are common to all processors. They are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resources. Coprocessor also means that there is a second processor in the system. In this two processor does not access the bus at the same time. One passes the control of the system bus to the other and then may suspend its operation. In the maximum-mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor.



Fig: Maximum mode 8086 system configuration•In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. In this mode, the processor derives the status signal S 2, S 1, S 0. Another chip called bus controller derives the control signal using this status information. In the maximum mode, there may be more than one microprocessor in the system configuration. The components in the system are same as in the minimum mode system. •The basic function of the bus controller chip IC8288 is to derive control signals like RD and WR (for memory and I/O devices), DEN , DT/R, ALE etc. using the information by the processor on the status lines. •The bus controller chip has input lines S 2, S 1, S 0 and CLK. These inputs to 8288 are driven by MICROPROCESSOR. •It derives the outputs ALE, DEN , DT/R, MRDC, MWTC, AMWC, IORC, IOWCand AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems. •AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN output depends upon the status of the IOB pin. •If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral data enable used in the multiple bus configurations. •INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device. •IORC, IOWC are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the address port. •The MRDC, MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals. •All these command signals instructs the memory to accept or send data from or to the bus. •For both of these write command signals, the advanced signals namely AIOWC and AMWTCare available. •Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals.•R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1.



•In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4. •The status bit S0 to S2 remains active until T3 and become passive during T3 and T4. •If reader input is not activated before T3, wait state will be inserted between T3 and T4.



Interrupts:

While CPU is executing a program, an interrupt break the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine(ISR).

After executing ISR ,the control is transferred back again to the main program.

Whenever a no.of devices interrupt a CPU at a time and if the processor is able to handle them properly, it is said to have multiple interrupt processing capability. 8086 has two interrupt pins NMI and INTR.

Classification of Interrupts

In general the interrupts can be classified in the following three ways : 1. Hardware and software interrupts

2. Vectored and Non Vectored interrupt:3. Maskable and Non Maskable interrupts.

The interrupts initiated by external hardware by sending an appropriate signal to the interrupt pin of the processor is called hardware interrupt. The 8086 processor has two interrupt pins INTR and NMI. The interrupts initiated by applying appropriate signal to these pins are called hardware interrupts of 8086.

The software interrupts are program instructions. These instructions are inserted at desired locations in a program. While running a program, if software interrupt instruction is encountered then the processor initiates an interrupt. The 8086 processor has 256 types of



software interrupts. The software interrupt instruction is INT n, where n is the type number in the range 0 to 255.

When an interrupt signal is accepted by the processor, if the program control automatically branches to a specific address (called vector address) then the interrupt is called vectored interrupt. The automatic branching to vector address is predefined by the manufacturer of processors. (In these vector addresses the interrupt service subroutines(ISR) are stored). In non-vectored interrupts the interrupting device should supply the address of the ISR to be executed in response to the interrupt. All the 8086 interrupts are vectored interrupts. The vector address for an 8086 interrupt is obtained from a vector table implemented in the first 1kb memory space (00000h to 03FFFh).

The processor has the facility for accepting or rejecting hardware interrupts. Programming the processor to reject an interrupt is referred to as masking or disabling and programming the processor to accept an interrupt is referred to as unmasking or enabling. In 8086 the interrupt flag (IF) can be set to one to unmask or enable all hardware interrupts and IF is cleared to zero to mask or disable a hardware interrupts except NMI.

The interrupts whose request can be either accepted or rejected by the processor are called maskable interrupts. The interrupts whose request has to be definitely accepted (or cannot be rejected) by the processor are called non-maskable interrupts. Whenever a request is made by non-maskable interrupt, the processor has to definitely accept that request and service that interrupt by suspending its current program and executing an ISR. In 8086 processor all the hardware interrupts initiated through INTR pin are maskable by clearing interrupt flag (IF). The interrupt initiated through NMI pin and all software interrupts are non-maskable.

Interrupt cycle of 8086:When an external device interrupts the CPU at NMI or INTR pin, while executing a program the CPU first completes the execution of current instruction and IP is incremented to point the next instruction. The contents of IP and CS are pushed to stack. The CPU then only acknowledges the requesting device immediately on INTA if it is a NMI,TRAP or divide by 0. If it is INTR request, the CPU checks the IF flag. If IF flag is set then it acknowledges the device otherwise the interrupt is ignored. After acknowledgement the CPU computes the vector address from the type of interrupt. Then the control is transferred to ISR for serving the interrupt device. The ISR address is available in Interrupt Vector Table. At the end of ISR last instruction should be IRET.



The 8086 supports a total of 256 types of the interrupts, i.e. from 00 to FFH. Each interrupt requires 4 bytes, i.e. two bytes each for IP and CS of its ISR. Thus a total of 1.024 bytes are required for 256 interrupt types. Hence the interrupt vector table starts at location 0000:0000 and ends at 0000:03FFH. The interrupt vector table contains the IP and CS of all the interrupt types stored sequentially from address 0000:0000 to 0000:03FF H. The interrupt type N is multiplied by 4 and the hexadecimal multiplication obtained gives the offset address in the zeroeth code segment at which the IP and CS addresses of the interrupt service routine (ISR) are stored. The execution automatically starts from the new CS:IP.


iii b.tech. iisem (r15) ece : microprocessors and ... · web view2018/02/01 · a simple block...

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