iep07basicblocks

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BASIC BLOCKS :

PASSIVE COMPONENTS

1



PASSIVE COMPONENTS:

Capacitors Junction Capacitors

Inversion Capacitors Parallel Plate Capacitors

Resistors Poly Resistors

Diffused Resistors Switched capacitors as resistors Active Load

2



CAPACITORS

The desired characteristics for capacitorsused are given below:· Good matching accuracy· Low voltage-coefficient· High ratio of desired capacitance to

Parasitic capacitance

· High capacitance per unit area

3



This structure uses the Gate to Source and gate to

Drain Capacitances to realise the required

Capacitances. This capacitance achieves a large

capacitance per unit area and good matching but

suffers from high voltage dependent parasitic

capacitance to ground.

Poly- SiO2 ² Channel Capacitance

4



Poly ² SiO2 ² Poly Capacitor

This is one of the best configurations forhigh performance capacitors.

5



MOS Accumulation Capacitor

This has a high capacitance per unit areaand used where grounded capacitors re required.

6



Capacitors realized using various inter connect layers

This gives the method to obtain capacitors by

appropriate choice of plates and connection betweenvarious metal and Poly Si layers available. It shouldbe mentioned that each interconnect layer isinsulated from the others by a SiO2 layer. Of thevarious structure shown, the four layer structure

has the least parasitic capacitance. 7



As processes migrate toward finer line widths and higherspeed performance, the oxide between metals increases whilethe allowed space between metals decreases. For such

processes, samelayer, horizontal, capacitors can be moreefficient than different-layer vertical capacitors. This is dueto the fact that the allowed space between two M1 lines, forexample, is less than the vertical space between M1 and M2.

8



The capacitor plate with the smallest parasitic

associated with it is referred to as the top plate.It is not necessarily physically the top platealthough quite often it is. In contrast, the bottomplate is that plate having the larger parasiticcapacitance associated with it. Schematically, the

top plate is represented by the flat plate in thecapacitor symbol while the curved platerepresents the bottom plate.

9



10



While designing for matched capcitors or ratioedcapacitors, a technique of common centroid lay out is

used. The concept is best illustrated with an example.

11



VICINITY EFFECTS

12



13



RESISTORS

The diffused resistor is normally formed with

source/drain diffusion. The sheet resistance of suchresistors are normally in the range of 50 to 100;/ for non salicide process and about 5-15;/ forsallicide processes. These resistance have a voltagedependence in the range of 100-500 ppm/V range and

also a high parasitic capacitance to ground. 14



The poly Si resistor has a sheet resistance in therange of 30-200 ;/ depending on the doping of

the poly Si layer. For a polysilicide process theresistance is about 10;/ .

15



The n-well resistance has a resistance of 1-10K;/

along with a high voltage sensitivity. In cases where accuracy is of no concern this structure is veryuseful.

16



17



ACTIVE (ac) RESISTORS

18



19



SWITCHED CAPACITOR RESISTOR

20



AMPLIFIERS

21



DSn2

THGSDS V1VVLW

2kI Pd!

BS

DSmb

DS

DSds

GS

DSmsbmbdsdsgsmds V

Igand,

V

Ig,

V

Igwherevgvgvgi

x

x!

x

x!

x

x!!

dsDSnn

2

THGSDS

DSds

DSTHGSGS

DSm

r

1IVVL

W

2

'k

V

I

gand

ILW

'k2VVLW

'kV

Ig

!P!P!x

x

!

!!x

x!

BSF

mmbs

V22

gg

J

K!

SMALL SIGNAL PARAMETERS

22



23



COMMON SOURCE AMPLIFIERS

24



25



gm = gm1 and RL = R ||l rds1 for Resistance load amplifier

gm = gm1 and RL = rds1 ||l rds2 ||l 1/gm2 for Active load

amplifiergm = gm1 and RL = rds1 ||l rds2 for Current source load amplifier and

gm = gm1 + gm2 and RL = rds1 ||l rds2 for Push PullAmplifier.

26



Ain = gm1 (R ||l rds1) for Resistance load amplifierAin = gm1 (rds1 ||l rds2 ||l 1/gm2) = for Active load

amplifier.A

in= g

m1(r

ds1||l r

ds2) = for Current source load

amplifierAin = (gm1 + gm2) (rds1 ||l rds2) = for Push Pull amplifier.

27



The capacitor at the input CIN = CGS1 for Active Loadand Current Source Load Amplifier and CIN = CGS1 +CGS2 for the Push Pull amplifier. The bridging capacitorC = CGD1 for Active Load and Current Source Load

Amplifier and C = CGD1 + CGD2 for the Push Pullamplifier. The capacitor at the output CL = CLoad + CGS2

+ CBD1 + CBD2 for the Active Load amplifier and is CL =CLoad + CBD1 + CBD2 for the Current Source Load and

Push Pull Amplifiers. 28



1

1Lm

in

outin s

z/s1Rg

v

vA

[

[!!

MS

2m

LL1

21

21Lm

s

out

CR

1and

C

gz

CR

1where

ss

z/s1Rg

v

vA ![!![

[[[[!!

CM is the Miller Capacitance seen at the input.

29



COMMON DRAIN AMPLIFIER

30



31



loadsourcecurrentforgggg

1r

2ds1ds1mbs1mout

!

loadactiveforggggg

1

2ds2m1ds1mbs1m !

ionconfiguratpullpushforgggggg

1

2ds2mbs2m1ds1mbs1m !

loadsourcecurrentforgggg

g

v

vA

2ds1ds1mbs1m

1m

in

out

!!

loadactiveforggggg

g

2ds2m1ds1mbs1m

1m

!

ionconfiguratpullpushforgggggg

g

2ds2mbs2m1ds1mbs1m

1m

!

32



COMMON GATE AMPLIFIER

33



LSS1ds1mb1m1ds

L1ds1mb1m

s

out

1ds1mmb1mL1ds

L1ds1m

L1ds

L1ds1mb1m

in

outin

RRRrggr

R1rgg

v

vA

1rg&ggforRr

Rrg

Rr

Rrgg1

v

vA

!!

""""

}

!!

¹¹ º

¸©©ª

¨

!

1ds

L

1mbs1mSin r

R1

gg1

Rr

34



CASCODE AMPLIFIER

C1 = Cgd1, C2 = Cdb1 + Csb2 + Cgs1, C3 = Cgd2

+ Cdb3 + Cdb2 + Cgd3 and L2 = gmbs2/gm2. 35



1gd3ds

2ds

2m1m1gd

2ds2L2m1m1gd2in1m1gdin

1

1gdM

C3g

g1

g1

g1C

gR

1g

1

g1Crg1Cv

v

1CC

e¹¹

º

¸©©ª

¨¹¹

º

¸©©ª

¨!

¹¹

º

¸

©©ª

¨!!

¹¹

º

¸

©©ª

¨!

Since in the presence of a signal source with a sourceimpedance RS, the pole contributed by the MillerCapacitance seen by the Cascode amplifier will befarther than the Common Source Amplifier with nearly

the same gain and input and output impedances.

36



In cascode amplifier we have used a simple currentsource load. However, to obtain a larger gain we can use a cascade of current mirror load. It should be mentioned here that a single current source isrepresented as a single transistor with a bias while we have represented a cascade current source withtwo transistors in series with appropriate gate bias.

37



38



¹¹ º ¸

©©ª¨ !

2ds

2 3ds3m

2m2in r

rg1g1r

ds

1m

1

1ds2in

1min

11 g2

gg

r

1g

v

vA }¹¹

º

¸©©ª

¨!!

gm2 § gm3, gds2 = gds3 = gds1 = gds5

2m

1ds2ds

3m

4ds3dsL g

gg

g

ggG !

L

ds

L'2in1

out2 G

gG1

r1

vvA }!!

L

1m21

1

out

in

1

in

out

G1

2

gAA

v

v

v

v

v

vA !!!!

TELESCOPIC CASCODE AMPLIFIER

39



¹

¹

º

¸

©

©

ª

¨!

2ds

23ds3m

2m2in

r

rg1

g

1r ||l 1/g

ds5

ds

1m

1

1ds2in

1min

11 g2

gg

r

1g

v

vA }¹¹

º

¸©©ª

¨!!

2m

5ds1ds2ds

3m

4ds3dsL g

ggg

g

ggG

!

L

ds

Lin

out

G

g

Gr v

v

A }}!

11

'

21

2

L

1m21

1

out

in

1

in

out

G1

2

gAA

v

v

v

v

v

vA !!!!

FOLDED CASCODE AMPLIFIER

40

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