IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015 399

A New Accelerated Endurance Test for TerabitNAND Flash Memory Using Interference EffectJaewon Cha, Wooheon Kang, Junsub Chung, Kunwoo Park, and Sungho Kang, Senior Member, IEEE

Abstract—Limited endurance of E/W cycles is a unique restric-tion of flash memories and the endurance characteristics usuallytake a longer time to test. In this paper, we proposed a novelendurance test scheme that takes advantage of the parasiticcell-to-cell interference as well as a shortened program time toaccelerate the endurance test for terabit NAND flash memory.The novelty of the new scheme is the use of a new test sequenceknown as even/odd row address sequence (EORAS). The inter-ference effect during the program operation mainly affects thethreshold voltage widening in the victim cell and leads to errorslinearly during the read operation. We mainly focus on the corre-lation between the interference and device error rate during theendurance test. Based on the correlation, we use the interferenceeffect as an acceleration factor in EORAS. EORAS is composedof a new program operation for unit test-time reduction. Ourexperimental results show that the proposed scheme method caninduce the raw bit error rate by 50% and thereby improve thecycling time by 19.4% in a 3×-nm flash device. The proposedscheme method can also induce the raw bit error rate by 80% andthereby improve the endurance test time by 30.8% in a 2×-nmflash device. Consequently, the new endurance scheme reducesthe test time by 68.4%.

Index Terms—Test time reduction, reliability testing,erase/write (E/W) cycling, multilevel cell, NAND flash memory,acceleration test.

I. INTRODUCTION

THE MEMORY market has grown at a compound annualgrowth rate (CAGR) of nearly 50% in the past decade

because its high capacity and low bit cost are suitable forvarious applications such as removable portable storage andsolid-state drives (SSDs) [1]. This success is due to theimprovement of aggressive process scaling, the introductionof multi-level cell (MLC) schemes by mature lithography

Manuscript received November 28, 2014; revised February 1, 2015 andMarch 9, 2015; accepted April 26, 2015. Date of publication May 4, 2015;date of current version July 31, 2015. This work was supported by theNational Research Foundation of Korea (NRF) grant funded by the Koreagovernment (MSIP) (No. 2015R1A2A1A13001751).

J. Cha is with the Department of Electrical and Electronics Engineering,Yonsei University, Seoul 120-749, Korea, and also with the NAND-flashResearch and Development Division, SKhynix, Inc., Icheon 467-701,Korea (e-mail: jaewon.cha@sk.com).

W. Kang and S. Kang (corresponding author) are with the Departmentof Electrical and Electronics Engineering, Yonsei University, Seoul 120-749,Korea (e-mail: sudal@soc.yonsei.ac.kr; shkang@yonsei.ac.kr).

J. Chung and K. Park are with the NAND-flash Research and DevelopmentDivision, SKhynix, Inc., Icheon 467-701, Korea (e-mail: chungjs@sk.com;kunwoo.park@sk.com).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TSM.2015.2429211

techniques and advanced design skills such as error correctioncodes [2]. Reliability issues, such as endurance and data reten-tion, have a large impact on NAND flash devices, and they arebecoming increasingly complex and difficult due to the rapiddecrease in size of technology. Furthermore, the current issueswith MLC flash memory are worsening due to the inclusionof several data elements within a cell. Generally, each cell hasa threshold-voltage (VTH) window of four or eight; thus, VTHwindows are required in order to separate different VTH levels.

Endurance is defined as the maximum number of data writesfor each memory cell. Among reliability issues, the lim-ited endurance of flash memory has recently become themain difficulty preventing the wide use of SSDs [3]. This ismainly due to the fact that erase/write (E/W) cycling causesa uniform decrease in device performance [4], [5] due to thedeterioration of an oxide layer at the physical level of theflash memory cell. The cell-to-cell interference caused byfloating-gate coupling has a serious impact on endurance dueto parasitic capacitances among the cells [6]–[8]. The inter-ference phenomena have been the most significant issuesin 40-nm technology. To solve these issues and reduce theerror rate, many interference cancellation schemes have beenproposed [9]–[12].

The 2011 International Technology Roadmap forSemiconductors (ITRS) reports that the maximum num-ber of bits, including single-level cell (SLC), 2-bit/cell,3-bit/cell, and 4-bit/cell NAND flash devices, will be 128 Gbin 2013 and 1 Tb in 2019 [13]. 3D charge-trapping flashdevices can also allow the cell capacity increase to continuefor at least another decade beyond the 1y-nm process [14].Therefore, with this trend toward higher capacity, the totaltest time is a significant consideration for the test cost ofa device. Moreover, the test time per bit needs to be seriouslyconsidered because higher-level cell technology, such astriple-level cell (TLC) and quadruple-level cell (QLC), sig-nificantly degrades the write/read throughput due to precisecell control. To minimize the burden of the test time forNAND flash memory, fast data-load [15], a test schemethat reduces the data-load period during the endurance test,is used. Using this scheme, we can simultaneously loaddata into all page-buffers (PBs). However, this scheme onlyprovides a few regular patterns due to a silicon area burdencaused by an increase in the number of control signal linesin the PB. Design for test (DFT) using an internal paralleltest scheme, such as a two-plane parallel operation [16], isanother speedup testing approach. This technique reduces thetest time by using the structural changes of flash devices.

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400 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

However, it is expensive and difficult to keep up with thegrowth in the flash memory density. Endurance testing withE/W cycling is a common testing procedure for lifetimeerrors and is described in detail in the Joint Electron DeviceEngineering Council publication, JESD22 [15]. This testingis normally used in device qualification due to its large timeconsumption and cumulative damage. This testing is alsowidely used in screening errors in order to optimize theprocess steps or the device working conditions during theproduction test.

In this paper, we propose a new accelerated endurance test inorder to reduce the time consumed. We focused on the followingtwo factors. First, we increase the interference effect betweencells, which increases the error rate of the device during the test.There is a method for increasing the interference: changing thesequence of addresses. Second, we reduce the write operationtime. The endurance test is made up of repeated write and eraseoperations. During the test, the write time consumes a largepart of the cycling time due to the device structure. The eraseprocess operates by a block, whereas the write process operatesby a page. The NAND flash memory is logically composed ofsmall subunits of pages and blocks. The page is the smallestunit for the program and read operations, whereas the block isthe smallest unit for the erase operation. Each block in a 3x-nmand a 2x-nm MLC devices logically consists of 256 pages.Therefore, we propose unit test-time reduction methods, namely,a least significant bit (LSB) and most significant bit (MSB)integrated memory program.

The rest of the paper is organized as follows. Section IIintroduces the organization and the previous endurance issuesof NAND flash memory. Section III explains the pro-posed endurance test for test cost. The performance of thenew scheme, based on experimental results, is describedand discussed in Section IV. Finally, Section V concludesthe paper.

II. BACKGROUND

A. Basic Cell Array of the NAND-Flash Device

While stored in the flash memory, the data that is con-trolled by the column decoder will sequentially arrive at thePB and then be written into the selected word lines (WLs).Then, the selected WL controlled by the row decoder receiveshigh voltage (more than 18 V) generated by high voltagegenerators (HVGs). The PB, which temporarily stores thedata for the page program and the page read operations, isphysically connected to the bit-line (BL). In addition, thisblock has as many internal buffers as BLs. For example,there are 65536(8 × 1024 × 8) internal buffers for an 8 KBpage in 3×-nm and 2×-nm technology. One PB normallyincludes more than three latches for device operations suchas cache operations and data sensing in MLC devices [17].The WL driver that is connected to the WLs is composed ofan N-channel metal oxide semiconductor using high-voltage inorder to deliver the program or the pass bias to WLs locatednear the memory matrix. Moreover, this block has aggressivelayout rules that result from the progression of the technol-ogy size reduction. A high-voltage generator composed of

Fig. 1. Illustration of parasitic capacitances between victim and adjacentcells in a NAND flash array.

several circuits, such as charge pumps, regulators and high-voltage switches, needs to provide precise voltage control,fast timing and low power consumption. These high voltage-related blocks must endure high-voltage stress for the lifetimeof the device. The user-operated controller circuit managesthe peri-circuits that are involved in the memory operation.This controller circuit contains several sub circuits, such asthe command interface for understanding user commands, anembedded microcontroller for execution of embedded algo-rithms, and the read-only memory (ROM) for firmware. Thelayout of the controller circuit is semi-customized, and auto-matic placement and routing techniques can be effectively usedin this subunit.

B. Basic Theory of the Interference Effect

According to [6], the VTH widening of the victim cell dueto cell-to-cell interference can be modeled as

�VTH−VICTIM =∑

adj(�VTH(adj)�γFG) (1)

where �VTH(adj) represents the internal VTH shift of theadjacent cells due to the program operation. The floatinggate-coupling ratio, γFG, is defined as

γFG = CFG

Ctotal(2)

where Ctotal is the total capacitance of the victim cell and CFG

is the parasitic capacitance between the adjacent cells and thevictim cell, as shown in Fig. 1. It is sufficient to consideronly the adjacent cells around the victim cell because CFG

decreases exponentially as the spacing between cells increases.A critical factor to consider is that adjacent cells can inter-fere with the victim cell whose VTH is not located in theerase state. When the victim cell is located in the erase state,the interference factor to move the VTH state is very smallduring the program operation. If the program operation is per-formed sequentially (WL[n], WL[n+1], WL[n+2], . . .), CFG

is described as follows:

CFG = 2CX + CY + 2CXY (3)

because the cells in WL(n) are almost not disturbed during theprogram operation of the cells in WL(n + 2). In conclusion,it is sufficient to consider only six of the nine cells in thesequential program operation.

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From Formulas 1, 2 and 3, we can calculate the influence ofinterference among cells with the test pattern of the cycling.Therefore, we can predict the results of the cycling test. Inpractice, we are able to determine a poor test pattern that willinduce a higher bit error rate and a better test pattern that willinduce a lower bit error rate during cycling.

A recent study [12] has clearly identified data randomiza-tion as an endurance enhancement technique due to interfer-ence mitigation during E/W cycling. The interference amongcells is associated with the lack of a VTH margin, which iscaused by floating gate coupling among cells. The measure-ment results show that the cell-to-cell interference is the mostdominant parasitic effect of the VTH distribution wideningsince the 60 nm process node, and the interference generatesa serious problem relating to the error rate of the device in anMLC operation [18].

C. Previous Endurance Tests

Endurance is the ability of flash memory with a float-ing gate to operate within specifications after repeated E/Wcycling [19]. The average raw bit error rate (RBER) afterapplying E/W cycling has been rapidly increasing due todecreasing physical cell sizes and increasing storage of mul-tiple bits of flash memory cells such as MLC, TLC, andQLC [20]. To minimize endurance errors, numerous designapproaches are being developed. The typical approach relatesto the disturbance error associated with the isolation diffi-culties of high voltages that are mostly caused by adjacentneighbor cells in a NAND string during device operations,such as reading and programming. Therefore, the local self-boosting scheme [21] has been proposed to improve thechannel boost ratio after the 0.7-um process in the programoperation. This scheme is regarded as a solution to the dis-turbance. Other modified schemes are required in the MLC inorder to repeat write operations on a page because the localself-boosting scheme is only optimized in an SLC device.

To evaluate the endurance behavior of flash memory withina reasonably short test time, two methods are presented. Oneis built-in, fast semiconductor switching in the automatic testequipment (ATE), which is used to efficiently apply a highvoltage to the cell [22]. This method provides substantialthroughput improvements for the endurance test. However,using this method, it is difficult to determine the entire trend inwafer processing because the method is only available for test-ing a single cell using a direct-memory-access mode. Anothermethod is high voltage acceleration, which involves the appli-cation of voltages higher than the operating voltage duringE/W cycling. This also provides an endurance model to ver-ify the validity of the endurance performance. However, it isuncertain whether this model is even valid for the 20-nm pro-cess because its validity has only been demonstrated for the0.5-um process [23]. The other method is a single commandoperation in which the behavior of each individual deviceoperation such as the program, the erase and the read, is inte-grated into a command. Therefore, this method reduces theidle time that occurs between the individual operations. Theidle time is not negligible during the cycling test in the con-troller testing [24]. However, this method has a limit in order

Fig. 2. Components of the new accelerated endurance test.

to reduce the test time due to the relevance to the raw NANDdevice being lower.

The E/W endurance test is performed across a range ofNAND flash devices, and the experimental results show thatthe built-in random generator minimizes the RBER [12]. Fora data-load period in the program operation, the IO_bus fromthe input/output buffer runs an exclusive or (XOR) operationwith the random value. The pseudo-random generator consistsof an 8-bit linear feedback shift. As a result of the XOR,the scramble_data are stored temporarily in the PB duringthe toggling of write-enable low data, and then all of thescramble data are simultaneously written to the flash mem-ory cells. In contrast, toggling of read-enable low data createsa data-output period. This scheme generates randomized pat-tern data arranged in a pseudo-random pattern and avoids thepoor pattern data that increase interferences from adjacent bitsto the victim bits in order to forward device-level reliability.However, at the moment, this scheme needs to consider issuessuch as the test-time and chip-size burden.

III. NEW ACCELERATED ENDURANCE TEST

The component of the new accelerated endurance testscheme is shown in Fig. 2. The endurance test is made upof repeated erase and program operations. In order to real-ize the new accelerated tests for the endurance, we increasethe interference between cells using a method such as newaddress ordering. Even/odd row address sequence (EORAS)is the new E/W cycling operation in a cell. This operationincludes the new integrated program method to reduce unittest time. Consequently, the device can reach its target RBERquickly during the proposed endurance test.

A. New LSB and MSB Integrated Program

The endurance test is very time-consuming because a largenumber of erase and program operations are repeated in orderto measure the device availability. Since the program operationis slower than the erase operation, it must be analyzed firstfor test time reduction. About 95% of the E/W cycling time is

402 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

Fig. 3. Integrated LSB and MSB program. (a) Test time comparison of the conventional and newly proposed methods. (b) 2-bit MLC VTH distribution.(c) Simplified circuit diagram of one PB. (d) Internal algorithm of the integrated program.

used for the program operation in the conventional test. Thus,we mainly focus on the behavior of program operations for anaccelerated test.

Fig. 3 shows the integrated LSB and MSB program. Thisnew program is a way to shorten the time required to oper-ate the two-page program in a single operation, as shown

CHA et al.: NEW ACCELERATED ENDURANCE TEST FOR TERABIT NAND FLASH MEMORY 403

in Fig. 3(a). The two-plane operation is a method for simul-taneously operating the different pages of the adjacent twoplanes, whereas the proposed method is an operating methodfor running two logical pages simultaneously in the WL(n).The two logical pages are called the LSB page and the MSBpage. The proposed method can significantly reduce the testtime because it can be used concurrently with the two-planeoperation. Fig. 3(b) shows the VTH distribution of the 2-bitMLC device. Each programmed state has its own verificationreference (verify_1, verify_2, verify_3) VTH located on thelower edge of the various states. If all of the cells exceedtheir verification reference VTH, the program operation willbe stopped. In addition, the verification operation refers tothe process of verifying whether the VTH of the cells sur-passes the verification VTH during program operation. NANDflash memory can be moved from the erase state to the firstprogrammed state, the second programmed state and the thirdprogrammed state simultaneously. Each memory can be movedto the one of the three programmed states selectively during theNew LSB & MSB integrated program. However, the programoperation of the NAND flash device is performed in a pageunit. Therefore, all cases can occur as shown in Fig. 3(b).Fig. 3(c) shows a simplified circuit diagram of one PB con-nected to two BLs. The PB is composed of several sub-latchblocks. Latch_A is the cache latch that receives the data tobe programmed during the program operation. Latch_B is themain latch used to put the data into the memory cells duringthe program operation. Latch_B is also used for data sensingthat determines the state of the target cell during the programverification operation. In addition, during the read operation,the value of the target cell is stored in latch_B. Latch_C isthe temporary latch that stores the data from the LSB pagebefore programming of the MSB page occurs. The multiplexerblock is used for selecting one of the two BLs during deviceoperations. Fig. 3(d) shows the flow chart of the integratedprogram algorithm. A key point of this algorithm is that it per-forms the program verification operations three times in orderto simultaneously write two pages in a cell, whereas the con-ventional method performs the program verification operationsonly once or twice. The first step is the reset operation that ini-tializes all variables located in a peripheral circuit. The secondstep is the phase that operates the two data-load processes tobe programmed. It is possible to use the fast data-load schemein order to save time. Then, latch_A stores the results from theNOR operation between latch_B and latch_C in order to dis-tinguish between the “00” state and the “10” state. The thirdstep determines whether the target cell will be written usinga charge sharing technique between the BL and latches. If theBL bias is ground, then the cell will be programmed; other-wise, the cell will be inhibited during program operation. Thenext step is the first verification operation which is a data sens-ing operation in order to investigate whether the VTH of thecell exceeds the verify_1 level, as shown in Fig. 3(b). If the cellcompletes the program, the value of latch_C will be inverted.If the cell has not yet completed the operation, then latch_Cwill maintain its initial value. The second verification is alsoa data sensing operation in order to investigate whether theVTH of the cell exceeds the verify_2 level. The value of

latch_B is inverted using the charge sharing in accordancewith the VTH of the target cell. However, the read operationis performed successfully only if the value of latch_A gen-erated by the second step is one (third VTH distribution, thedata “00”). Otherwise, the latch value maintains its previousvalue. The third verification is also a data sensing operation inorder to investigate whether the VTH of the cell exceeds theverify_3 level. This operation is performed successfully onlywhen the value of latch_A is zero (last VTH distribution, thedata “10”). Otherwise, all latch values maintain their previ-ous values. After the final verification operation, the devicewill ensure that all cells have reached their target VTH state.The operation will be completed if the values of latch_B andlatch_C are all ones. Otherwise, the third step is repeated.

B. New Even/Odd Row Address Sequence

Fig. 4 shows the new endurance test sequence namedEORAS. This is an address-ordering, repeating the sameoperation twice. While the conventional test sequence usespage-address ordering with temporary LSB storage, the pro-posed sequence uses WL-address ordering with the integratedLSB and MSB program method in order to reduce theendurance test time. The new endurance test sequence usingthe integrated LSB and MSB program method is shown inFig. 4(a). After the erase operation, the integrated program isperformed in a cell located in the odd WL. Then, through theblock erase, the data stored in the odd WL are deleted. Finally,the operations previously described are repeated only on evenWL cells. Fig. 4(b) shows the EORAS and its interferenceeffect of NAND flash. The proposed sequence produces anapproximately two-fold change in VTH(�2VTH) and resultsin a larger distribution of the victim cells compared to usingthe conventional address sequence. This is because the MSBstate is directly changed from the erase state without usingthe temporary LSB state. Accordingly, the vertically adjacentWL whose VTH is in the erase state offsets the two-fold inter-ference effect in the horizontal direction. Equations for thecell-to-cell interference are given in Table I, where Ctotal isthe total capacitance of the victim cell, and �VTHX is theVTH change in the cells horizontally adjacent to the victimcells. Additionally, �VTHY is the VTH change in the cellsvertically adjacent to the victim cell, and �VTHXY is theVTH change in the cells diagonally adjacent to the victimcell. Consequently, the equations shown in Table I can besimplified as 2CX + CY + 2CXY and 4CX , respectively. Thesimulated parasitic capacitance values of CX, CY and CXY in22-nm NAND flash memory are set to 0.75, 0.92 and 0.17,respectively [25]. According to calculations, the interferenceof the proposed test is approximately 10% greater than that ofthe conventional test.

The proposed test sequence can be applied beyond 22 nmtechnology until the following formula is satisfied

2CX + CY + 2CXY < 4CX

CY + 2CXY < 2CX

CY < 2CX (4)

404 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

Fig. 4. New endurance test sequence. (a) New endurance test ordering using the integrated program operation. (b) Even/odd row address pass and itsinterference effect on NAND flash.

TABLE IAPPROXIMATED EQUATION OF CELL-TO-CELL INTERFERENCE

where it is assumed that the diagonal capacitance can benegligible.

IV. EXPERIMENTAL RESULTS

In order to verify this analysis, experiments were carriedout on both 3×-nm 4-level and 2×-nm 4-level NAND flashchips [26]. Fig. 5 shows the measurement of the integratedprogram operation using the ATE and the oscilloscope. Theintegrated program operation takes approximately 2 ms pertwo logical pages (LSB + MSB), and the number of programpulses (Np) is 15. We confirmed that it takes approximately40% less operating time as compared to the time using theconventional method. The initial threshold voltage distribution(�VTH0) is determined as follows [27].

�VTH0 = [Np − 1

] ∗ �VISPP = 4.2V (5)

where �VTH0 is an important factor in determining the pro-gram time. The VTH values of the cells are distributed between

Fig. 5. Measurement of an integrated program operation.

the fastest cell and the slowest cell by the first program pulse.With a downscaled cell size, �VTH0 is expected to becomelarger due to reductions in the number of electrons. VISPP isthe bias for the incremental step pulse programming. �VISPP

is generally set to 0.3 V in MLC devices.Fig. 6 compares the RBER between the conventional test

and the proposed test in 3x-nm devices. The RBER of theproposed test is approximately 50% higher on average com-pared to that of the conventional test. These results show that,in the proposed test, it is possible to induce the interference,effectively replacing the conventional cycling test and reduc-ing the test time for any given number of E/W cycles becausethe RBER is higher. As a result, the E/W cycles using pro-posed scheme reduce 19.4% on the average compared to theconventional test.

Fig. 7 shows the RBER comparison of the conventional testand the proposed test in 2×-nm devices. The RBER of the

CHA et al.: NEW ACCELERATED ENDURANCE TEST FOR TERABIT NAND FLASH MEMORY 405

Fig. 6. Experimental results from a comparison of RBERs in a 3×-nmdevice.

Fig. 7. Experimental results from a comparison of RBERs in a 2×-nmdevice.

proposed test is approximately 80% higher on average com-pared to that of the conventional test. As a result, the E/Wcycles using proposed scheme reduce 30.8% on the averagecompared to the conventional test.

Fig. 8 shows the RBER of the proposed test accordingto the technology shrink when 2K cycling is applied. TheRBER of the proposed test is improved when the technologyshrink scales down. It is estimated that the RBER of 1x-nmdevice is 1.23E-02 and the RBER of beyond of 1x-nm deviceis 2.00E-01, respectively. These results show that our pro-posed test is quite effective during the shrinking of technology.The experimental results show that as the tech shrink pro-gresses, E/W cycle reduction continues to increase. Therefore,the test time of the proposed scheme will be reduced exponen-tially with the tech-shrink. We expect more remarkable resultsbeyond a 22-nm device because the horizontal parasitic capac-itance has more influence on a device of this size comparedwith the proposed test. Consequently, the difference in theRBER between the two tests will increase.

Table II summarizes the comparison results of E/W cyclingwith the conventional endurance tests for NAND flashes.

Fig. 8. Experimental results of RBERs according to the technology shrink(2K cycling).

In order to compute the total E/W test time (Ttotal−cycle) of1 Tb of memory, the following equation is used:

Ttotal−cycle = Ncycle ∗ Nb ∗ Tb ∗ (1 − IAR)

= Ncycle ∗ Nb ∗ (256TP + αTE) ∗ (1 − IAR)

= Ncycle ∗ Nb ∗ (256Tload + 256Tw + αTE)

× (1 − IAR) (6)

where Nb is the number of blocks in the device and isexpressed as Nb = 1 − Tb/(1 − page size ∗ 256). Ncycle is thenumber of cycles, Tb is the E/W cycling time for a 1-block,TP is the program time for 1-page, TE is the block-erase time,Tload is the data-load time for 1-page, Tw is the memory writ-ing time for one page using the test pattern, and α is thenumber of erase times in each scheme, respectively. IAR isthe interference acceleration ratio; in other words, it is thereduction ratio in the number of cycles to reach the RBERusing the proposed scheme. The 1-Tb flash memory has twoplanes, each with 32,768 blocks and 256 pages. TE value ofthe all tests is set to 2.5ms. In the proposed scheme, α is set to2 since it is twice of the conventional test scheme as shown inFig. 4(a). IAR of the proposed scheme is 19.4% in the 3×-nmNand-flash memory as shown in Fig. 6. However, IAR of theprevious works are 0 since these use the conventional programmethod and the conventional address sequence.

In Table II, the endurance test scheme using the pseudo-random generator is the slowest test among them. Theendurance test using the fast data-load scheme reduces thedata-load time considerably because it performs a 1-pagedata-load simultaneously, whereas other schemes use onlysequential operations. Therefore, this scheme can achievea 10.5% test time reduction compared to the previous test.The two-plane parallel scheme can achieve a 44.5% test timereduction compared to the previous test. Compared with theprevious tests, the number of blocks to be tested is reduced byhalf because the two-plane parallel scheme works two pagesat the same time. However, two-plane architecture for par-allel testing must include the area penalty due to additionalperi-circuits in order to operate flash memories such as anHVG, column-decoder, and a WL decoder. The area penalty

406 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 28, NO. 3, AUGUST 2015

TABLE IICOMPARISON RESULTS OF THE E/W CYCLING TIME USING VARIOUS TESTS IN THE 3×-NM NAND-FLASH

TABLE IIISUMMARY OF THE PERFORMANCE COMPARISON ON THE VARIOUS ENDURANCE TESTS

of the proposed endurance test is relatively small because itis possible to reuse existing circuits. The ROM for execut-ing only the test algorithm becomes larger and the integratedLSB and MSB program method uses just two extra latches ina PB that have already been used for user operations such asthe interleaving operation. The proposed test has been appliedto an acceleration test using the interference. Therefore, theproposed scheme has a dramatically reduced test time. Theproposed test can achieve a 68.4% test time reduction com-pared to a conventional test scheme using a pseudo-randomgenerator. The total E/W test time of the proposed work canbe dramatically reduced because of two reasons. The first rea-son is the erase speed which is much faster than the programspeed during the unit block operation. The erase operation isperformed in the block whereas the program operation is per-formed in the page, since the block is composed of the severalhundred pages. The second reason is that the program time ofthe proposed scheme is affected by the integrated LSB andMSB program methods.

Table III shows a summary of the performance compari-son of the various endurance tests. There are four comparisonitems such as endurance test-time, high-capacity memory-test, device area-overhead and test-cost. The proposed schemeand the high voltage acceleration are very suitable for theendurance test time because their test time can be reducedexponentially. However, other approaches are less suitablesince the test time is the most important factor. Most of thetest schemes such as the parallel test are easy for performinghigh capacity memory testing. The built in fast data switchingscheme which is less suitable for the high capacity mem-ory, uses the switching relay in the ATE in order to testthe small number of the unit memories. Therefore, test timeis long and test cost is high. The device area overhead ofmost schemes is small except the fast data-load and the high

voltage acceleration scheme. In particular, the high voltageacceleration scheme is relatively poor since this scheme needsan additional high voltage generation circuit. The priority ofmemory device development is the cheaper development costand the larger capacity. Therefore, the scheme which requiresadditional area such as the high voltage acceleration is lesseffective. Test cost is usually determined according to thedevice area-overhead and test time. In this respect, the singlecommand operation scheme and the built in fast data switch-ing scheme are the worst. The pseudo random generator andthe fast data load schemes have their disadvantages. Overall,the proposed scheme is the best in terms of test cost and itcan be used as a practical solution.

V. CONCLUSION

This paper proposes a new accelerated endurance testscheme for a high capacity flash-memory device. The mostimportant issue pertaining to the endurance test is the timerequired for the test. To reduce the test time, the proposed testuses the interference between cells as an acceleration factor.Therefore, we introduced a new test scheme in Section III. Inorder to prove the proposed test, we determine the correlationbetween the increasing interference and the RBER to confirmthe acceleration method. Experiments were carried out usingtwo-technology (3×-nm and 2×-nm) NAND-flash devices. Asthe tech-shrink progresses, the value of the acceleration ratioincreases continuously. As a result, the proposed test schemereduces the endurance test time greatly. In addition, the pro-posed scheme requires very small area overhead because ofonly using the existing read only memory (ROM) as shown indraft Section II. From the experimental results, the proposedscheme shows a significant impact on the endurance test andcan be used as a practical solution.

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Jaewon Cha received the M.S. degree in electron-ics engineering from Chonnam National University,Gwangju-si, Korea, in 2004. He is currently pursuingthe Ph.D. degree in electrical and electronic engi-neering with Yonsei University, Seoul, Korea. Hehas been a Design Engineer with the NAND-FlashDesign Group, SK Hynix Semiconductor, Inc.,Icheon-si, Korea, since 2004. His current researchinterests include memory testing, BIST, BISR,design for testability, and device reliability.

Wooheon Kang received the B.S. degree inelectrical and electronic engineering from YonseiUniversity, Seoul, Korea, in 2009, where he iscurrently pursuing the combined Ph.D. degreewith the Department of Electrical and ElectronicEngineering. His current research interests includebuilt-in self-repair, built-in self-testing, built-inredundancy analysis, redundancy analysis algo-rithms, reliability, and very large-scale integrationdesign.

Junsub Chung received the B.S. degree in electricaland electronic engineering from Yonsei University,Seoul, Korea, in 1993. Since 1993, he has beenworking for SK Hynix Semiconductor Inc., Icheon-si, Korea. He joined in the development of NAND

Flash memory. His current research interests arehigh-speed and low-power analog and mixed-signalintegrated circuit designs.

Kunwoo Park received the B.S. degree fromKyungpook National University, Daegu, Korea, andthe M.S. degree from the Korea Advanced Instituteof Science and Technology, Daejeon, Korea, in1989 and 1991, respectively, both in electronicsengineering. He joined Hyundai Electronics, Seoul,Korea, in 1991, where he researched developmentof dynamic random access memory technologies.He was the Head of Nand-flash Design Group,SK Hynix Semiconductor, Inc., Icheon-si, Korea.His current research interests include logic design

methodology, high-speed NAND interface, bit line sense amplifiers, power dis-tribution systems and memories, such as 2-D NAND flash memory and 3-DNAND flash memory.

Sungho Kang received the B.S. degree from SeoulNational University, Seoul, Korea, and the M.S.and Ph.D. degrees in electrical and computer engi-neering from the University of Texas at Austinin 1992. He was a Research Scientist with theSchlumberger Laboratory for Computer Science,Schlumberger Inc. and a Senior Staff Engineer withthe Semiconductor Systems Design Technology,Motorola Inc. Since 1994, he has been a Professorwith the Department of Electrical and ElectronicEngineering, Yonsei University, Seoul, Korea. His

main research interests include very large-scale integration/SOC design andtesting, design for testability, and design for manufacturability.