ieee transactions on industry applications, vol. 52, … · 2017. 5. 26. · ieee transactions on...

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 52, NO. 4, JULY/AUGUST 2016 3267

Dual Comparison One Cycle Control for SinglePhase AC to DC Converters

Nimesh Vamanan and Vinod John, Senior Member, IEEE

Abstract—Resistance emulation using one cycle control (OCC)has been used extensively in single-phase full-bridge boost recti-fiers. This paper proposes a new control strategy called dual com-parison OCC (DC-OCC), which eliminates the limitations of OCC.The advantages of the proposed control strategy is that it ensuresthe average current is equal to grid voltage scaled by emulated re-sistance, in each switching cycle. This eliminates issues such as dcoffset due to the peak current comparison in OCC. It also ensuresthat there is no distortion in current when the converter is lightlyloaded. It is analytically shown that the proposed DC-OCC doesnot have the light load instability concerns of conventional OCC.The proposed method is also shown to achieve unipolar pulse-widthmodulation without sensing the grid voltage resulting in lower ef-fective switching frequency. The proposed control requires onlyone additional comparator and additional logical elements for im-plementation. Detailed simulation and experimental studies arecarried to validate the proposed control and the high performancethat can be obtained.

Index Terms—Current distortionuni-polar pulse-width modula-tion, dual comparison one cycle control, light load operation, onecycle control, steady-state dc offset.

I. INTRODUCTION

ACTIVE rectifiers draw near sinusoidal current from thegrid by shifting the frequency of the dominant harmon-

ics to the switching frequency of the converter [1]–[3]. It alsoregulates the dc bus voltage at a desired level [4]. To draw si-nusoidal current from grid, duty ratio of the switches needs tobe modulated sinusoidally. Of the different control strategies re-ported in the literature, voltage oriented control [1]–[3], [5], [6]and resistance emulation control [7]–[13] are the most popularcontrol techniques to achieve this.

Voltage oriented control has two control loops, outer volt-age loop and inner current loop. Output of outer voltage loopcontroller determines the amplitude of input current requiredto maintain dc-link voltage at desired level [4]. Inner cur-rent loop controller compares the sensed input current with a

Manuscript received November 06, 2015; revised February 26, 2016; acceptedApril 09, 2016. Date of publication April 21, 2016; date of current version July15, 2016. Paper 2015-IPCC-0846.R1, presented at the 2014 International Con-ference on Power Electronics, Drives, and Energy Systems, Mumbai, India, Dec.16–19, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY

APPLICATIONS by the Industrial Power Converter Committee of the IEEE Indus-try Applications Society. This work was supported by the Department of HeavyIndustry, Government of India, under the Off-line and Real-Time Simulators forElectric Vehicle/Hybrid Electric Vehicle Systems Project.

The authors are with the Department of Electrical Engineering, Indian In-stitute of Science, Bengaluru 560012 India (e-mail: [email protected];[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIA.2016.2555903

sinusoidal reference current, generated with the help of unit vec-tors synchronized with grid voltage, which requires grid voltagesensors. Generation of the unit vectors requires a phase-lockedloop to be implemented in the controller [5]. Hence, the im-plementation of overall voltage oriented control structure us-ing analog circuit components is a challenging task. Constantfrequency integration control [7]–[9], scalar resistive emula-tion [12], and one cycle control (OCC) [14], [15], all imple-ments resistive emulation control using peak detection compar-ison method. Converters controlled by aforementioned controlstrategies has a simplified control structure with one explicitvoltage feedback loop, and one controller to maintain dc busvoltage at a desired level [7]–[14], [16]. Output of the volt-age controller is used to generate saw-tooth carrier, which iscompared with the sensed input current, the implicit loop, togenerate gating signals for the active devices. The controllerstructure can be implemented using simple analog and digitalcircuits. Hence, this control technique is better suited for lowcost applications. The controller functionality required for theproposed method can be integrated into application specific in-tegrated circuits which can lead to inexpensive solutions whencompared to low cost microcontrollers.

In this paper, a new control strategy, dual comparison OCC(DC-OCC) is proposed [17]. Here saw-tooth carrier is comparedwith sensed input current and inverted sensed input current togenerate gating signals for the active devices. Hence, both thepeak and the valley of the current is compared with the carrier.This is analytically shown to ensure that the average current isequal to grid voltage scaled by emulated resistance, in a car-rier cycle. Steady-state dc offset is also addressed in [7], butit requires either sensing of input voltage or two additional in-tegrators, making the control strategy more complex. Averagecurrent control proposed in [18], requires an on-time doublercircuit, a zero crossing detector, and bi-directional switch forsensing grid voltage, making the controller structure more com-plex. The proposed control strategy eliminates the steady-statedc offset in input current without additional sensors and cir-cuitry. DC-OCC requires only and additional comparator andsimple digital logic elements for its implementation.

Active rectifiers controlled by conventional OCC (C-OCC),exhibits distortion in input current when converter is loadedlightly and a steady-state dc offset in current drawn by the con-verter under all loading conditions [7]. The distortion at lightloads is shown in [7] to be an outcome of the small-signal in-stability of the converter under C-OCC control. Solutions toremove distortion of input current addressed in [7], [14] in-volves requirement of higher values of filter inductors or addi-tion of a fictitious current term in the controller using additional

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3268 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 52, NO. 4, JULY/AUGUST 2016

Fig. 1. Single-phase full-bridge converter (a) circuit schematic and(b) controller structure of C-OCC.

input voltage sensors. It is analytically shown that the proposedmethod is stable under all load conditions. It also does not exhibitdistortion in current at light loads that is observed in C-OCC.

In C-OCC, the pulse-width modulation (PWM) generated atthe ac side terminals of the converter is bipolar in nature. It isshown that the proposed DC-OCC has unipolar PWM outputresulting in lower total harmonic distortion in the current drawnfrom the grid. This also results in lower effective switchingfrequency of the active rectifier.

Simulation and experimental studies are performed on asingle-phase full-bridge boost rectifier topology, designed at apower level of 605 W, to verify the performance of the proposedcontrol scheme. Section II summarizes C-OCC control law andits drawbacks as discussed in [7]. Modification to the C-OCCto get improved input current and zero steady-state dc offset iscovered in Section III. Stability analysis of the proposed controlstrategy is presented in Section IV. Comparison of the controlstrategies for steady-state operation, with aid of simulation andexperimental studies is presented in Section V. Dynamic perfor-mance of the proposed control strategy is presented in SectionVI and VII concludes the paper.

II. CONVENTIONAL ONE CYCLE CONTROL

Fig. 1(a) and (b) shows a single-phase full-bridge topologyand the controller structure for C-OCC. With all the assump-tions mentioned in [7], control law governing C-OCC can beexpressed as (1),

isRs = Vm (1 − 2d) (1)

where, Vm =VdcRs

Re(2)

is , Rs , Vdc , d and Re are input current, current sensing gain, dcbus voltage, duty ratio of switches 3, 4 and emulated resistance,respectively.

By the control law governing C-OCC, switch states are tog-gled when sensed input current intersects with carrier. So in thistype of control strategy, peak detection comparison method,peak of sensed input current, imx0 , assumes the value vs/Re .

The fundamental input current, the average of instantaneous in-put current for each carrier cycle, drawn by the converter willhave a steady-state dc offset. This phenomenon for low carrierfrequency is shown in Fig. 2(a).

With reference to Fig. 3(a) and the assumptions mentioned in[7], imn0 ≈ imn1

Expected fundamental current = im x0 =vs

Re

(3)

Actual fundamental current =im x0 + im n 0

2=

vs

Re

− Δi

2

where, Δi = im x0 − im n 0 = (vs + Vdc )dTs/Ls .

(4)

C-OCC exhibits distortion in input current when the con-verter is loaded lightly. The distortion in input current is dueto the loss of second intersection point between sensed inputcurrent and carrier. This happens when the slope of falling cur-rent, which is fixed for a particular carrier cycle, is greater thanslope of carrier, determined by the load connected on converter.This phenomenon and its effect on current drawn is shown inFig. 2(b) and (c), respectively. In the literature [7], [14], meth-ods to eliminate mentioned drawbacks are presented, by treatingthem individually. This paper proposes a new control strategy,which is a modification to C-OCC, which is devoid of the abovediscussed drawbacks.

III. DUAL COMPARISON ONE CYCLE CONTROL

Fig. 3(a) shows the inductor current of a single-phase full-bridge converter, for a carrier cycle, when operated using C-OCC. In Fig. 3(a), imn0 , imx0 , imn1 represents inductor currentat start of the switching cycle, peak of current, and current atthe end of the switching cycle, respectively. On inspection, itis observed that the shape of the inductor current, in a carriercycle, is causing steady-state dc offset and distortion in inputcurrent on lightly loaded condition.

So synthesizing a current, in a carrier cycle, such that the av-erage value of current, iavg = vs/Re , with no ripple error andthere is a second intersection point with the carrier will solvethe aforementioned drawbacks. Fig. 3(b) and (c) shows currentin a carrier cycle for positive and negative half cycle of grid volt-age, respectively. In Fig. 3(b) and (c), imn0 , imx0 , i

′mn0 , imn1

represents inductor current at start of cycle, peak of current,valley of current, and current at the end of cycle, respectively.If switching frequency is much greater than grid frequency anddc bus voltage is constant in one switching period, then it canassumed that imn0 ≈ imn1 . This is used to show that there is nooffset in the synthesized output average current.

A. Selection of Switching Sequence

To synthesize inductor current as shown in Fig. 3(b), it isrequired to control peak as well as the valley of the current.So a second comparator is required which will change thestate of the state of switches, when current has reached its ex-pected minimum value. Current shown in Fig. 3(b) has twopositive slopes, m1p and m3p , and one negative slope, m2p .

VAMANAN AND JOHN: DUAL COMPARISON ONE CYCLE CONTROL FOR SINGLE PHASE AC TO DC CONVERTERS 3269

Fig. 2. C-OCC waveforms showing (a) DC offset phenomenon [7], (b) carrier and sensed input current, and (c) input voltage and current when converter isloaded lightly.

Fig. 3. Current in a carrier cycle for positive half cycle of grid voltage (a) C-OCC, (b) DC-OCC, and (c) for negative half cycle of grid voltage, DC-OCC.

TABLE ISELECTED SWITCHING SEQUENCE FOR THE DC-OCC

Grid Time and Switches State ofVoltage Slope ON Converter

vs > 0 t1 , m 1 p = vs /Ls 4, 2 0 0t2 , m 2 p = (vs − Vd c )/Ls 1, 2 1 0

t3 , m 3 p = vs /Ls 1, 3 1 1

vs < 0 t1 , m 1 n = vs /Ls 4, 2 0 0t2 , m 2 n = (vs + Vd c )/Ls 4, 3 0 1

t3 , m 3 n = vs /Ls 1, 3 1 1

In positive half cycle of the grid voltage, two feasible val-ues for positive slope of current is either vs/Ls or (vs +Vdc)/Ls and only feasible value for negative slope of cur-rent is (vs − Vdc)/Ls . Similarly, for current shown in Fig. 3(c)has two negative slopes m1n and m3n and one positive slope,m2n . In negative half cycle of the grid voltage, two feasiblevalues for negative slope of the current is either vs/Ls or(vs − Vdc)/Ls and only feasible value for positive slope of thecurrent is (vs + Vdc)/Ls . In a single-phase full-bridge converterswitch states corresponding to the different current slopes are asfollows.

1) vs/Ls , either switches 2 and 4 or 1 and 3 has to be ON.2) (vs + Vdc)/Ls , switches 3 and 4 has to be ON.3) (vs − Vdc)/Ls , switches 1 and 2 has to be ON.Switching sequence in a carrier cycle for both positive and

negative half cycle grid voltage as summarized in Table I, isselected in order to minimize the number of switchings. Afore-mentioned switching sequence results in same slopes for m1∗and m3∗ (∗ = p. n) in both positive and negative half cycle ofthe grid voltage. This sequence can be achieved in two ways—one by making use of the current and inverted current and secondis by making use of the carrier and inverted carrier. These twomethods can be shown to generate equivalent PWM signals for

the switches of the bridge converter. Fig. 4 shows the controllerstructure to achieve the switching sequence given in Table I. Theselected switching sequence results in uni-polar PWM withouthaving to sense the grid voltage [7], [19].

B. Average Current in a Switching Period

Average current for the wave shape shown in Fig. 3(b) isgiven by

iavg = imn0 +1Ts

[(imx0 − imn0)(t1 + tx)

2

]

− 1Ts

[(imn0 − i

′mn0)(t3 + ty )2

](5)

iavg =i′mn0 + imx0

2. (6)

At intersection points

imx0Rs = Vm

[1 − 2t1

Ts

]and (7)

− i′

mn0Rs = Vm

[1 − 2(Ts − t3)

Ts

]. (8)

Using (6), (7), and (8)

iavg =Vm

Rs

[1 − t1 + t3

Ts

]. (9)

Applying volt-second balance to the boost inductor, Ls

vst1 + (vs − Vdc)t2 + vst3 = 0 (10)

where

t1 + t2 + t3 = Ts.

∴ vs

Vdc=

[1 − t1 + t3

Ts

]. (11)


Fig. 4. Two possible controller structure for DC-OCC (a) current inverted and (b) carrier inverted modulation method. Carrier and current for two switchingcycles (c) current inverted and (d) carrier inverted modulation methods.

TABLE IIDESIRED SWITCHING SEQUENCE TO AVOID DOUBLE SWITCHING

Grid Carrier A B Q Desired state Desired statevoltage cycle of device 1 of device 3

vs > 0

n 0 0 0 OFF OFF

1 0 0 ON OFF

1 1 0 ON ON

n+1 1 1 1 ON ON

1 0 1 ON OFF

0 0 1 OFF OFF

vs < 0

n 0 0 0 OFF OFF

0 1 0 OFF ON

1 1 0 ON ON

n+1 1 1 1 ON ON

0 1 1 OFF ON

0 0 1 OFF OFF

Using (2), (9), and (11)

iavg =vs

Re. (12)

The above analysis is only for the positive half of the gridvoltage. A similar approach is done for the negative half ofgrid voltage and same result as in (12) is obtained. This showsthat the fundamental input current does not have steady-state dcoffset.

By realizing current as shown in Fig. 3(b), the current ref-erence for controller shifts from peak current, as in C-OCC, toboth peak and valley current, thus effectively controlling aver-age current. It is proved that the average current in a carriercycle is equal to vs/Re and removes the steady-state dc offsetin current drawn by the converter. Second intersection point ofcarrier and sensed current is ensured due to addition of secondcomparator, which is comparing two quantities with slopes ofopposite sign. This results minimal distortion for input current.

C. Issue of Double Switching

In DC-OCC, double switching occurs at the end of carriercycle as shown in Fig. 4(c) and (d). With reference to Fig. 4(c),state of converter from 11 and 00, causing double switching atthe end of cycle. The state change, caused by the S-R flip-flop,is unnecessary because both the states apply zero voltage acrossthe terminals of the converter.

Fig. 5. Comparator and modified digital stage that avoids double switchingfor current inversion modulation.

TABLE IIIDESIGN SPECIFICATIONS OF THE AC–DC RECTIFIER

Design specifications Values

Po 605 WVs 110 VVd c 220 Vfs 50 Hzfs w 10 kHzΔ is ( max)

Is ( peak)0.25

Δvdc( max)

Vd c0.05

Table II shows the desired state of devices 1 and 3 for nthand (n + 1)th carrier cycle. An additional input Q, output of Dflip-flop, and output of comparators, A and B, is also shown inTable II. Clock for the D-flip-flop has a frequency of fsw and isthe same signal used for resetting the integrator shown in Fig. 4.Output Q will have a frequency of fsw /2 with a duty ratio of50%. Using Karnaugh maps, the desired states of all devices issimplified as

g1 = QB + QA g4 = g1 (13)

g3 = QA + QB g2 = g3. (14)

The same modification to the digital logic can be used forcurrent inversion and carrier inversion modulation methods,to avoid double switching. Modification to current inversionmodulation method to avoid double switching is shown inFig. 5.

IV. STABILITY ANALYSIS

Stability analysis of the converters controlled by C-OCC andDC-OCC is presented in the section. When the converter isoperating in steady state a small perturbation, δi, is given to the


Fig. 6. Simulation result: Performance comparison of C-OCC (a), (c), (e), (g,) and DC-OCC (b), (d), (f), (h) at rated load (a), (b), (c), (d) 605 W and at lightload (e), (f), (g), (h) 60.5 W. (a), (b) input voltage (scaled by 0.2) and current, (c), (d) dc bus voltage (scaled by 0.05) and output of PI controller, (e), (f) input andoutput signals of comparator/comparators, (g), (h) input voltage (scaled by 0.02) and current.

sensed input current at the start of Nth switching cycle. Effectof perturbation, the coefficient of δi, is calculated for the nextswitching cycles. Conditions for stability is derived from theinequality satisfied by coefficient of δi.

A. Conventional One Cycle Control

Based on the analysis described in Appendix 7A, coefficientof δi has to satisfy the inequality (15) for stability in C-OCC

− 1 < 1 − Rs(ma − mb)maRs + mc

< 1 (15)

where

ma =vs + Vdc

Ls, mb =

vs − Vdc

Ls, mc =

2Vm

Ts.

The two corresponding constraints can be expressed as follows.

1) 1 − Rs(ma − mb)maRs + mc

< 1 gives the condition ma > mb .

2) 1 − Rs(ma − mb)maRs + mc

> −1 gives the condition −vs <

2LsVdc

ReTs.

First inequality is satisfied always and second inequality, isthe same as derived in [7]. This phenomena is described asthe small-signal instability and causes the inequality not to besatisfied at light loads. This causes distortion in grid currentclose to the negative peak of the grid voltage.

B. Dual Comparison One Cycle Control

A similar analysis is carried out for the DC-OCC for condi-tions of positive and negative values of vs . B1) vs > 0: Based


Fig. 7. Simulation result: harmonic spectrum of C-OCC (a, c, e, g) and DC-OCC (b, d, f, h) at rated load (a, b, e, f) 605 W and at light load (c, d, g, h) 60.5 W.(a, b) Harmonic spectrum of current, up to 22.5 kHz, drawn from the grid at rated load, (c, d) harmonic spectrum of current, up to 22.5 kHz, drawn from the grid atlight load, (e, f) low frequency harmonic spectrum of current, up to 500 Hz, drawn from the grid at rated load, (g, h) low frequency harmonic spectrum of current,up to 500 Hz, drawn from the grid at light load.

on the analysis described in Appendix B1, coefficient of δi hasto satisfy the inequality (16) for the stability of DC-OCC forvs > 0

− 1 < 1 − 2mcRs(m1p − m2p)(m1pRs + mc)(mc − m2pRs)

< 1 (16)

where

m1p =vs

Ls, m2p =

vs − Vdc

Ls, mc =

2Vm

Ts.


1) 1 − 2mcRs(m1p − m2p)(m1pRs + mc)(mc − m2pRs)

< 1 gives the condi-

tion vs/Ls > (vs − Vdc)/Ls .

2) 1 − 2mcRs(m1p − m2p)(m1pRs + mc)(mc − m2pRs)

> −1 gives the con-

dition vs(vs − Vdc) <

(2VdcLs

ReTs

)2

.

The above two conditions are satisfied always, because inpositive half cycle instantaneous value of the grid voltage vs isalways less than dc bus voltage Vdc .

B2) vs < 0: Based on the analysis described in Appendix B2,coefficient of δi has to satisfy the inequality (17) for the stabilityof DC-OCC for vs < 0

− 1 < 1 − 2mcRs(m2n − m1n )(m1nRs + mc)(mc − m2nRs)

< 1 (17)

where

m1n =vs

Ls, m2n =

vs + Vdc

Ls, mc =

2Vm

Ts.


1) 1 − 2mcRs(m2n − m1n )(m1nRs + mc)(mc − m2nRs)

< 1 gives the condi-

tion vs/Ls < (vs + Vdc)/Ls .

2) 1 − 2mcRs(m2n − m1n )(m1nRs + mc)(mc − m2nRs)

> −1 gives the con-

dition vs(vs + Vdc) <

(2VdcLs

ReTs

)2

.

The above two conditions are satisfied always, because innegative half cycle instantaneous value of grid voltage vs isalways less than dc bus voltage Vdc . Analysis presented in thissection shows that the proposed DC-OCC control strategy isinherently stable and it will not have the light load distortionsthat is observed in C-OCC.

V. SIMULATION AND EXPERIMENTAL

STUDIES—STEADY-STATE PERFORMANCE

Design specifications of the rectifier is tabulated in Table III.Po, Vs, Vdc are rated power, rated input voltage, and desireddc bus voltage, respectively, fs and fsw are grid frequencyand switching frequency of converter, respectively. Is(peak) andΔis(max) are peak of fundamental input current and maximumpeak-to-peak ripple current, respectively. Δvdc(max) is peak-to-peak ripple in dc bus voltage.

For the above design specifications, the boost inductance anddc bus capacitance are calculated as 5.5 mH (0.086 p.u.) and2200 μF (0.074 p.u.), respectively. Using these design values,detailed simulation studies are carried in MATLAB/Simulink.Of the two ways to implement the DC-OCC, explained inSection III, current inversion modulation method, is used forsimulation and experimental studies.

A. Simulation Studies

Fig. 6 compares the waveforms of the converter operation inC-OCC (a), (c) and DC-OCC (b), (d) at rated load. Fig. 6(a)


Fig. 8. Experimental result: Performance comparison of C-OCC (a), (c), (e), (g), and DC-OCC (b), (d), (f), (h) at rated load (a), (b), (c), (d) 605 W and at lightload (e), (f), (g), (h) 60.5 W. (a), (b) input voltage (CH2: 55 V/Div) and current (CH1: 5 A/Div), (Xdiv: 5 ms), (c, d) dc bus voltage (CH1: 100 V/Div) and outputof PI controller (CH2: 2 V/Div), (Xdiv: 10 ms), (e), (f) input (CH3: 500 mV/div and CH4: 500 mV/div) and output (CH1: 50 V/div and CH2: 50 V/div) signals ofcomparator/comparators, (Xdiv: 50 μs), (g), (h) input voltage (CH2: 55 V/Div) and current (CH2: 1 A/Div), (Xdiv: 5 ms).

Fig. 9. Experimental result: Harmonic spectrum of C-OCC (a), (c), (e), (g) and DC-OCC (b), (d), (f), (h) at rated load (a), (b), (e), (f) 605 W and at light load(c), (d), (g), (h) 60.5 W. (a), (b) harmonic spectrum of current, up to 22.5 kHz, drawn from the grid at rated load, (c), (d) harmonic spectrum of current, up to 22.5kHz, drawn from the grid at light load, (e), (f) low frequency harmonic spectrum of current, up to 500 Hz, drawn from the grid at rated load, (g), (h) low frequencyharmonic spectrum of current, up to 500 Hz, drawn from the grid at light load.


Fig. 10. Voltage at the ac side of the single-phase full-bridge boost con-verter when controlled by (a) C-OCC (Ydiv - 100 V/div and Xdiv - 5 ms) and(b) DC-OCC (Ydiv - 100 V/div and Xdiv - 5 ms) at rated load of 605 W.

and (b) shows current draw by the converter and grid voltage.Fig. 6(c) and (d) shows the dc bus voltage and output of PIcontroller for both the control strategies. Harmonic spectrum,for frequencies upto 22.5 kHz, of grid current drawn by con-verter controlled by both C-OCC and DC-OCC is shown inFig. 7(a) and in Fig. 7(b). In both the control strategies, firstand second switching side bands occurs at 10 and 20 kHz, re-spectively. With reference harmonic spectrum, Fig. 7(a), (b),(c), (d), it can be observed that the magnitude of harmon-ics at switching frequency is lesser for DC-OCC when com-pared with C-OCC. Fig. 7(e) and (f) shows the low-frequencyharmonic spectrum of the grid current for frequencies upto500 Hz. At rated load both the control strategies have com-parable results.

Fig. 6 compares the waveforms of the converter operation inC-OCC (e), (g) and DC-OCC (f), (h) at light load. Fig. 6(e)and (f) shows the input and output signals of the compara-tor/comparators, plotted close to negative zero crossing of gridvoltage, respectively. In Fig. 6(e) and (f), logic 1 and logic 0shows the switching state of switches g1, g2, g3, and g4. DC-OCC does not give a steady-state dc offset in input current atall loads, which is clearly seen in Fig. 6(h). While C-OCC givesa steady dc offset which is more noticeable at light loads [seeFig. 6(g)]. In DC-OCC, due to the second intersection pointbetween carrier and sensed current Fig. 6(f), distortion in cur-rent is absent, which is seen in Fig. 6(h). In C-OCC, the control

TABLE IVCOMPARISON OF SIMULATION RESULTS AND EXPERIMENTAL RESULTS OF

C-OCC AND DC-OCC

Simulation Experimental

Load on Parameters C-OCC DC-OCC C-OCC DC-OCCConverter

Full Load Offset(A) −0.64 0 −0.85 −0.05Offset (%) −12.16 0 −13.9 −0.9THD(%) 9.7 6.55 10.28 6.93

Light Load Offset(A) −0.4962 0 −0.64 -0.025Offset(%) −89.45 0 −77.5 −4.06THD(%) 67.65 45.32 68.04 46.41

of falling input current is lost [see Fig. 6(e)]. This can be no-ticed by the fact that the current falling slope is greater than theslope of the carrier and barely touches the carrier at the end ofthe switching cycle. This results in distortion of current drawnby the converter controlled by C-OCC [see Fig. 6(g)]. It canbe observed that for a given integrator reset rate the effectiveswitching of the DC-OCC is half that of C-OCC. Harmonicspectrum, for frequencies upto 22.5 kHz, of grid current drawnby converter controlled by both C-OCC and DC-OCC at lightload is shown in Fig. 7(c) and (d). Fig. 7(g) and (h) showsthe harmonic spectrum of the grid current for frequencies upto500 Hz. Presence of dc offset, in current, for a converter con-trolled by C-OCC is clearly visible in the harmonic spectrum,Fig. 7(e) and (g).

Peak to peak ripple in current drawn changes from zero cross-ing of grid voltage, in C-OCC, to peak of grid voltage, in DC-OCC, which can be clearly seen in Fig. 6(g) and (h). The changein mode of operation from bi-polar, in C-OCC, to uni-polar, inDC-OCC, results in shifting of occurrence of peak to peak rip-ple. It can also be observed that the current ripple is reduced inthe proposed DC-OCC.

Table IV summarizes the simulation results when the con-verter is operating with C-OCC and DC-OCC. at rated loadand at light load. DC-OCC has zero steady-state dc offset ininput current when the converter is loaded fully or lightly, whencompared with C-OCC, offset is expressed as a fraction of fun-damental input current. It can be observed that the dc offsetconcern can be effectively addressed by the proposed DC-OCC.

B. Experimental Studies

Single-phase full-bridge converter, shown in Fig. 1(a), is builtin laboratory to verify to effectiveness of DC-OCC. Fig. 8 com-pares the waveforms of the converter operation in C-OCC (a),(c) and DC-OCC (b), (d) at rated load. Fig. 8(a) and (b) showsthe input current and grid voltage. Presence of lower order har-monics makes the grid voltage flat topped, this can be seen inwaveform of grid voltage vs . Fig. 8(c) and (d) shows dc busvoltage and output of proportional integral (PI) controller. Atrated load both the control strategies has comparable results.

Fig. 8 compares the waveforms of the converter operation inC-OCC (e), (g) and DC-OCC (f), (h) at light load. Input andoutput signals of the comparator for C-OCC and DC-OCC


Fig. 11. Simulation (a), (b) and experimental (c), (d) results showing the tracking of controller when a step change in reference from 220 V to 195 V is given.(a) DC bus voltage reference and feedback (scaled by a factor of 70), (b) grid voltage (scaled by 0.2) and current drawn from grid, (c) dc bus voltage reference(CH2: 500 mV/div) and feedback (CH3: 500 mV/div), voltage sensing gain is 1/70, (d) grid voltage (CH1: 200 V/div) and current drawn from grid (CH2: 10A/div).

(a) (b) (c) (d)

Fig. 12. Simulation (a), (b) and experimental (c), (d) results for step change in load power from rated load to half rated load is given. (a) Output of PI controllerand dc bus voltage feedback (scaled by a factor of 70), (b) grid voltage (scaled by 0.2) and current drawn from grid, (e) output of PI controller (inverted, CH3: 1V/div) dc bus voltage feedback (CH2: 500 mV/div), (f) grid voltage (CH1: 100 V/div) and current drawn from grid (CH2: 5 A/div).

Fig. 13. Simulation (a), (b) and experimental (c), (d) results for grid voltage variations, from 110 to 95 V is given. (a) Output of PI controller and dc bus voltagefeedback (scaled by a factor of 70), (b) grid voltage (scaled by 0.2) and current drawn from grid, (e) output of PI controller (inverted, CH3: 1 V/div) dc bus voltagefeedback (CH2: 500 mV/div), (f) grid voltage (CH1: 100 V/div) and current drawn from grid (CH2: 5 A/div).

is shown in Fig. 8(e) and (f), respectively. Fig. 8(g) and (h)shows current drawn by the converter and grid voltage. Cur-rent drawn by the converter, controlled by DC-OCC has dcoffset close to zero and lesser distortion. Harmonic spectrumof the current drawn by the converter when controlled by C-OCC an DC-OCC is shown in Fig. 9(a), (b), (c), and (d).Low-frequency harmonic spectrum is shown in Fig. 9(e), (f),(g), and (h). Simulation and experimental harmonic spectrummatches closely. Fig. 10 shows the voltage across the ac-sideterminals of the single-phase full-bridge boost converter whenconverter is operated in C-OCC [see Fig. 10(a)] and DC-OCC[see Fig. 10(b)]. Converter controlled by C-OCC operates in bi-polar mode and when controlled by DC-OCC converter operatesin uni-polar mode, which can be seen from Fig. 10(a) and (b),respectively.

Table IV summarizes the experimental results. Experimentalresults closely match with the simulation results. In simulation,the devices are assumed ideal and the current sensor has no dcoffset too, unlike in the experimental studies. The deviation inexperimental and simulation results is less than 1.3% at full loadand 1.1% at no load.

VI. DYNAMIC PERFORMANCE OF DC-OCC

Dynamic performance, with the aid of experimental and sim-ulation studies, of the proposed control strategy, DC-OCC,is presented in this section. Dynamic performance evalu-ated includes reference tracking and disturbance rejection.Load disturbance and grid voltage disturbance transients arestudied for the DC-OCC.

A. Reference Tracking

Step change in reference voltage (nominal voltage −25 V)is given and its effects is shown in simulation, Fig. 11(a) and(b) and in experiment, Fig. 11(c) and (d). Fig. 11(a) and (c)shows feedback (waveform with 100 Hz ripple) tracking thereference and Fig. 11(b) and (d) shows the grid voltage andcurrent drawn from grid. It can be observed that current drawnfrom grid decreases when the reference voltage decreases, this isbecause the load power decreases and grid voltage is maintainedconstant. Settling time of the dc bus voltage is found to be closeto 80 ms, both in simulation and experiment. Simulation andexperimental results shows the reference tracking capability ofthe proposed control technique.


B. Load Disturbance

Step change in load power, from rated load to half rated loadis given and its effects is shown in simulation Fig. 12(a) and (b),and in experiment, Fig. 12(c) and (d). Fig. 12(a) and (c) showsthe output of the PI controller and dc bus voltage feedback. Whenload power changes, the emulated resistance Re and; hence, theoutput of the PI controller Vm also changes. Fig. 12(b) and(d) shows the grid voltage and current drawn from the grid.Settling time of the system is found to be close to 220 ms,both in simulation and experiment. Simulation and experimentalshows the rejection capability of the control technique for loaddisturbances.

C. Grid Voltage Disturbance

Effects of grid voltage variations (nominal voltage −15 V) inthe proposed control technique is shown in simulation, Fig. 13(a)and (b), and in experiment, Fig. 13(c) and (d). Fig. 13(a) and(c) shows the output of the PI controller and dc bus voltagefeedback. When grid voltage decreases/increases, the currentdrawn from the grid also increases/decreases, because the loadpower is constant, so the emulated resistance Re and, hence, theoutput of the PI controller Vm also varies. Fig. 13(b) and (d)shows the grid voltage and current drawn from the grid. Settlingtime of the system is found to be close to 220 ms. Simulationand experimental shows the rejection capability of the controltechnique for grid voltage disturbances.

VII. CONCLUSION

In this paper, a new control strategy, DC-OCC, is proposed.The proposed control strategy ensures that the average current ina switching cycle is equal to the current reference by controllingthe switching action at both peak and valley of current. DC-OCCdoes not exhibit steady-state dc offset in grid current drawn.The stability analysis on the proposed DC-OCC indicates thatit is stable under all operating conditions. This ensures thatthere are no light load distortions in grid current drawn. Theproposed control requires only one additional comparator andadditional logical elements for implementation. The proposedcontrol has the same number of switchings in a carrier cyclewhen compared with C-OCC. DC-OCC implements uni-polarPWM for the single-phase full-bridge boost converter withouthaving to sense the grid voltage. Double switching at the end ofthe carrier cycle, which is unnecessary, is avoided by appropriatelogic. This logic halves the switching frequency of the devicesand gives lower total harmonic distortion and smaller steady-state dc offset when compared with C-OCC. The viability of DC-OCC and its comparison with C-OCC is confirmed and validatedusing time domain simulations and experimental studies.

APPENDIX

A. Conventional One Cycle Control

Fig. 14 shows sensed input current and carrier when the con-verter is operating in steady state. A disturbance of δi is given atthe start of the switching cycle is given, shown as dotted lines,

Fig. 14. Stability of operating point in converter controlled by C-OCC.

and its effect at the start of next switching cycle is calculated.At steady-state first intersection point between the carrier andsensed input current, i.e., at t = ton

Vm − mcton = (imn(N ) + maton )Rs (18)

ton =Vm − imn(N )Rs

maRs + mc

toff = Ts − ton (19)

imn(N +1) = imn(N ) + (ma − mb)ton + mbTs. (20)

If there is a disturbance of δi at the start of switching cycle then

Vm − mct′

on = (imn(N ) + δi + mat′

on )Rs (21)

t′

on =Vm − imn(N )Rs

maRs + mc− δi Rs

maRs + mc

t′

off = Ts − t′

on (22)

Let,K1 =Rs(ma − mb)maRs + mc

(23)

i′

mn(N +1) = imn(N +1) + δi(1 − K1) (24)

i′

mn(N +2) = imn(N +2) + δi(1 − K1)2 . (25)

B. Dual Comparison One Cycle Control

In positive and negative half of grid voltage, sensed inputcurrent has different values of slope, for t2 duration. So onaccount of this stability, analysis for positive and negative halfcycle of grid voltage is carried out separately and presented.

1) vs > 0: Fig. 15 shows sensed input current and carrierwhen the converter is operating in steady state. A disturbanceof δi is given at the start of the switching cycle is given, shownas dotted lines, and its effect at the start of next switching cycleis calculated. In steady state, at first intersection point betweenthe carrier and sensed input current, i.e., at t = t1

Vm − mct1 = (imn(N ) + m1p t1)Rs (26)

t1 =Vm − imn(N )Rs

mc + m1pRs. (27)


Fig. 15. Stability of operating point in converter controlled by DC-OCC forvs > 0.

At the second intersection point, i.e., t = t1 + t2

Vm − mc(t1 + t2) = − (imn(N ) + m1p t1 + m2p t2)Rs (28)

t2 =Vm + imn(N )Rs

mc − m2pRs+ t1

m1pRs − mc

mc − m2pRs

(29)

t3 = Ts − (t1 + t2)

t3 = Ts −Vm + imn(N )Rs

mc − m2pRs

− t1m1pRs − m2pRs

mc − m2pRs(30)

imn(N +1) = imn(N ) + m1p(t1 + t3) + m2p(t2).(31)

If a disturbance of value δi is given to sensed input current atthe start of switching cycle then

Vm − mct′

1 = (imn(N ) + δi + m1p t′

1)Rs (32)

t′

1 = t1 −δiRs

mc + m1pRs(33)

Vm − mc(t′

1 + t′

2) = −(imn(N ) + δi + m1p t′

1 + m2p t′

2)Rs

(34)

t′

2 = t2 + δi2mcRs

(mc − m2pRs)(m1pRs + mc)(35)

t′

3 = Ts − (t′

1 + t′

2)

t′

3 = t3 − δiRs(mc + m2pRs)

(mc − m2pRs)(m1pRs + mc)(36)

i′

mn(N +1) = imn(N ) + δi + m1p(t′

1 + t′

3) + m2p(t′

2)(37)

Let, K2 =2mcRs(m1p − m2p)

(m1pRs + mc)(mc − m2pRs)(38)

i′

mn(N +1) = imn(N +1) + δi(1 − K2) (39)

i′

mn(N +2) = imn(N +2) + δi(1 − K2)2 . (40)

Fig. 16. Stability of operating point in converter controlled by DC-OCC forvs < 0.

2) vs < 0: Fig. 16 shows sensed input current and carrierwhen the converter is operating in steady state in negative halfcycle of grid voltage. In steady state, at first intersection pointbetween the carrier and sensed input current, i.e., at t = t1

Vm − mct1 = −(imn(N ) + m1n t1)Rs (41)

t1 =Vm + imn(N )Rs

mc − m1nRs. (42)

At the second intersection point, i.e., t = t1 + t2

Vm − mc(t1 + t2) = (imn(N ) + m1n t1 + m2n t2)Rs (43)

t2 =Vm − imn(N )Rs

mc + m2nRs− t1

m1nRs + mc

mc + m2nRs

(44)

t3 = Ts − (t1 + t2)

t3 = Ts −Vm − imn(N )Rs

mc + m2nRs

− t1m2nRs − m1nRs

mc + m2nRs(45)

imn(N +1) = imn(N ) + m1n (t1 + t3) + m2n (t2).(46)

If a disturbance of value δi is given to the sensed input currentat the start of switching cycle then

Vm − mct′

1 = −(imn(N ) + δi + m1n t′

1)Rs (47)

t′

1 = t1 +δiRs

mc − m1nRs(48)

Vm − mc(t′

1 + t′

2) = (imn(N ) + δi + m1n t′

1 + m2n t′

2)Rs

(49)

t′

2 = t2 − δi2mcRs

(mc + m2nRs)(mc − m1nRs)(50)

t′

3 = Ts − (t′

1 + t′

2)

t′

3 = t3 − δiRs(m2nRs − mc)

(mc + m2nRs)(mc − m1nRs)

(51)


i′

mn(N +1) = imn(N ) + δi + m1n (t′

1 + t′

3) + m2n (t′

2) (52)

Let, K3 =2mcRs(m2n − m1n )

(mc − m1nRs)(mc + m2nRs)(53)

i′

mn(N +1) = imn(N +1) + δi(1 − K3) (54)

i′

mn(N +2) = imn(N +2) + δi(1 − K3)2 . (55)

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Nimesh Vamanan received the B.Tech. degreein electrical and electronics engineering from theCollege of Engineering Thiruvananthapuram,Kerala, India, in 2004, and the M.Tech. degree inpower electronics and power systems from the IndianInstitute of Technology, Mumbai, Maharashtra,India, in 2008.

He is curently a Research Student with theIndian Institute of Science, Bangalore, Karnataka,India. His primary areas of interest are in powerelectronics, focusing on control of grid connectedconverters.

Vinod John (S’92–M’00–SM’09) received theB.Tech. degree in electrical engineering from the In-dian Institute of Technology Madras, Chennai, India,in 1992; the M.S.E.E. degree from the Universityof Minnesota, Minneapolis, MN, USA, in 1994; andthe Ph.D.degree from the University of Wisconsin–Madison, Madison, WI, USA, in 1999.

He has worked in research and development posi-tions at GE Global Research, Niskayuna, NY, USA,and at Northern Power, Barre, VT, USA. He is cur-rently an Associate Professor with the Indian Institute

of Science, Bangalore, India. His primary areas of interest are in power elec-tronics and distributed generation, power quality, high-power converters, andmotor drives.

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