The 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON)Nov. 5-8, 2007, Taipei, Taiwan

A Single-Stage AC/DC Converter with HighPower Factor, Regulated Bus Voltage and Output

VoltageDylan Dah-Chuen Lu

School of Electricaland Information Engineering,The University of Sydney,

Australia

Herbert Ho-Ching IuSchool of Electrical, Electronic

and Computer Engineering,The University of Western Australia,

Australia

Velibor PjevalicaJP "Srbijagas", Narodnog Fronta,

21000 Novi Sad,Serbia

Abstract- Unlike existing single-stage AC/DC converterwith uncontrolled intermediate bus voltage, a new single-stage AC/DC converter achieving power factor correction(PFC), intermediate bus voltage output regulation and outputvoltage regulation is proposed. The converter is formed byintegrating a boost PFC converter with a two-switch clampedflyback converter into a single power stage circuit. Thecurrent stress of the main power switch is reduced dueto separated conduction period of the two source currentsflowing through the power switch. A dual-loop currentmode controller is proposed to achieve PFC, and ensureindependent bus voltage and output voltage regulations.Experimental results on a 24V/100W hardware prototype aregiven to confirm the theoretical analysis and performance ofthe proposed converter.

1. INTRODUCTION

Series connection of a power factor correction (PFC)circuit such as boost converter with an isolated DC/DCconverter such as flyback and forward converters is a com-mon practice to implement both power factor correctionand fast output regulation of off-line power supplies. Inorder to reduce the circuit and control system complexityand to lower the total cost that suitable for low powerapplications, single-stage power-factor-corrected (S2PFC)AC/DC converters have been introduced [1]-[6]. The twopower stages of the PFC circuit and the DC/DC converterare simplified by sharing a common switch (or a pairof switches). By allowing the boost inductor to operatein discontinuous conduction mode (DCM), PFC and fastoutput regulation can be performed simultaneously usinga single-loop voltage feedback controller.Among existing S2PFC converters, the single-switch

type S2PFC converter is found low cost and compact.However, the voltage spike caused by the leakage energyof transformer has to be dealt with to protect the switchfrom exceeding the maximum tolerable voltage and toreduce switching loss. To overcome this problem, vari-ous passive and active snubber circuits are proposed tosuppress the voltage stress on the switch and to dissipateor recycle the leakage energy the snubbers stored. Two-transistor clamped isolated converter is useful in clamping

the switch stresses to the input voltage as well as recyclingthe leakage energy back to the source. Fig. 1 shows aS2PFC converter which integrated a boost converter intoa two-transistor clamped flyback converter and shared thesame switch SI based on S2PFC concept in [1]-[6]. S1and S2 are synchronized in action so that when they areturned on, the inductors L1 and Lm are both charged uplinearly by input voltage IVinl and storage capacitor CBrespectively. When the switches turn off, the energy storedin L1 and Lm are transferred to the storage capacitor andthe load respectively. The leakage energy is transferredback to the storage capacitor and the switches are clampledto the intermediate bus voltage VB.The two main problems in S2PFC converter are the

high voltage stress across the storage capacitor and extracurrent stress on the switch (or a pair of switches) whencompared with the two-stage approach. In this paper,a new S2PFC converter derived from novel integrationof boost converter and two-transistor clamped isolatedconverter is proposed. In summary, the proposed converterhas the following advantages: 1) The proposed S2PFCconverter gives simultaneous PFC, bus voltage regula-tion and fast output regulation which are not possiblein existing S2PFC converter; 2) No additional switches,such as range switch, are needed to implement universalinput range applications; 3) The current stress of the twopower switches is lower than that of the single-switch (ormultiple-switch) S2PFC converter circuits; 4) High powerfactor as there is no deadband of input current around thezero crossing of the line input voltage; 5) Stand-by modeis possible that saves power and reduces loss.

II. PRINCIPLE OF OPERATION

A. Circuit descriptionThe proposed boost-flyback S2PFC converter is shown

in Fig. 2. It consists of an input inductor L1, a two-transistor (SI and S2) clamped flyback converter withtransformer TI and a storage capacitor CB. Inductor L1is used to shape the input current for PFC function andto feed CB. Transformer TI with turns ratio N is used

1-4244-0783-4/07/$20.00 C 2007 IEEE 1455

to store energy from CB and couple the energy stored inthe magnetizing inductance Lm to output load at transistorturn-off period. Storage capacitor CB serves as a storageelement for absorption of power imbalance between inputand output powers as well as maintains output voltageconstant. Diodes Di and D2 are used to recycle theleakage energy in TI back to CB and to clamp thedrain-to-source voltages of S2 and SI to bus voltage VBsimultaneously. D3 is a bypass diode for charging of CBto provide necessary housekeeping power at start-up. OnceVB rises and becomes higher than input voltage, D3 isreverse biased.

B. Circuit operationTo simplify the analysis of operation, it is assumed that

all semiconductor devices are ideal. The capacitances ofCB and CO are so large that the ripple voltage on them arenegligible; VB and VO are constant dc voltage sources. Therectified input voltage IVin is essentially constant withineach switching cycle as the switching frequency fs(=1/T) is much higher than the line frequency. Finally, theboost inductor Li works in DCM whereas the primaryinductance of flyback transformer Lm operates in CCM.To illustrate the principle of operation of the proposed

boost-flyback S2PFC converter, Fig. 3 shows the keytheoretical waveforms within two switching cycles. In thesteady state, there are four modes of operation. Note thatthe input voltage and bridge rectifier have been modeledas a voltage source in series with a diode DB. Before thetime t = To, switches SI and S2 are turned off and nocurrent is flowing in the primary side (i.e. iLl = p= tDl=tD2 = 0). Meanwhile, diode DO is in conduction state andtransformer TI continues delivering energy to output VOthrough current iDo.Mode 1 (To- T): Both the switches SI and S2 are

closed. As the intermediate bus voltage VB is higher thanthe rectified input voltage IVin at all times, the bridgediodes are reverse biased. Therefore inductor L, is notcharging and iLl is zero. Capacitor CB is dischargedthrough S2 - Lm - S1. Energy is being stored in theflyback transformer TI and the current iP increases linearlywith a slope

dip VBdt Lm(

A blocking voltage equals VB/N + VO is applied acrossoutput diode DO and DO is reversed biased. The outputvoltage VO is sustained by CO. Note that only one voltagesource (i.e. CB) provides the current of two switches,which equals ip(t -To).Mode 2 (T -T2): Mode 2 is initiated by turning off

S2 while SI remains in on-state. The parallel capacitanceof S2 is charged up so that the drain-to-source voltage ofS2, VDS2, rises towards VB until it is clamped by VB.During this period, the energy stored in TI cannot becoupled to output as SI is still closed. Because iP cannotsustain a sudden change of current direction, Di is turned

on to maintain the current flow in TI. The voltage appliedacross primary winding of TI is thus zero (assume Di haszero forward voltage drop). Namely, TI is free-wheelingwithin this interval and the rate of change of iP is zero.Meanwhile, the rectified input voltage is applied on Liand Li is charged up linearly with a slope

diLldt

|Vin| (2)By the KCL the current into node X (as shown in Fig. 2)equals the current out of the node, we have the followingrelationship

tLl + tDl = tP (3)

Therefore the current in Di is not a constant but isdecreasing with the expression given by

tVinitDl =ip(Ti)- Li (t- TO)

where ip(Ti) is the peak of ip at time equals Ti. Itshould be noted that the current of power switch SI duringthis mode equals iP and is clamped at ip(Ti), withoutincreasing current stress even tLl is charging up.Mode 3 (T2 -T3): Mode 3 is begun when SI is also

turned off. The parallel capacitance of SI is charged by iP.The drain-to-source voltage of SI, VDS1, rises towards VB.When VDS1 rises slight above VB, D2 is forward biased.VDS1 is clamped at VB and VDS2 is reduced to NV,. Onceagain, inductor current i cannot sustain a sudden changeof current direction, D2 provides the path to maintain thecurrent of Ll. The stored energy in Li is being transferredto CB through Lm and D2 with a downslope equals

diLi VB - |vi NV0 5dt Li

As point X reaches VB- NV0, a blocking voltage isset up on Di and Di is reverse biased. As the dottedends of TI is positive with respect to the non-dotted endsand voltage across primary side rises and becomes slightlyover NV0, DO is forward biased and the energy stored inTI is transferred to the load. iDo conducts with a rate ofchange of current equals

diDo N(VB-R vi -NVo)dt Li

N2V

Lm (6)Mode 4 (T3 -T4): This mode is started when iLl has

decreased to zero. Note that Mode 4 must exist, otherwisethe transfer of energy stored in L1 to CB has not yetcompleted and iLl will enter CCM. A sudden rise intLl would occur that causes high input current harmonicsdistortion. Transformer TI continues to deliver the rest ofenergy to output through D,. The rate of change of currentin DO is negative and equals

diD0 _ N2V0 (7)dt Lm

After some time SI and S2 turns on again to begin thenext switching cycle, the operation described above willrepeat.

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(4)

III. CONTROL

The main objective of the control system is to find asimple and effective way to control the two switches S1and S2 so that PFC is achieved, the bus voltage VB andthe output voltage V0 are regulated as line and load vary.

A. Power Factor Correction (PFC)

Given that the input voltage is a rectified sinusoidalwave, i.e. lvi,l = Vm sirotw, where w and Vm are theangular frequency and the peak value of line input voltage.Assume the inductor works in DCM, the instantaneousinput current is obtained by averaging the inductor currentover a switching period, which is given by

2L, Fsi(w (t) (8)

whereFUt) Vm sinwt

9

F(wt)=VB NV (9)

As long as L1 works in DCM throughout the line cycle,tLl flows into the converter for every switching period(i.e., in Mode 2) and duty cycle d3 keeps relatively con-stant, PFC is achieved automatically because L1 functionsas a boost inductor. At Mode 2, when S2 is turned off andSI remains on, the input current flows into the converterand charges L1 linearly. As seen from (2), as soon asinput voltage lVinl increases from zero, there is alwaysinput current flows through L1.

In order to obtain good power factor of the proposedconverter, all the parameters in (8) should be kept rela-tively constant, except for the sine term which changesaccording to input line voltage. The bus voltage VBcontains twice the line frequency voltage ripple becauseit serves as a buffer to balance the difference of inputand output powers. The control loop of PFC should havea cutoff frequency far behind the line frequency to avoidinput current distortion and therefore its response is slowerthan that of the DC/DC counterpart. This implies dutycycle d3 is relatively constant throughout the line halfperiod.The converter operates in fixed frequency, the non-linear

factor would be the function F(wt) which will cause inputcurrent distortion. From (9), it shows that the higher thebus voltage VB and the smaller turns ratio N and theoutput voltage VO, the smaller F(wt) will be. The inputcurrent is less distorted at low line than that of at high lineas the effect of non-linearity of (9) is smaller. However,such input current distortion still allows the converter topass the international standards such as IEC 61000-3-2, aswill be proved by the experimental results in Section V.

B. Bus Voltage RegulationAt start-up, the bus voltage is essentially zero though

residual charge may exist. When input voltage appliesacross the converter input terminals, the storage capacitorCB is charged up via D3. The presence of D3 also

prevents the inductor from saturation at start-up. The busvoltage rises to the peak value of input voltage. Theconverter begins to deliver energy to CB through L1 andVB rises gradually to the designed reference value. The busvoltage is sensed and regulated by controlling the durationof energy stored in L1 during Mode 2. At Mode 3, energystored in L1 will be delivered to CB. Therefore, Modes 2and 3 are dedicated for PFC and bus voltage regulation.

C. Output Voltage Regulation

The bus voltage is used to provide regulation of outputvoltage VO. This happens during Mode 1, when bothswitches SI and S2 are turned on. At mean to full load,transformer TI is working in CCM. Even there exists largeload current variation, the change of duty cycle in thismode is slight. It is due to the negative current feedbackthat the transformer regulates its primary current accordingto the demand of secondary current. As seen from (7),the rate of change of output diode current is proportionalto the output voltage VO. For example, if a decrease ofload (or a increase of load resistance RO) occurs, theinstantaneous output current is constant and causes VOto increase. This steepens the downslope of output diodecurrent. The primary transformer current will be decreasedso less current is drawn from CB. When the load becomeslight, TI may work in DCM. The duty cycle can varyfreely in this mode to keep output constant as there isno other current path. Therefore, Mode 1 is dedicated foroutput voltage regulation.

D. Current Mode Control

Even though voltage mode control is the simplest wayto achieve control purposes, current mode control monitorscircuit currents to provide fast response and protectionfrom abnormal operations such as over-current. Peak cur-rent mode control can be achieved easily on the DC/DCpart by sensing the current of switch SI directly througha resistor R1 which is placed in series with SI, as shownin Fig. 2. The PFC part is implemented also using peakcurrent mode control. One of the direct methods to sensethe inductor (or input) current is by placing a resistorR2 in the return path, as shown in Fig. 2. Althoughthe PFC operates with constant duty cycle d3 and peakcurrent limit, the average inductor current indeed changesproportionally with input voltage to shape input current, asseen from (5). For example, when |vi, increases, the rateof change of iLl decreases and the discharge period d4T,extends. As input voltage is in series with the current path,more current flows into the converter and tL1 increase asa result.The controls on VO and on VB are independent due

to the circuit configuration that allows independent powerprocessing stages and independent currents paths for mon-itoring and regulating of VO and VB. It can be seen fromFig. 3 that during Mode 1, only flyback DC/DC partis working. No current from line input flows into the

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circuit. The current through R1 equals the bus capacitordischarging current. During Mode 2, flyback transformercurrent is constant while boost inductor current iLl buildsup. The current through R2 is 'Ll only.

E. Control Realization

Fig. 4 shows the simplified schematic of the proposeddual-loop current mode control for the proposed converter.Both loops are triggered by the same clock to havesynchronized ON pulse. When a clock pulse is generated,both SI and S2 go to high state. At start-up, CB is chargedup and able to couple energy to output through TI. Thefirst loop (upper circuit in Fig. 4) is used for output voltageregulation. The output voltage is sensed by the invertinginput of the error amplifier E/A 1 with compensationnetwork, and an error control voltage v,1 is generated.v,1 is compared to the switch current of SI by comparatorPWM 1 to produce desired off duty cycle for S2 throughthe D-type flip-flop (FF1). The second loop (lower circuitin Fig. 4) is used for PFC and bus voltage regulation.The bus voltage is detected by the inverting input of theerror amplifier E/A 2 with compensation network, andan error control voltage Vc2 is generated. Vc2 is summedwith the inductor L1 current and compared to ground bycomparator PWM 2 to produce desired off duty cycle forSI through the D-type flip-flop (FF2). SI will not go tolow state until PWM1 commands S2 to turn off and currentis then flowing through R2 (in Fig. 2) to pull point Bnegative when peak inductor current is reached.

In the design of the controller, on one hand, the com-pensation network by E/A2 is of slow response, which hasaround 10-20Hz of cutoff frequency, to avoid the 100Hz acripple from bus capacitor being amplified and cause inputcurrent distortion eventually. On the other hand, E/Al isof fast response to provide tight output regulation.

IV. CURRENT STRESS ON POWER SWITCHES

For conventional S2PFC converter such as in Fig. 1,when both switches S1 and S2 are closed, currents fromline input lVW and storage capacitor VB inject into S1simultaneously. Suppose the on-state resistance of S1 isexpressed as R(DS)ON, the conduction loss P0onl of theswitch S1 is given by

Pconl (ILI + ip)2R(DS)ONIL2IR(DS)ON + ipR(DS)ON + 2ILlipR(DS)ON

(10)

where IL, and iP are the boost inductor current andstorage capacitor discharging current through TI respec-tively. From (10), apart from the individual conductionloss there is an extra loss term 2ILjipR(DS)ON. Thisexplains why conventional S2PFC converters have higherpower dissipation and lower total efficiency than thatof conventional two-stage PFC voltage regulator whenallowing two individual currents to flow through the sameswitch simultaneously.

Reduction of switch current stress of the proposedconverter is achieved by separating the current injectinginto S1 from the two voltage sources (bus voltage VB andrectified input voltage lVin ). Since VB is always higherthan vin , when S1 and S2 are turned on only currentfrom CB is flowing through the switches because thebridge rectifier is reverse biased. When S2 is turned offbut S1 is kept on, the current from CB ceases so that inputcurrent can flow through S1. By inspecting the waveformsin Fig. 3, the switch current of S1 is equal to ip from Toto T2. And during period T1 to T2 the switch current isclamped to the peak current of ip due to D1. Thereforethe conduction loss on S1 is reduced to

Pcon2 =ipR(DS)ON. (1 1)

Due to the circuit operation, a conduction loss on Dequals

PD1 = (iL2,pk -iLl)VDd3TS (12)

is observed at Mode 2, where VD is the voltage drop onD1. By using a low voltage drop diode such as Schottky-barrier diode the loss can be kept to minimal. The currentstress in S2 for both S2PFC converter in Fig. 1 andproposed one is the same as the two-transistor clampedflyback converter.

V. EXPERIMENTAL RESULTS

Suppose we choose vi,=OOVrms L1=510,uH,Lm=3.05mH, LK=0.OlLm and N=2.5, as the low linehas the highest input current.

Fig. 5 shows the critical switching waveforms of theconverter. We can observe that when the inductor currentrises, the transformer primary current (same as the switchcurrent from To to T2) stays flat. It confirms the discussionin Section II.The input voltage and filtered input current of the

converter at 110V and 240V line voltages and at full loadcondition is shown in Figs. 6 and 7 respectively. These fig-ures show close agreement with the theoretical line currentwaveforms of DCM PFC operation. As shown in Fig. 8,power factor is greater than 0.94 for entire input range andabove 20% of load. Fig. 9 shows that the converter attainslow current harmonics which complies with both Class Aand D limits of IEC 61000-3-2, though the input currentis not purely sinusoidal. As the experimental input currentis obtained with a non-ideal sinusoidal voltage, the inputcurrent may be further distorted when pure sinusoidalvoltage is applied. However, as the present input currentharmonics, as shown in Fig. 9, are much below the limit,there is room for further adjustment as discussed in SectionIII.A.The bus voltage is tightly regulated at 400V throughout

entire line and load conditions due to the integrated but in-dependent converter structure and control which make thesimultaneous control of bus and output voltages possible.

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Fig. 1. Previous S2PFC converter based on boost and two-transistorclamped flyback converters [1]-[5].

Apart from steady state performance, the transient re-sponse of the converter is tested under step change ofload between 40% to 100%, as shown in Fig. 10. Theoutput voltage settles after 2.5ms with less than 1V ofovershoot/undershoot. From the measurement of our ex-periment, the conversion efficiency reaches 80% or aboveat full load for entire line voltage range and for input240V(rms).

VI. CONCLUSION

This paper presents with verifications of experimentalresults the true single stage PFC (S2PFC) converter con-cept - PFC, regulation of bus and output voltages at thesame time. The key idea is to construct the power circuitso that current from two input sources (AC main and buscapacitor) can be separately controlled. Therefore, thoughthe two power stages share the same power switches, onlyone of the two currents passes the switches at a time withineach switching period. Current stress on power switchesis also reduced as a result. Moreover, by deliberatelyrestricting the current from AC main, the converter canwork at stand-by mode with energy saving, which canhardly be implemented in existing S2PFC converters.

REFERENCES

[1] M. Madigan, R. Erickson, and E. Ismail, "Integrated high qualityrectifier regulators," in IEEE Power Electronics Specialists Conf,1992, pp. 1043-1051.

[2] R. Redl, L. Balogh, and N. 0. Sokal, " A new family of singlestage isolated power factor correctors with fast regulation of theoutput voltage," in IEEE Power Electronics Specialists Conf, 1994,pp. 1137-1144.

[3] R. Redl, and L. Balogh, " Design consideration for single stageisolated power factor corrected power supplies with fast regulationof the output voltage" in IEEE Power Electronics Specialists Conf,1995, pp. 454-458.

[4] M. Daniele, P. K. Jain, and G. Joos, "A single-stage power-factor-corrected AC/DC converter," IEEE Trans. Power Electron., vol. 14,no. 6, pp. 1046-1053, Nov. 1999.

[5] D. M. Divan, G. Venkataramanan, and C. Chen, " A unity powerfactor forward converter," in IEEE Ind. Appl. Society Annual Meet.,1992, pp. 666-672.

[6] C. Qiao and K.M. Smedley, "A topology survey of single-stagepower factor corrector with a boost type input-current-shaper," IEEETrans. Power Electron., vol. 16, no. 3, pp. 360-368, May 2001.

Fig. 2. Proposed S2PFC converter based on new integration of boostand two-transistor clamped flyback converters.

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Fig. 3. Key switching waveforms of the proposed S2PFC converterduring two successful switching period.

Fig. 4. Configuration of adopted dual-loop current mode PWM controlin simplified version.

1459

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Fig. 5. Switching waveforms: Switch SI drain-to-source current (uppertrace) and inductor current iLl (lower trace). Scale: 2A/Div; 2A/Div.

110 120 140

Input voltage 20 230 24

Fig. 8. Power factor for entire line and load ranges.

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

Fig. 6. Waveforms for input voltage vi, and filtered input current Iinfor input voltage lOV (rms) and line frequency 50 Hz. Scale: 5OV/Div;2A/Div.

Fig. 9. Input current harmonics for input voltage 240V (rms) and fullload 4A.

Fig. 7. Waveforms for input voltage vi, and filtered input current Iin Fig. 10. Transient response between 40% and 100% of load. Upper:for input voltage 240V (rms) and line frequency 50 Hz. Scale: lOOV/Div; output current 1o (4A/Div); lower: output voltage VO (0.5V/Div).0.25A/Div.

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