Monostable-Bistable Threshold Logic Elements in a Fully Complementary Optical Receiver Circuit for High Frequency Applications

Andreas Matiss; Artur Poloczek; Wolfgang Brockerhoff; Werner Prost; Franz-Josef Tegude Solid-State Electronics Department

University of Duisburg-Essen Duisburg, Germany

andreas.matiss@uni-due.de

Abstract—A fully complementary optical receiver design is presented utilizing two Monostable-Bistable Threshold Logic Elements, consisting of four Resonant Tunneling Diodes and a pin-photodetector in one circuitry. By complementary on and off switching of the two Monostable-Bistable Logic Elements it is possible to double the sampling rate of the optically generated photocurrent. Measurements on fabricated circuits have shown functionality up to 13.2 Gbit/s.

Monostable; Bistable; Resonant Tunneling Diodes; Optical Receiver

I.

II. III.

INTRODUCTION The application of resonant tunneling diodes in monostable

bistable threshold logic elements (MOBILE) is well known for more than one decade [1], [2]. Pin-photodiodes have been used to optically control the switching behavior of the MOBILE and to directly sample an incident optical signal stream. Therefore, MOBILE have been applied in simple optical demultiplexers up to high frequencies [3], [4]. In order to sample every incident bit of such an optical signal, it is necessary to clock the MOBILE with the frequency of the incident signal. In this paper a complementary circuit setup using two MOBILE connected to one pin-photodiode is discussed that overcomes the limitation of the sampling rate when using only one MOBILE. By employing two MOBILE to each node of the photodiode [5] it is possible to reduce the sampling frequency and therefore doubling the maximum data rate that can be processed by the complementary receiver circuit. Measurements of a realized demultiplexer on InP-substrate are also presented.

DEVICE TECHNOLOGY The layer stack was grown by metal organic vapour phase

epitaxy (MOVPE) on a s.i.-InP substrate. The double barrier structure consists of 5 nm lattice matched InGaAs-well sandwiched between lattice mismatched InAlAs barrier layers with a nominal thickness of five monolayers. In order to realize ohmic contacts, the double barrier structure is sandwiched between n+-doped InGaAs layers.

The RTDs were processed using optical lithography. After evaporating the upper contact metallisation (Ti/Pt/Au), the first mesa etching was performed by an anisotropic ICP-RIE dry etching system using Cl2/N2 chemistry in order to control the underetching of the upper electrode. Afterwards, a wet etching step was added to achieve a defined undercut of the upper contact, which is necessary for self aligned devices. Then, the lower mesa was etched using wet chemistry, only, and the lower electrode was realized. For high yield, the mesa structure is covered with a polymide (Durimide®) up to the pad contact of the small-size upper electrode (AE=1.5x1.5 µm2). In the next step the polymide was removed from the top contact area, only, by an anisotropic blanket O2-plasma etching. This leads to an improved yield because short circuits due to possible misalignments are prevented. Finally, the devices were placed into a series connection forming a monostable bistable threshold logic element (figure 1).

Figure 1 SEM image of the resonant tunneling diodes in MOBILE configuration employing a self-aligned metallisation process.

RTDdriver

RTDload

COMPLEMENTARY MOBILE CIRCUIT The MOBILE consists of two InGaAs / InAlAs RTD with

different areas which are connected in series [6]. By adding an external current, in this paper provided by the pin-photodiode, to the common node between the RTDs, the switching behavior can be controlled when a clock voltage is applied. Depending on the current, the output of the MOBILE corresponds to either 'low' or 'high' values, which also depend on the applied voltage polarity. Since the RTDs are symmetrical in their IV-

electricaldata out(RZ)

Iph

RTD1,load

RTD2,loadR

TD1,

driv

erR

TD2,

driv

er

V1,out,neg

V2,out,pos

V1,clk,neg

V2,clk,pos

optical fibre

V2,ref,pos

V1,ref,neg

opticaldata in(NRZ)

MOBILE 1

MOBILE 2

Figure 2 Circuit schematic of complementary MOBILE optical receiver circuit with double sampling rate

MOBILE 1

V2,clk,pos

Ipos

Ineg

V1,clk,neg

RTDdriver

RTDdriver

RTDload

RTDload

Ineg=I1+Ipin

Ipos=I2-Ipin

Ipin=0Ipin>0

Ipin=0Ipin>0

V2,out,low V2,out,high

V1,out,lowV1,out,high

MOBILE 2

∆IPeak

∆IPeak

Ipin=0

Ipin=0

Ipin>∆IPeak

Ipin>∆IPeak

V1,ref,neg=V2,ref,pos=0 V

AL>AT

Figure 3 Operation principle of co

characteristic [7], the MOBILE can be driven with positive and negative voltages. Figure 2 presents the complementary circuit design that has been investigated in this paper. The upper MOBILE 1 operates in the negative voltage regime and is connected to the anode of the pin-photodiode. The area of the load RTD is larger than the area of the driver RTD (see figure 1 also) resulting in an inverted transfer characteristic (e.g. when the input is 'low' the output is 'high'). The lower MOBILE 2 is driven in the positive voltage regime and connected to the cathode of the pin-photodiode. Equivalent load to driver area ratio as described for MOBILE 1 is also used for MOBILE 2. The clock voltage for both MOBILE has the same frequency and amplitude, but different DC offsets within the respective voltage regime of each MOBILE.

IV. SWITCHING PROPERTIES A

In the proposed circuit the loadthe driver RTD area AD (AL = 13results in automatically switchingclock voltage if no current is MOBILE 1 and 2. The simulated IVthe RTD/MOBILE setup is givencurrent source provides one MOBIand the other one with a negative cvoltages have to be in the oppoMOBILE 2 is driven with positive

s.i. InP substrate

HFERTD

PIN

anode

cathodedrain

gaupper contaktlower contakt

RTD-layers

InP-HFET-layers InP-HEMT-layers

THEM

RTPI

i-InGaAs

n-InGaAs

p-InGaAs

n+

n+

n+ n+

Figure 4 Integration concept for monolithical integration on InP-substrate

mplementary MOBILE gate

ND IV-CHARACTERISTICS RTD area AL is larger than µm²; AD = 10 µm²), which of the output with rising applied to the nodes of characteristics [8], [9] for

in figure 3. Because the LE with a positive current urrent, the respective clock site polarity regime. The

clock voltages and receives

T

tesource

opologies:T: 120 nmD: 570 nmN: 650 nm

a negative input current. Compared to the driver RTD, the load RTD has a larger peak current. The external current will cause a shift of the load line parallel to the current axis. If the driver peak current becomes larger than the load peak following the following criteria

, ,peak driver peak load photocurrentI I I> − (1) Beele

the MOBILE output voltage will not switch anymore and remain in the low state. The MOBILE complementary switching can be achieved by using one common clock signal source. Employing two bias-tees, each MOBILE input will get either a positive or negative DC offset. The advantage of using a common clock AC signal is the autocorrelation of the two outputs and the minimized phase error during the sampling process.

Figure 3 shows the corresponding IV characteristic for the load and driver configuration of both MOBILE. The reference voltages in the diagram are set to zero volt. Both cases for high and low output condition are shown in dependency on the incident photocurrent Ipin.

V.

VI.

INTEGRATION CONCEPT AND REALIZATION The topology cross view of the monolithic integration is

presented in figure 4, showing the position of the devices in the layer stack. The pin-photodiode is designed to absorb a vertically incident optical signal with a wavelength of 1550 nm. Typical active diameters in the realized circuit are 15 µm and 20 µm with a 3dB cut-off frequency of 10 GHz in the presented design.

The resonant tunneling diodes are located in between the pin-layer stack and the HEMT-layers. A double barrier quantum well structure consisting of InAlAs/InGaAs/InAlAs is shown in figure 4.

A chip die photograph is shown in figure 5. In the center of the circuitry, the pin-diode and the two MOBILE can be seen.

cause MOBILE are very sensitive to current drop, high-ctron mobility transistors (HEMT) are employed as source

followers in output buffer stages to decouple the MOBILE stages against the low 50 Ω impedances in the surrounding system setup. This stage is located on the right-hand side in figure 5.

MEASUREMENT RESULTS The test circuit measurement has been performed using a

continuous laser source at 1550 nm optical wavelength to drive

the phas modu

75

V /

mV

Figu6

Figure 5. Measurement results of the proposed gate for clock frequencies of 6.6 GHz showing the capability of sampling a 13.2 Gbit/s optical signal

Aan oncleavalso frequsampmeasbeenabsor

Usampfrequdemoand whileonceBecapolar

in-diode. For optical modulatbeen used together with an lator (EAM) with 13.2 Gbit/s

29,5 30,0 30,5-75

-50

-25

0

25

50

0 1000

out

time

pos neg

optical bit-pattern: '00001111'

fclk=6.6GHzfda

re 6. Measurement results of the pro.6 GHz showing the capability of sam

ll measurements have been do-wafer probe station with highed optical fibre for vertical ingenerated by the bit pattern genency of the data stream (fcling oscilloscope has been urement results. An optical c modulated with a '00001111' bption modulator.

sing the on-wafer probe statling functionality was possiency and 6.6 Gbit/s incidentnstrates that every bit sent is

data rates are correlated. Whe maintaining the clock rate,

, thus handling a data rate twicuse both MOBILE operateities, the outputs of the circuit

ion, a bit pattern generator 1.55 µm electro-absorption bandwidth.

31,0 31,5 32,0

111

/ ns

ta=6.6GBit/s

posed gate for clock frequencies of pling a 13.2 Gbit/s optical signal

ne directly on-wafer using -frequency probe tips and a jection. The clock signal is erator and correlated to the

lk=fdata). A 50 GHz digital employed to capture the ontinuous wave signal has it pattern using the electro-

ion, the verification of the ble up to 6.6 GHz clock signal bit rate. Figure 6 sampled two times if clock n the data rate is doubled every bit will be sampled e as high as the clock rate. with different voltage

s also show complementary

on and off switching behavior, which has to be corrected using an inverter stage for further signal processing.

VII. CONCLUSION By employing two MOBILE, one to each node of the pin-

photodiode, and complementary switching them on and off, the possibility to double the maximum sampling rate is demonstrated and thus significantly improves the maximum processed data rate. The concept has been demonstrated by high-speed measurements of high optical bitrates up to 13.2 Gbit/s.

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[3] Sano, K., Murata, K., Akeyoshi, T., Shimizu, N., Otsuji, T., Osaka, J. & Sano, E., "Ultrafast optoelectronic time-division demultiplexer IC using resonant tunneling diodes and a unitraveling-carrier photodiode", Technical Digest. Summaries of papers presented at the Conference on Lasers and Electro-Optics, 1998. CLEO 98., pp. 499-500, 3-8 May 1998

[4] K. Sano, K. Murata, T. Otsuji, T. Akeyoshi, N. Shimizu, E. Sano, “An 80-Gb/s Optoelectronic Delayed Flip-Fflop IC Using Resonant Tunneling Diodes and Uni-Traveling-Carrier Photodiode”, IEEE Journal of Solid State Circuits, vol.36, no.2, pp.281-289, February 2001

[5] Matiss, A., Prost, W. & Tegude, F., "Optoelectronic 1:2 demultiplexing based on resonant tunnelling diodes and pin-photodetectors", Electronics Letters, vol. 42, no. 10, pp. 599-600, 11 May 2006

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[8] Yan, Z. & Deen, M., "New RTD large-signal DC model suitable for PSPICE", Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 14, no. 2, pp. 167-172, Feb. 1995

[9] Q. Liu, A. Seabaugh, P. Chamhal, F.J. Morris, “Unified AC Model for the Resonant Tunneling Diode”, IEEE Transactions on electron devices, vol. 51, no. 5, pp. 653-657, May 2004.