978-1-61284-736-8/11/$26.00 ©2011 IEEE 161 27th IEEE SEMI-THERM Symposium

Temperature Sensors Modeling for Smart Power ICs

K.O. Petrosyants, N.I. Rjabov Moscow State Institute of Electronics and Mathematics (Technical University)

3, Bolshoy Trekhsvyatitelsky per., 109028 Moscow, Russia eande@miem.edu.ru

Abstract

The computational model of the temperature sensors integrated on the IC chip with power transistors is developed. The 2D/3D problem of sensor placement is mathematically described by the classic heat transfer equation coupled with the equation for current density distribution. It is shown that parasitic effects of sensor current displacement and thermo-emf generation resulting from a temperature gradients (Seebeck effect) must be taken into account. For this purpose the special differential equation is introduced. The examples of point- and strip-like temperature sensors modeling for power BJTs and ICs are demonstrated.

Keywords Temperature sensors, power transistors, smart power IC,

heat transfer, temperature distribution, Seebeck effect.

1. Introduction Smart power IC and modules are advanced hardware

components for industrial automatics, robotechnics, automotive electronics, avionics, telecommunication, peripheral units, measurement technique, home appliances, signaling, monitoring equipment. Particularities of smart power ICs are: 1) power output devices placement on one IC chip with low-power control and protection circuits, logics, AD and DA converters, memories; 2) heavy duty operation: with high current (above 1 �), voltage (1000 V), temperature (125 - 150 0�); 3) high requirements for linearity, sensitivity of sensors and analog elements; 4) operation with inductive load (motor, generator, relay windings).

So the protection circuits are usually used to provide the failure-free operation of smart power ICs. The temperature sensors built-in IC chip are the key elements limiting the junction temperature. Small-size low current BJTs and MOSFETs are suitable as temperature sensors. In practice BJTs and diodes have essential advantages over MOS transistors in sensitivity and stability for a wide range of temperatures.

Two configurations of temperature sensors: point-like (in the form of small-size circles, quadrates or rectangles) and strip-like (in the form of long narrow strips) are often used.

The forward biased emitter – base p-n junction voltage VBE is the main output electrical parameter identifying the temperature in primitive sensor model:

2

00

0

( )BE BE T TT TV T V S T Q

T� ��

� � � � ��

, (1)

where: �0 –predetermined medium temperature of p-n – junction; VBE0 - voltage independent on transistor layout and

small dependent on physical parameters; ST and QT - coefficients independent on temperature and dependent on transistor layout [1].

Formula (1) represents the quadratic dependence VBE on T. The difference between voltages VBE of two adjacent matched transistors, having essentially different emitter squares SE1 and SE2, is used to obtain a linear dependence. This difference is directly proportional to the absolute temperature (Proportional To the Absolute Temperature – PTAT):

1 21 2

1 2

ln lnC Cptat BE BE

S E S E

I IkTV V Vq J S J S �� � � �

� � � �� � � � �� � � �

,

or

1 2

2 1

ln C Eptat ptat

C E

I SkTV S Tq I S

� �� �� �

� , (2)

where coefficient Sptat is independent on technological parameters.

Placement of temperature sensors in power IC constructions is a difficult task. It is desirable to displace p-n junction – sensor in the IC chip region with maximal temperature. Therefore it is necessary to calculate temperature distribution in power devices and ICs.

2. Numerical Model of IC Temperature Distribution

Fig. 1. Multi-layer IC Construction

Mathematical model of electro-thermal processes in power semiconductor devices and ICs is based on three-dimensional heat-transfer equation for multi-layer rectangular parallelepiped (fig. 1) with nonlinear boundary condition in combination with equation for current density [2]:

Petrosyants, Temperature Sensors Modeling for Smart Power .. 27th IEEE SEMI-THERM Symposium

2 2 2

2 2 2 0T T Tx y z

� � �� � �

� � � , (3)

10

( , , )

( ( , ,0), ), ( , )0, ( , )

z

E

E

T P x y TzV J T x y U x y S

x y S

��� �

� � �

� ��� �� ��

(4a)

1 1

10 0

1 1

,

( , , 0) ( , , 0),2,3,..., ,

z z

T Tz z

T x y z T x y z� �

� �

� �

� �� �� �

� �

� �

�� �

� �

�

� � ��

(4b)

0 0

0,

( , , ) ,C Cx x x y y y

PACK

T T T Tx x y y

T x y z T const�

� � � �� � � �� � � �

� � � �

� �

(4c)

( ( , ,0), )ES

J T x y U dxdy I const� ��� , (5)

where: T – chip temperature; �� - heat conductivity for �-layer; P – power density; J – current density; V – voltage on device contacts (for BJT – collector-emitter voltage); U – control voltage (for BJT - base-emitter voltage); TPACK – package temperature; I – device current; � - number of layers; SEL – device heat-dissipating square.

3D heat-transfer equation (3) with boundary conditions (4) is solved in combination with 2D integral equation for current density (5).

The software tool Overheat [3] was developed for numerical solution of nonlinear problem (3) – (5) using quasilinearization iterative method in combination with fast Fourier transformation (FFT) method.

Using calculated IC structure temperature distribution it is possible to analyze the thermal regime influence on sensor electrical characteristics.

3. Point Sensors Placement On fig. 2 are shown temperature distributions on chip

surface of power BJTs with different emitter configuration, located in common base region. Transistors are fabricated using bipolar power analog IC technology with project layout norms 2 μm.

It is seen, that the “spots” with maximal temperatures are located in active power emitter regions. Therefore passive emitters - sensors are located in free segments of base, adjacent to most heated regions, particularly: for the transistor with dumb-belled layout (fig. 2a) emitter – sensor is placed between isotherms 4 and 5; for figured layout (fig. 2b) - on isotherm 5; for stripped layout (fig. 2c) - on isotherm 4. In table 1 are listed maximal temperature, sensor temperature and their difference �� for each transistor.

a) dumb-belled

b) figured

c) striped Fig. 2. 2D Temperature Distributions in Power BJTs with Different Layouts

Number Transistor’s type

�MAX, K �SENS, K ��, �

1 dumb-belled 379 340 39 2 figured 372 356 16 3 striped 370 336 34

Table 1: Maximal p-n - junction temperature, sensor temperature and their difference.

It is necessary to take into account the difference between maximal and sensor temperatures for sensor calibration and thermal protection circuit design.

4. Stripped Sensors The strip-like sensors are built in active regions of power

devices to measure the maximal junction temperature �MAX, so the temperature difference ��=�MAX-�SENS is removed.

Petrosyants, Temperature Sensors Modeling for Smart Power .. 27th IEEE SEMI-THERM Symposium

In fig. 3 is shown an example of stripped sensor placement in power BJT. The emitter – sensor is located in active base region between two power BJT emitter rows and monitors the maximal device temperature. In this case the temperature difference is ��=0.

Fig. 3 Power multiple-emitter bipolar transistor with stripped emitter – sensor

Fig. 4 Layouts of temperature sensors: a) base contact is a stripe along emitter, b) base contact is a little area at the end.

Fig. 5 Experimental temperature distribution on voltage stabilizer IC chip surface

We consider two configurations of p-n junction sensors with long narrow strip emitter (see fig. 4): a) base contact is a metal strip along emitter, in this case sensor base is equipotential (see fig. 3); b) base contact is a metallized pad at one of the ends, in this case it is necessary to take into account distribution of base potential [3].

Fig. 6. Layout of voltage stabilizer and isotherms on device surface

However, for stripped sensors it is necessary to take into account two parasitic effects absent in point sensors: 1) voltage drop �BE caused by base and/or emitter current flows along stripped emitter - sensor, 2) appearance of additional thermo-emf, caused by temperature gradient along sensor strip (Seebeck effect). The first effect in BJT is well-known, the second effect is illustrated by the example of power voltage stabilizer K142EN9, fabricated using bipolar power analog IC technology with project layout norms 2.5-3 μm and surface resistances �BPAS=200 Ohm/square, �E=4 Ohm/square. The power BJTs are placed close together on the chip and are heating each other. The situation is shown in fig. 5 and fig. 6 for IC electrical regime: VIN=40 V, VOUT=27 V, P=3.7 W. Experimental temperature distribution on the IC chip surface (see fig 5) was measured using IR thermovision camera A-40 FLIR Systems. Computing results developed with tool Overheat are presented in fig. 6. It is seen that a good agreement between measured and designed 2D temperature distributions was achieved. The temperature of most heated power BJT is irregularly distributed along sensor stripe (see curve 1 in fig. 7.). Temperature gradient along sensor (curve 2 in fig. 7) generates Seebeck thermo-emf [4]. It adds to potentials of emitter �E and base �B regions.

Both effects can introduce significant error into chip temperature measurement.

Mathematical model of sensor electro-thermal regime takes into account both mentioned above effects:

2 2

2 2( ) ( )Nd kL d T Jd q d

�� � �

�� � �

� �� � � , (6)

where: �=E,B; � - floating co-ordinate along sensor (x or y); �� - potential; ��=1/( �h) – surface resistance of region

Petrosyants, Temperature Sensors Modeling for Smart Power .. 27th IEEE SEMI-THERM Symposium

(Ohm/square); - specific conductance of semiconductor layer; � - specific thermo-emf, dependent on Fermi level, bandgap and physical parameters of semiconductor region [4]; LN=ln(Nc/Nd) - for n-type semiconductor, LN=-ln(Nv/Na) - p- type; Nd, Na – donor and acceptor concentration; w,h - width and thickness of sensor region; J(�) – current density through sensor p-n junction; q – electron charge; k – Boltzmann constant; T – absolute temperature, preliminarily calculated with tool Overheat by solving equation (3) - (5) for power device or IC, in which the sensor is built-in (see curve 1 in fig. 7).

First term in left side of equation (6) describes the shift of potential �BE caused by current flow along sensor stripe; second term – thermo-emf caused by temperature gradient.

Boundary conditions for the equation (6) are the following:

a) on sensor contact the electrical potential is constant and equal to external applied voltage:

( )CONT const�� � � , (7)

b) on opposite end of sensor the whole current, resulting from both potential gradient and temperature gradient, is equal to zero:

( ) 0Nd kL dTd q d

��

��

� �� � � . (8)

The sensor current is the current of emitter - base p-n junction:

2

1

( , , )E E B EJ T wd I�

�

� � � �� , (9)

where: �1,�2 – initial and final values of co-ordinate along sensor strip.

Temperature distribution T(�) in equations (6) – (9) was calculated preliminarily using tool Overheat. Only one equation (6) for emitter potential is solved for sensor layout fig. 4a, and two equations (6) for emitter and base potentials - for fig. 4b.

For solving equations (6-9) we have used the algorithm based on finite differences, Newton-Kantorovich and sweep methods. The results of simultaneous solution of equations (6) with boundary conditions (7-8) and integral equation (9) for two sensor configurations are shown in fig. 7. The applied base contact voltage was 0.7 V.

Curve 3 – base-emitter voltage distribution taking into account only one effect of voltage drop caused by emitter current flow; 4 - base-emitter voltage distribution taking into account both effects – voltage drop and Seebeck thermo-emf.

It is seen in fig. 7, that sensor p-n junction voltage VBE varies along the co-ordinate �. Maximal voltage decrease along sensor p-n junction strip is �VBE=30 mV for sensor fig. 4.a (24 mV – voltage drop caused by current displacement; 6 mV – Seebeck thermo-emf) and 85 mV for fig. 4.b (72 mV – voltage drop caused by current displacement; 13 mV – Seebeck thermo-emf).

a)

b)

Fig. 7 Temperature distribution along stripped sensor (designed - curve 1, measured - �), its derivative (curve 2); voltage VBE without (curve 3) and with (curve 4) Seebeck effect for sensors fig. 4,a and fig. 4,b.

Thus voltage VBE determining the temperature T in (1) or

(2) is not satisfactory characteristic for strip sensors. For these sensors it is necessary to use the emitter current IE defined by (9) as an output informative value. In fig. 8 are shown dependences of maximal p-n – junction temperature on emitter – sensor current for sensors fig. 4.a,b which were designed using (6) – (9) model. It is possible to define in fig. 8 the maximal p-n – junction temperature of power transistor for measured value of sensor current IESENS. For example, in case the voltage stabilizer (fig. 6) dissipates power P=3.7 W the sensor current is IE=0.25 mA and maximal p-n – junction temperature is TMAX=356 K; in case P=15 W the appropriate values are IE=1.0 mA and TMAX=407 K.

If the primitive model (1) is used, the proper values of TMAX are significantly lower: 340 K and 372 K. So the temperature measurement errors are 16 K and 35 K. It is too

Petrosyants, Temperature Sensors Modeling for Smart Power .. 27th IEEE SEMI-THERM Symposium

much for power ICs, particularly voltage regulators and power amplifiers. In opinion of semiconductor device designers from National Semiconductors Corp. the error in limiting temperature over the production distribution can not be more ±15 0C, exclusive of severe hot-spot problems [4].

Fig. 8 Maximal temperature vs sensor current for different models.

5. Conclusions 1. The adequacy of temperature sensors models is

discussed. It is demonstrated that the primitive temperature model (1)

is valid only for point-like p-n – junction sensors. In most practical cases the device maximal IC p-n – junction temperature can be identified adding to the sensor measured temperature value TSENS more precise definition �T (see table 1).

2. It is shown that the primitive model (1) is not valid for strip-like temperature sensors built in structures of power transistors.

3. The two-level model has been developed for temperature calculation of p-n – junction sensors built in constructions of smart power ICs.

First level model is described by three-dimensional heat-transfer equation for multilayer rectangular parallelepiped (3) with boundary conditions (4,5), which is solved by numerical methods to obtain 3D temperature distribution in power device IC structure. This model takes into account thermal coupling of components placed on chip. For temperature calculation of point sensors it is sufficed to use first level model.

Second level model considers parasitic effects of current displacement and thermo-emf resulting from temperature gradient (Seebeck effect), in sensors built in structures of power transistors and other components of IC. This model is described by equation (6) with boundary conditions (7-9) and is solved by numerical methods. The parasitic effects of current displacement along sensors stripe and thermo-emf resulting from temperature gradient (Seebeck effect) must be taken into account. Only second level model is valid for temperature calculation in strip-like sensors.

4. It is shown that forward-biased p-n – junction voltage VBE varies along strip length in strip-like sensors, and therefore it is not a satisfactory characteristic for the temperature. For strip-like sensors it is necessary to use the emitter current IE as an output informative value.

5. The examples of point- and strip-like temperature sensors modeling for power BJTs and IC are demonstrated. The temperature measurement error is discussed.

References 1. R.A. Bianchi, F. Vinci Dos Santos, J.M. Karam, B.

Courtois, F Pressecq, S. Sifflet. CMOS compatible temperature sensor based on the lateral bipolar transistor for very wide temperature range applications // Sensors and Actuators. 1998. V. A 71, N 1, p.p. 3-9.

2. K.O. Petrosjanc, N.I. Rjabov, I.A. Kharitonov, P.A. Kozynko. Thermal Design System for Chip- and Board-level Electronic Components. Proceedings of IEEE East-West Design & Test Symposium (EWDTS’09). Moscow, Russia, September 18 – 21, 2009, p.p. 247-250.

3. K.O. Petrosjanc, N.I. Ryabov, I.A. Kharitonov, P.A. Kozynko Electro-thermal simulation: a new Subsystem in Mentor Graphics IC Design Flow // Proceedings of 15th International Workshop on THERMal INvestigation of ICs and Systems (THERMINIC 2009). – Leuven, Belgium, 2009. pp. 70-74

4. R.J. Widlar, M. Yamatake, Dynamic Safe-Area Protection for Power Transistors Employs Peak-Temperature Limiting. IEEE Journal of Solid-State Circuits. 1987, v. SC-22, N 1, p. 77-83.

5. H.F. Wolf. Semiconductors. Wiley Interscience, New York, 1971.

This work was supported by Russian Foundation for Basic Research, grant 10-02-00689