Grand Challenges of Nanoelectronics and Possible Architectural Solutions What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to Do with Moore

Valeriu Beiu College of Information Technology, United Arab Emirates University

Al Jimi 2, PO Box 17555, Al Ain, Abu Dhabi Emirate, United Arab Emirates Centers for Neural Inspired Nano Architectures (www.cnina.org)

vbeiu@uaeu.ac.ae

Abstract

This presentation will discuss the many challenges

faced by the design of future tera-scale integrated circuits that result from the use of nano-scale electronic devices. The relations among these challenges will be studied, and a relative ranking will be proposed. Afterwards, we shall delve into the most difficult challenges. Finally, possible solutions will also be suggested. 1. Introduction

In the nano era, which we have entered, the growing complexity of integrated circuits (ICs) turns difficult problems (e.g., power, reliability) into great challenges. Also, communication problems lead to network-on-chip and force (partly) asynchronous solutions. Out of the many nanoelectronics challenges, we shall focus here on those for which an architectural approach could make a difference. A review of the nanoelectronic devices currently being investigated is presented in Fig. 1. As can be seen, most of them are only at the level of single devices.

In this presentation we shall: (i) identify many challenges amenable to architectural approaches; (ii) briefly detail some of these challenges; (iii) rank a selected set of challenges based on both first-order and second-order effects; and (iv) enumerate some of the plausible architectural solutions. 1. Grand challenges

We believe that the following set of challenges is particularly amenable to architectural solutions:

• power-heat P/H – have to be reduced (this also includes power delivery/distribution, heat removal, and dealing with hot spots);

• reliability REL – has to be increased through redundancy in space, or time, or both, but the redundancy factors should be (very) small;

• testing TST – associated costs have to be reduced;

• connectivity CONN – has to be reduced both as overall length, and as number of connections;

• communication COMM – method has to be optimized;

• hybrid integration HYB – must be achieved in the near term, including mixed design and interfacing;

• logic and (en)coding L/C – must be optimized to reduce switching, computations, and communications (e.g., non-Boolean, error correction, spikes).

Other challenges, which might be considered, are algorithmic improvements ALG (e.g., probabilistic), and reduced design complexity DCOM (e.g., by reuse).

Our first goal will be to rank these challenges with respect to their importance, when considering not only their own intrinsic importance, but also how improving on one challenge would affect the other challenges. We have tried to correlate all these challenges as can be seen in Fig. 2. The first column contains the challenges described before. The first step was to assign an “importance” (percentage) to each of the challenges. These are shown in the second column. P/H was rated the highest at 25%, while the other challenges were assigned lower percentages, with all of them totaling 100%. Our next step was to fill the correlation matrix, which is shown in the remainder of the spreadsheet. It contains coefficients that reflect

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07)0-7695-2831-7/07 $20.00 © 2007

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Fig. 1. The roadmap for nanotechnology presents many nano devices currently being investigated as an alternative to standardCMOS. As can be seen, for most of them only single devices have been realized and tested.

second-order effects, namely how a solution improving on a particular challenge will affect the other challenges. Let us take CONN as an example (i.e., the fourth column in the correlation matrix):

• Reducing CONN (number of connections and/or the overall length of the connections) should reduce P/H. This shows a positive influence. We have decided that the influence factor is ‘medium’.

• CONN influences REL in a complex manner. The overall number of wires (connections) of a reliable design should be about the same as for an unreliable one, so apparently enhancing CONN should not make REL any easier or harder. On a closer look, the total length of the wires might be increased in a redundant design (needed for enhancing REL), even if the number of connections is not. This explains the ‘small’ negative influence, since

CONN would make redundant design slightly more difficult. [Remark: The problem is even more complex, since one should consider both faulty devices and faulty wires].

• CONN might affect TST in an adverse way, because fewer connections might make testing more difficult. Hence, a ‘small-to-medium’ negative influence.

• CONN clearly influences COMM, because reducing or shortening connections would make it more difficult to implement an optimal communication. Therefore, a negative ‘medium’ has been assigned.

• CONN does not seem to influence HYB, since the difficulty of hybrid design is not affected by the connectivity of its parts.

• CONN has a ‘small’ negative effect on L/C, as it might allow only for a sub-optimum encoding.

% 25% 15% 12% 12% 12% 12% 12%P/H REL TST CONN COMM HYB L/C ALG DCOM

Power / Heat 25% P/H -10% -5% 15% 15% 10% 10% 10%Reliability 15% REL 15% 5% -5% -10% 10% 5%Testing 12% TST 25% -10% 5% -5% 5% 5%Connectivity 12% CONN 5% -5% -20% 5% 5% 5% 5%Communication 12% CoMM 5% 5% -15% -10% 5% 10% 5%Hybrid 12% HYB 5%Logic / Coding 12% L/C 5% 5% -5% 5%

Algorithms ALG -5% 15% -5% 5%Design complexity DCOM -10% -10% -5% 10% -10% -10% 5%

Overall 30% 15% 9% 9% 13% 9% 14%

Fig. 2. Ranking nanoelectronic architectural challenges (i.e., challenges where architecture can make a difference).

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07)0-7695-2831-7/07 $20.00 © 2007

After repeating this procedure for all the columns in the correlation matrix, we have quantified small, small-to-medium, medium, medium-to-large, and large influences in a percentage scale as 5%, 10%, 15%, 20%, and 25%, respectively. Obviously this is subjective, but should be good enough to give us an idea of the overall importance of each challenge. This overall importance takes into account the importance initially assigned to the challenge (second column), together with the weighted sum of the second-order effects over all the other entries in each column. The results can be seen in the last row in Fig. 2. They show that: P/H becomes more important (25→30%); REL maintains its importance (15→15%); L/C (12→14%) and COMM (12→13%) increase slightly; while TST, CONN, and HYB are decreasing (12→9%).

Because power has been discussed many times, we shall present in the following a brief on reliability. 3. On the reliability challenge

Ever since humans first fashioned tools, they have had to ponder on their reliability, and cope with the consequences of their failure. The unprecedented complexity of our electronic gadgets in the digital age has given rise to the study and practice of fault-tolerance, with the objective of delivering acceptable operation even during sub-optimal or adverse circumstances. Over the past fifty years, fault-tolerance has steadily advanced in stride with the permeation of computers into all aspects of society and human welfare.

The study of fault-tolerance as we know it today emerged from the science of information theory (or informatics). In the course of a decade, Claude Shannon (1948), Richard Hamming (1950), Edward F. Moore (1956), and John von Neumann (1956) developed the fundamental principles of error-correction and redundancy. These basic principles were immediately put into practice by the fledgling telecommunications, computing, and avionics industries in pursuit of reliability. William H. Pierce (1965) unified the theories of masking redundancy, and shortly thereafter Algirdas A. Avižienis (1967) integrated these techniques for detection, diagnosis, and recovery into the concept of fault tolerant systems. In 1971, the NASA Jet Propulsion Lab (JPL) and the Institute of Electrical and Electronic Engineers (IEEE) sponsored the first International Symposium on Fault-Tolerant Computing, establishing the IEEE Technical Committee on Fault Tolerant Computing (TCFTC), which continues to be a major forum for discourse and progress. From 1985 to 1992, Jean-Claude Laprie led a

team of members from the International Federation for Information Processing (IFIP) Working Group 10.4 to publish the definitive reference work in the field.

Fault-tolerance has since been most prominently employed in high profile, high-cost areas such as: (i) telecommunications; (ii) defense; (iii) aeronautics; (iv) space exploration; (v) nuclear power; and (vi) financial services. As we become more deeply entangled in the web of our own machineries, the repercussions of their failures grow more profound. That is why, in the nano age, fault-tolerance is becoming exponentially more relevant at all levels as the price of system failure is becoming much greater than that of prevention. As an example, in 1994 Intel had to start the first ever chip recall campaign that cost US$ 475 millions when it was discovered that the Pentium processor generated slightly incorrect results for some floating-point operations. In the future, larger number of devices will be deployed in many applications and embedded systems (tera-scale integration), and reliability could turn out to be a showstopper for economically viable technology scaling: the cost to perform a similar recall—especially in the realm of failure-sensitive and energy-conscious real-time embedded systems—will be exponentially larger. Thus, there is very high pressure to make sure that future nanoelectronic systems will be functioning correctly over their expected lifetime—even if not free of faults and defects!

In this part of the presentation, we will explore the feasibility of designing reliable nano architectures using practical/economical (i.e., small and very small) redundancy factors. In fact we will analyze schemes that require small extra area (and power), and if possible without incurring additional delays. To this end, we go through a thorough review of relevant literature on the design of reliable (fault-tolerant) logic circuitry. We primarily focus on the literature concerning development and analysis of practical redundant design schemes for fault-tolerant nano architectures, but also discuss theoretical studies on optimal redundant design of reliable logic functions. In reviewing the existing literature, we identify needed directions for further study, stressing in particular the importance of considering non-Boolean gates in general (like e.g., threshold logic gates including majority gates in particular, as well as low precision analog gates like e.g., multiple valued logic ones), and for studying practical/economical designs — i.e., those that require only small or very small redundancy factors.

We will then adapt several redundant design strategies—including modular redundancy, von Neumann multiplexing, and reconfigurability—to

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07)0-7695-2831-7/07 $20.00 © 2007

majority-gate circuits, and evaluate the reliability of these designs (i.e., circuits containing both Boolean and non-Boolean gates) for small and very small redundancy factors, using exact combinatorial arguments analytically as well as based on exhaustive counting simulations as needed. Our analysis of von Neumann multiplexing will motivate several extensions that allow optimization of reliability for very small redundancy factors, and highlights the benefits of using non-Boolean gates in nano-scale design, paving the way for novel and practical adaptive fault-tolerant architectures. Simulation results will be presented for 180nm down to 22nm CMOS, as well as for single electron technology (SET).

We shall also assimilate multiple strategies for redundant architectures that mesh several design strategies—including device level ones—to explore feasibility of blending them optimally for lowering the redundancy factors (and hence the overall area and the dissipated power) even more. Using these meshed strategies, we will study the feasibility of achieving chip-level reliability with very small redundancy factors, given estimates of both gate failure probabilities as well as (and much more importantly) of device failure probabilities.

Finally, the redundant designs will be compared with previous studies of redundant architectures. In exploring the feasibility of such enabling redundant designs, we also thoroughly review both the analytical methods (that have been used to characterize reliability of fault-tolerant architectures in general) as well as practical implications and recent advancements in this burgeoning field.

While doing these we shall also review and discuss simulation tools for efficient calculation of reliabilities. This comprehensive tutorial will cover 50 years, and is based on over 250 references.

2. Possible architectural solutions

The possible architectural solutions for the challenges described before can be divided into three categories (with respect to their expected time of implementation):

• Near-term solutions should include massively parallel, modular (cells, blocks); regular (grid processing, cellular arrays); locally connected (near-neighbor connections); higher functionality (multiple valued and threshold logic); reconfigurable.

• Medium-term solutions might include asynchronous (GALS = globally asynchronous locally synchronous); fault-tolerant (noise immune, rad-hard by design, redundant, self-testing, self-correcting); defect-tolerant (reconfigurable); adaptive (self-adaptive, self-organizing, evolvable); bio-inspired (complex functions, self-organizing, self-healing); nanophotonic (optical communication, e.g. GOLE = globally optical locally electrical); nanofluidic (e.g., for cooling); 3D interconnects; stochastic/probabilistic (algorithms, encoding, communication).

• Long-term solutions envisaged are molecular and quantum computing, adiabatic/reversible computing, and biocompatible.

Fig. 3 presents a synthetic view of the four most important challenges identified (as horizontal thrusts), and of some of the plausible architectures, in increasing order of their connectivity complexity from left to right (as vertical pillars). This drawing also suggests that both novel CAD tools, and models will highly be needed.

POWER / HEAT

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Fig. 3. Possible solutions. Logic/encoding (also reconfigurability and asynchronicity) will be considered at all levels.

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07)0-7695-2831-7/07 $20.00 © 2007

4. Conclusions

The building blocks for ICs and for the Brain are the same at nanoscale level: electrons, atoms, and molecules, but their evolutions have been radically different (see Fig. 4). The fact that reliability, low-power, reconfigurability, as well as asynchronicity are brought up so many times in recent conferences and articles, makes it compelling that the Brain could serve as an inspiration at many different architectural levels, suggesting that future nano architectures might be neural inspired (Fig. 5). Personal publications (related to topic) [1] V. Beiu, and U. Rückert (Eds.), Emerging Brain

Inspired Nano Architectures (book accepted for publication in 2005), Singapore: World Scientific Press, in progress, 2007/8.

[2] V. Beiu, and S. Roy, “Review of Redundant Designs for Nano-architectures” in V. Beiu and U. Rückert (Eds.): Emerging Brain Inspired Nano Architectures, Singapore: World Scientific Press, in progress, 2007/8.

[3] V. Beiu, “Limits, Challenges and Issues in Nano-scale and Bio-inspired Computing,” in M.M. Eshaghian-Wilner (Ed.): Bio-inspired and Nano-scale Integrated Computing, Hoboken, NJ, USA: John Wiley & Sons, in progress, 2007.

[4] V. Beiu, and W. Ibrahim, “On Computing Nano-Architectures Using Unreliable Nano-Devices (or On Yield-Energy-Delay Optimal Designs),” in S.E. Lyshevski (Ed.): Handbook of Nano- and Molecular-

Fig. 5. A joint effort on nano architectures.

R E V O L U T I O N

Nano-architectures:

low-power, reliable,

reconfigurable, asynchronous, …

Neuron Column Hypercolumn Area Cortex

100 103 106 109 1012

BRAIN: complex– non-linear – robust– adaptive – redundant– low power – asynchronous

Fan-in103

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ITANIUM (0.13 um CMOS)– 410 M transistors (374 mm2) – 1.5 GHz– 130 W @ 1.3 V

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Nano-architectures:

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reconfigurable, asynchronous, …

Neuron Column Hypercolumn Area Cortex

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BRAIN: complex– non-linear – robust– adaptive – redundant– low power – asynchronous

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ITANIUM (0.13 um CMOS)– 410 M transistors (374 mm2) – 1.5 GHz– 130 W @ 1.3 V

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Fig. 4. Comparing the Bio and the Tech evolutions.

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07)0-7695-2831-7/07 $20.00 © 2007

Electronics, London, UK: Talylor & Francis, in press, 2007.

[5] W. Ibrahim, V. Beiu, and S. Lazarova-Molnar, “Practical Insights into NAND Multiplexing—An Understanding from the Bottom Up,” IEEE Intl. Midwest Symp. Circ. & Sys. MWSCAS’07, Montreal, Canada, Aug. 2007, under review.

[6] V. Beiu, W. Ibrahim, and S. Lazarova-Molnar, “A Fresh Look at Majority Multiplexing—When Devices Get into the Picture,” IEEE Intl. Conf. Nanotech. IEEE-NANO’07, Hong Kong, China, Aug. 2007, under review.

[7] V. Beiu, W. Ibrahim, and S. Lazarova-Molnar, “What von Neumann Did Not Say About Multiplexing: Beyond Gate Failures — The Gory Details,” Intl. Work-Conf. Artif. Neural Networks IWANN’07, San Sebastián, Spain, Jun. 2007, under review.

[8] W. Ibrahim, V. Beiu, and M. H. Sulieman, “On the Reliability of Majority Gates Full Adders,” IEEE Trans. Nanotech., under review.

[9] V. Beiu, W. Ibrahim, Y. A. Alkhawwar, and M. H. Sulieman, “On Practical Multiplexing Issues” (extended version of an IEEE-NANO’06 paper), IEEE Trans. Nanotech., under review.

[10] V. Beiu, “On Brain Inspired Nano Architectures” Invited, Center on Functional Engineered Nano Architectonics (FENA, http://www.fena.org/), Univ. of California, Los Angeles, CA, USA, Apr. 2007.

[11] V. Beiu, “A Brain-inspired Perspective on Nano Communications: Interconnects Tyranny—Brain versus Rent’s Rule” Invited, Annual Nano Materials for Defense Appls., San Diego, CA, USA, Apr. 2007.

[12] W. Ibrahim, V. Beiu, and Y. A. Alkhawwar, “On the Reliability of Four Full Adder Cells,” Proc. IEEE Intl. Design & Test Workshop IDT’06, Dubai, UAE, Nov. 2006, in press.

[13] V. Beiu, W. Ibrahim, Y. A. Alkhawwar, and M. H. Sulieman, “Gate Failures Effectively Shape Multiplexing,” Proc. IEEE Intl. Symp. Defect & Fault Tolerance in VLSI Sys. DFT’06, Washington, DC, USA, Oct. 2006, pp. 29–37.

[14] V. Beiu, and M. H. Sulieman, “On Practical Multiplexing Issues” Proc. IEEE Intl. Conf. Nanotech. IEEE-NANO’06, Cincinatti, Ohio, USA, Jul. 2006, pp. 310–313.

[15] V. Beiu, “What Do Moore, von Neumann, and Kolmogorov Have in Common,” Invited Plenary Talk at ACS/IEEE Intl. Conf. Comp. Sys. & Appls. AICCSA’06, Sharjah, UAE, Mar. 2006.

[16] M. H. Sulieman, and V. Beiu, “Multiplexing Schemes for Single Electron Technology,” Proc. ACS/IEEE Intl. Conf. Comp. Sys. & Apps. AICCSA’06, Sharjah, UAE, Mar. 2006, pp. 424–428.

[17] V. Beiu, “The Quest for Reliable Nano Computations,” Invited Plenary Talk at IEEE Intl. Conf. Microelectr. ICM’06, Islamabad, Pakistan, Dec. 2005 (p. xix).

[18] M. H. Sulieman, and V. Beiu, “On Single-Electron Technology Full Adders,” IEEE Trans. Nanotech., vol. 4, no. 6, Nov. 2005, pp. 669–680.

[19] V. Beiu, “On Brain Inspired Nano Architectures (or There Are Plenty of Opportunities at the Top)” Invited Seminar, School of Computing and Intelligent Systems, University of Ulster, Londonderry, UK, Nov. 2005.

[20] V. Beiu, “Great Challenges of Nanoelectronics (or There Are Plenty of Challenges at the Bottom)” Invited Seminar, School of Computing and Intelligent Systems, University of Ulster, Londonderry, UK, Nov. 2005.

[21] S. Aunet, Y. Berg, and V. Beiu, “Ultra Low-Power Redundant Logic Based on Majority-3 Gates,” Proc. IFIP Intl. Conf. VLSI Sys.-on-Chip VLSI-SoC’05, Perth, Australia, Oct. 2005, pp. 553–558.

[22] V. Beiu, J. Nyathi, and S. Aunet, “Sub Pico Joule Switching: High-Speed Reliable CMOS Switching Are Feasible,” Intl. Conf. Innovations in Info. Tech. IIT’05, Dubai, UAE, Sep. 2005. www.it-innovations.ae/iit005/ proceedings/articles/E_5_IIT05_Beiu.pdf

[23] V. Beiu, and A. Zawadzki, “On Kolmogorov's Superpositions: Novel Gates and Circuits for Nanoelectronics?,” Proc. IEEE Intl. Joint Conf. Neural Networks IJCNN’05, Montreal, Canada, Aug. 2005, pp. 651–656.

[24] S. Aunet, and V. Beiu, “Ultra Low Power Fault Tolerant Neural Inspired CMOS Logic,” Proc. IEEE Intl. Joint Conf. Neural Networks IJCNN’05, Montreal, Canada, Aug. 2005, pp. 2843–2848.

[25] S. Roy, and V. Beiu, “Majority Multiplexing—Economical Redundant Fault-Tolerant Designs for Nanoarchitectures,” IEEE Trans. Nanotech., vol. 4, no. 4, Jul. 2005, pp. 441–451.

[26] V. Beiu, S. Aunet, J. Nyathi, R. R. Rydberg III, and A. Djupdal, “On the Advantages of Serial Architectures for Low-Power Reliable Computations,” Proc. IEEE Intl. Conf. App.-specific Sys., Arch. & Processors ASAP’05, Samos, Greece, Jul. 2005, pp. 276–281.

[27] V. Beiu, A. Djupdal, and S. Aunet, “Ultra Low Power Neural Inspired Addition—When Serial Might Outperform Parallel Architectures,” Intl. Work-conf. Artif. Neural Networks IWANN’05, Barcelona, Spain, Jun. 2005, pp. 486–493.

[28] V. Beiu, A. Zawadzki, R. Andonie, and S. Aunet, “Using Kolmogorov Inspired Gates for Low Power Nanoelectronics,” Intl. Work-conf. Artif. Neural Networks IWANN’05, Barcelona, Spain, Jun. 2005, pp. 438–445.

[29] V. Beiu, S. Aunet, R. R. Rydberg III, A. Djupdal, and J. Nyathi, “The Vanishing Majority Gate: Trading Power and Speed for Reliability,” Proc. IEEE Intl. Work. Design & Test of Defect-Tolerant Nanoscale Arch. NanoArch’05, Palm Springs, CA, USA, May 2005. http://www.eecs.wsu.edu/~vbeiu/Publications/2005%20NanoArch.pdf

[30] V. Beiu, “A Novel Highly Reliable Low-Power Nano Architecture: When von Neumann Augments Kolmogorov,” Proc. IEEE Intl. Conf. App.-specific Sys., Arch. & Processors ASAP’04, Galveston, TX, USA, Sep. 2004, 167–177.

[31] V. Beiu, U. Rückert, S. Roy, and J. Nyathi, “On Nanoelectronic Architectural Challenges and

Proceedings of the 37th International Symposium on Multiple-Valued Logic (ISMVL'07)0-7695-2831-7/07 $20.00 © 2007

Solutions,” Proc. IEEE Intl. Conf. Nanotech. IEEE-NANO’04, Munich, Germany, Aug. 2004, pp. 628–631.

[32] M. H. Sulieman, and V. Beiu, “Design and Analysis of Single Electron Technology Circuits: Using MATLAB Modules and SIMON,” Proc. IEEE Intl. Conf. Nanotech. IEEE-NANO’04, Munich, Germany, Aug. 2004, pp. 618–621.

[33] S. Roy, and V. Beiu, “Multiplexing Schemes for Cost-Effective Fault-Tolerance,” Proc. IEEE Intl. Conf. Nanotech. IEEE-NANO’04, Munich, Germany, Aug. 2004, pp. 589–592.

[34] M. H. Sulieman, and V. Beiu, “On Single Electron Technology Full Adders,” Proc. IEEE Intl. Conf. Nanotech. IEEE-NANO’04, Munich, Germany, Aug. 2004, pp. 317–320.

[35] M. H. Sulieman, and V. Beiu, “Characterization of a 16-bit Threshold Logic Single Electron Technology Adder,” Proc. IEEE Intl. Symp. Circ. & Sys. ISCAS’04, Vancouver, Canada, May 2004, pp. 681–684.

[36] V. Beiu, J. Quintana, M. Avedillo, and M.H. Sulieman, “Threshold Logic—From Vacuum Tubes to Nanoelectronics” Invited, Proc. IEEE Intl. Midwest Symp. Circ. & Sys. MWSCAS’03, Cairo, Egypt, Dec. 2003, pp. 930–935.

[37] M.H. Sulieman, and V. Beiu, “Review of Recent Full Adders Implemented in Single Electron Technology” Invited, Proc. IEEE Intl. Midwest Symp. Circ. & Sys. MWSCAS’03, Cairo, Egypt, Dec. 2003, pp. 872–875.

[38] V. Beiu, “Neural inspired architectures for nanoelectronics: Highly reliable, ultra low-power, reconfigurable, asynchronous” Special Session, Neural Info. Proc. Sys. NIPS’03, Whistler, Canada, Dec. 2003. http://www.eecs.wsu.edu/~vbeiu/workshop_nips03/

[39] V. Beiu, J.M. Quintana, and M.J. Avedillo, “Threshold Gates: Past, Present, and Future” Special Session, Intl. Work-Conf. Artif. Neural Networks IWANN’03, Maó, Menorca, Spain, Jun. 2003.

[40] V. Beiu, “Noise Tolerant Conductance-Based Logic Gate and Methods of Operation and Manufacturing,” US Patent 6,430,585, Aug. 6, 2002.

[41] V. Beiu, “High-Speed Noise Robust Threshold Gates” Best Paper Award, Proc. IEEE Annual Conf. Semicon. CAS’00, Sinaia, Romania, Oct. 2000, pp. 79–82.

[42] V. Beiu, “Ultra-Fast Noise Immune CMOS Threshold Gates,” Proc. IEEE Intl. Midwest Symp. Circ. & Sys. MWSCAS’00, Lansing, USA, Aug. 2000, pp. 1310–1313.

[43] V. Beiu, and C. Constantinescu, “Fault-Tolerant Systolic Arrays for Antialiasing,” Proc. IEEE CompEuro’87, Hamburg, Germany, May 1987, pp. 720–723.

[44] V. Beiu, “Self-Testable and Self-Repairable Antialiasing Unit,” Proc. MicroElectronics’86, Plovdiv, Bulgaria, Oct. 1986, pp. 183–195.

[45] I. Manole (supervisor V. Beiu), “Self-Testable and Self-Repairable Correlation Circuit,” MSc Dissertation, CE Dept., “Politechnica” Univ. Bucharest, Bucharest, Romania, May 1985.

[46] C. Borş (supervisor V. Beiu), “Self-Testable RAM/CAM Memory,” MSc Dissertation, CE Dept., “Politechnica” Univ. Bucharest, Bucharest, Romania, May 1985.

[47] V. Beiu, “Self-Testable and Self-Repairable Units: A Must for VLSI Structures,” Proc. Annual Conf. CNETAC’84, Bucharest, Romania, Nov. 1984 (in Romanian).

[48] V. Beiu, “VLSI Implementation of Self-Testable Real Content Addressable Memory,” Proc. IEEE Intl. Conf. Control Sys. & Comp. Sci. CSCS’84, Bucharest, Romania, May 1984, pp. 400–405.

[49] V. Beiu, “High Reliability Memory Organization,” Proc. Annual Conf. CNETAC’83, Bucharest, Romania, Nov. 1983 (in Romanian).

[50] V. Beiu, “Reliability Enhanced Memory Architectures with Gracefully Degrading Performances” Invited, “Traian Vuia” College of Informatics, Bucharest, Romania, May 1981 (in Romanian).

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