Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM

Bing-Chuan Bai1,2, Kun-Lun Luo1, Chen-An Chen1, Yee-Wen Chen1, Ming-Hsueh Wu1, Chun-Lung Hsu1,

and Liang-Chia Cheng1

1Information and Communications Research Lab. Industrial Technology Research Institute (ICL, ITRI)

Chutung, Hsinchu 31040, Taiwan, R.O.C. e-mail: {bcbai, kunlun, chenanchen, windychen, shair, clh,

aga}@itri.org.tw

James C.-M. Li2

2Laboratory of Dependable Systems Graduate Institute of Electronics Engineering

National Taiwan University (LaDS, GIEE, NTU) Taipei 10617, Taiwan, R.O.C. e-mail: cmli@cc.ee.ntu.edu.tw

Abstract Rnv8T nonvolatile SRAM combines conventional SRAM and resistive RAM to provide both fast access speed and data retention. Traditional test methods for conventional SRAM or resistive RAM are not suitable for nonvolatile SRAM. This paper analyzes the defective behavior of the Rnv8T nonvolatile SRAM based on defect injection and simulation. Simulation results showed that the inject defects caused stuck-at faults and transition faults which escaped from conventional March tests. Based-on the defective behavior and circuit operations, a straight forward test algorithm is proposed to detect the escaped faults.

Keywords-nonvolatile SRAM; resistive RAM; memristor; Rnv8T; defect analysis;

I. INTRODUCTION

For normally-off, instant-on applications, the standby energy consumption seriously reduces the battery life even when the static power is small [1][2]. Nonvolatile memory (NVM) has made zero standby power possible, but it does not provide as fast access speed as SRAM. Besides, the life cycle of the nonvolatile memory is very limited. Traditionally, a serial link is constructed between SRAM and NVM. The contents of SRAM are transferred to NVM before the power is switched off.

Nonvolatile SRAM (nvSRAM) provides fast access speed as well as its nonvolatile nature by building parallel (bit-to-bit) connections between SRAM and NVM [3 9]. The parallel connections speed up the transfer rate between SRAM and NVM, and reduce the sleep time and wakeup time. RRAM (or memristor [10][11]) is a promising candidate for next generation nonvolatile memory due to its simple metal-oxide structure and potential for device scaling [12 19]. Rnv8T is a RRAM-based nvSRAM that integrates eight transistors and two vertical-stacked memristor devices (8T2M) within a single nvSRAM cell [20]. Rnv8T has shown several advantages over other nvSRAM designs, such

as small cell area, fast write speed, higher cell stability, and lower minimum supply voltage during the normal operations.

Many papers about NVM testing were published, but only few of them were related to RRAM testing. To detect the hard-to-detect undefined state of a RRAM cell between the logic 1 and 0 states, a defect oriented testing method based on reducing supply voltage and reducing write time was presented [21][22]. A divide-and-conquer testing technique based on current measurement was proposed to test memristor based lookup table [23]. Another current-based parallel testing technique, that is called sneak-path testing, was proposed to speed up RRAM testing [24][25]. However, distinguishing the intrinsic leakage current in advanced process technology from the defect induced current is very difficult. Moreover, these papers did not discuss about testing nvSRAM, and the mentioned techniques were not even suitable for testing RRAM-based nvSRAM.

This paper is the first one discussing about testing RRAM-based nvSRAM, especially for the Rnv8T nvSRAM. This research started with building fault models by analyzing the defect behavior. For the Rnv8T nvSRAM, the memristor devices were fabricated using the back-end-of-line (BEOL) process. Only possible defects injected during the BEOL process were considered in this research, while the other parts of fabricated circuits were assumed defect-free. For example, a defect can represent a defective via connecting the memristor, or a short defect bypassing the memristor. The simulation results showed that the defects may cause stuck-at faults and transition faults when the memory contents were transferred between the SRAM and RRAM. Conventional March tests did not cover the test patterns detecting the nvSRAM specific faults. Based on the simulation results, a March-like test was proposed for testing Rnv8T nvSRAM and other nvSRAM having similar structure. The test algorithm can be easily integrated into the SRAM BIST methods with careful chip power

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2013 22nd Asian Test Symposium

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DOI 10.1109/ATS.2013.32

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management. The remainder of this paper is organized as follows.

Section II gives the background of memristor and the RRAM-based nvSRAM Rnv8T. Section III consists of the qualitative defect analysis, and proposes a March-like test algorithm. The simulation results are shown in Section IV, which reveals the defect-caused stuck-at faults and transition faults. Before the end of this paper, the conclusion is contained in Section V.

II. BACKGROUND

A. Memristor Fundamentals

Memristor is known as the fourth fundamental element that connects the link between flux ( ) and charge (q) [10][11]. A memristor acts like a resistor but the resistance depends on its accumulated charge. The characteristics of a memristor can be described as follow: = ( ) (1) = ( ) , (2) where M denotes the resistance of the memristor, v is the cross voltage, and i denotes the current flowing through the memristor. Based on the phenomenon, the memristor was modeled as two resistors connected in series as shown in Figure 1. Considering a memristor of thickness D, the memristor consisted of a doped resistor of thickness w, and an undoped resistor of thickness D-w. The doped region has low resistance, while the undoped region has high resistance. The application of an external bias voltage caused the dopants to drift, and thus changed the position of the boundary between the two regions. When the memristor was completely doped, the resistance was Ron. When it was completely undoped, the resistance became Roff. The resistance of the memristor is shown as below: ( ) = + 1 (3) = , : . (4)

Figure 1 Memristor modeled as coupled resistors

Since memristor model was not a built-in element in the SPICE engines, several macro models based on its characteristics were proposed for circuit simulations. Figure 2 shows the structure of a memristor SPICE model proposed in [26][27]. The model consists of two dependent parts. The left part consists of a voltage-controlled voltage source (Emem) and a serially connected resistor (Roff). The right part is a current-controlled current source (IX) connected in series to a capacitance (CX). The capacitance

can be charged or discharged without any constraints in this model, but the resistance of a fabricated memristor is limited in real world. A proposed window function f solved the issue, which is called the boundary effects, of this model. A clipping circuit was proposed to replace the window function [28], but the circuit was complicated and it slowed down the simulation speed. To speed up the simulation speed, simple diode connections were used to limit the charge of the capacitance [29][30].

Figure 2 Structure of the memristor SPICE Model [26]

B. Rnv8T Cell

The schematic of the Rnv8T cell is shown in Figure 3. Rnv8T provides as fast write/read speed as conventional SRAM. The element for normal SRAM operations is the conventional 6T-SRAM, which consists a pair of feedback inverters and two gating transistors (PGL and PGR). The nonvolatile nature of Rnv8T is provided by the memristor devices. The memristor device ML(MR) connects the Q(QB) to BL(BLB) through another gating transistor RSWL(RSWR). Before switching off the power, the memory content is stored into the two memristors by a combination of SET and RESET operations. When switching on the power, the RESTORE operation is executed and the memory content is transferred back to the 6T-SRAM. The details of the operations are described later.

Figure 3 Cell schematic of Rnv8T

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The operations and the corresponding signal states of Rnv8T are listed in Table 1. During the IDLE operation, the WL and SWL signals are fixed to VSS. During the WRITE or READ states, the WL and SWL signals are fixed to VDD, and the four gating transistors (PGL, PGR, RSWL, RSWR) are switched on. The STORE operation consists of two stages SET and RESET. In both of the two stages, WL is fixed to VSS and SWL is fixed to VDD, respectively. In the SET stage, BL and BLB are tied to VSS. The current flows through the memristor ML(MR) from Q(QB) to BL(BLB) if Q(QB) is at logic one (high). In the RESET stage, BL and BLB are tied to VDD. The current flows through the memristor MR(ML) from BLB(BL) to QB(Q) if QB(Q) is at logic zero (low). The flowing current changes the resistance of the memristors. When the current flows from Q(QB) to BL(BLB), it increases the resistance. When the current flows in the opposite direction, it reduces the resistance. When no current flows through the memristor, the resistance is retained and the power can be completely turned off. When the power is turned on, the RESTORE operation is executed. The WL and SWL signals are tied to VSS and VDD, respectively. The BL and BLB wires are tied to VSS. When the power is gradually turned on, the Q and QB nodes are charged in different speed according to the resistance of ML and MR. The feedback latches rapidly lock Q and QB to stable logic states, either 0/1 or 1/0. The Q node restores to logic one if the resistance of ML is larger than MR. Otherwise, the Q node restores to logic zero.

Table 1 Rnv8T operations

Operations Signal States IDLE WL=VSS, SWL=VSS

WRITE, READ WL=VDD, SWL=VDD STORE(SET) WL=VSS, SWL=VDD, BL=BLB=VSS

STORE(RESET) WL=VSS, SWL=VDD, BL=BLB=VDD RESTORE WL=VSS, SWL=VDD, BL=BLB=VSS

III. DEFECT ANALYSIS AND FAULT MODELING

SPICE simulations were performed to classify the defective behavior corresponding to the injected defects. To focus on the defects possibly induced during the BEOL process, the 6T-SRAM was assumed fault-free. In practice, pre-testing of the 6T-SRAM could guarantee that only known good dies were used in the BEOL process. Figure 4 shows the circuit structure of the Rnv8T cell with possible defect locations on the vertical-stacked devices. The resistive-open defects (R1o, R2o, R3o and R4o) represented the via voids and the resistive opens of the top-level metal wire. The resistive-short defects (R1s and R2s) represented faulty memristors having direct leakage current flowing through them. A faulty memristor could be defectively manufactured or be destroyed during the forming process [31]. The bridging defect (Rb) represented the resistive short between the top-level metal wires.

Figure 4 Rnv8T cell with injected possible defects

When the resistance of the resistive-open defects (R1o, R2o, R3o and R4o) was small, it slowed down the switching speed of the memristor states during the store operation, i.e. switching from high-resistance state (Roff) to low-resistance state (Ron), or vice versa. When the resistance of the open defect was large, it caused a stuck-at fault in the STORE and RESTORE states. For example, the condition (5) caused a stuck-at-one fault, and condition (6) caused a stuck-at-zero fault. + + ( ) > ( ) (5) + + ( ) > ( ) (6)

The resistive-short defects (R1s and R2s) also slowed down the state switching of the memristor. The current that meant to flow through the memristor was divided by the resistive-short defect connected in parallel with the memristor. When the resistance of the short defect was small, it also caused a stuck-at fault. For example, the condition (7) caused a stuck-at-zero fault, and the condition (8) caused a stuck-at-one fault. || ( ) < ( ) (7) || ( ) < ( ) (8)

The stuck-at and delay faults caused by the BEOL defects were activated by STORE and observed after RESTORE. To cover the functional faults of the 6T-SRAM and the BEOL-defect-cased faults, a March-like test algorithm for testing the RRAM-based nvSRAM was proposed as below: ( 0); ( 0); ( 1); ( 1) ;( 0, 0); ( 0); ( 0, 1);( ); ( 0); ( 0);( 1, 1); ( 1); ( 1, 0);( ); ( 1); ( 1); . (9)

The notations is similar to conventional March test, except:

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(a) the STORE and RESTORE operations denoted as store and restore, and (b) the power-off and power-on sequences denoted as PX. The test algorithm begins with a self-forming sequence consisted of N times of write-and-store sequences without reading the memory contents. The self-forming sequence fixed the over-forming problems and brought the resistance of the memristors into working region [31]. After the self-forming sequence, the leading WRITE and READ operations detected the functional faults of the 6T-SRAM, and initialized the value before the STORE operation. The READ operation following the STORE operation was executed in order to examine the memory content not being altered by STORE. An opposite value was set by WRITE in order to set the initial value before PX and RESTORE. If PX or RESTORE had not executed successfully, the faulty value was observed by the following READ operation.

The bridging defect (Rb) might cause functional faults to WRITE or READ operations, but it was fault-free during STORE and RESTORE operations. The proposed test algorithm or conventional march tests could not detect the bridging defects. However, the bridging defects caused quiescent current flowing from Q(QB) to QB(Q) through the memristors. The quiescent current may decrease the endurance of the memristor devices. IDDQ tests may increase the defect coverage to ease the problem.

IV. EXPERIMENTS

The memristor model for SPICE simulation in this paper is shown in Figure 5. The clipping function was implemented using two independent voltage sources connected with diodes. The resistance of Roff was 100K , and Ron was 10K . The high-to-low (from Roff to Ron) transition time was about 17ns, and the low-to-high (from Ron to Roff) transition time was about 7ns. Based on the transition time, the SET duration was 19ns, and the RESET duration was 8ns. In order to separate transition fault effects from stuck-at faults, the SET and RESET durations were doubled (38ns and 16ns) to catch the slow-to-rise and slow-to-fall transition faults. These transition faults could be soft-repaired easily by programming the SET and RESET durations in the nvSRAM controller.

Figure 5 Memristor Model with Clipping Diodes

Single defect injection was assumed during the

simulation, and the results were listed in Table 2. To simplify, R1o and R2o were considered as one single defect because they were equivalent in increasing the series connected resistance. Similarly, R3o and R4o were considered as one single defect. For the resistive-open defects, when the resistance was equal or larger than 90K , the Rnv8T cell had a stuck-at fault. It was consistent with the theoretical calculation. If the defect was located at the Q side, it caused a stuck-at-one fault. If the defect was located at the QB ride, it caused a stuck-at-zero fault. If the resistance ranges between 49K and 90K , the defect caused transition faults. That is, good value was observed when the SET and RESET durations were doubled, while faulty value was observed when the durations were not. If the resistance is smaller than 49K , no faults were caught.

Table 2 Injected defects and the corresponding faults

Defects Faults (R1o+R2o) 90K , R2s 18K Stuck-at 1 (R3o+R4o) 90K , R1s 18K Stuck-at 0

90K > (R1o+R2o) 49K Slow-to-Fall 90K > (R3o+R4o) 49K Slow-to-Rise

0 Rb Fault-free, IDDQ

For the resistive-short defects, no transition faults but only stuck-at faults were observed. Although the resistive-short defects slowed down the transition of the memristors, the stuck-at faults appeared before the increased transition time formed a transition fault. The results showed that when the short resistance was larger than 18K , it caused no faults. The observed boundary condition of the resistance (18K ) was larger than the theoretical condition (11K ) obtained from (7) or (8). It was because the transition time was extremely long when the resistance ranges between 11K and 18K , and the transition fault was considered as a stuck-at fault. When the resistive-short resistance located at the Q(QB) side was equal of smaller than 18K , it caused a stuck-at-zero(stuck-at-one) fault. The bridging defect Rb, caused no stuck-at or transition faults, but it induced quiescent current between Q and QB. When the resistance of the injected defect became smaller, the quiescent current became getting larger. The quiescent current may decrease endurance of the memristor, and it still needs more research effort.

V. CONCLUSION

This paper analyzes the possible defect location and defective behavior of the RRAM-based nvSRAM (Rnv8T) injected during the BEOL process. The defect types included the resistive-open defects connected in serial, the resistive-short defects connected in parallel, and the resistive-bridge defect connecting the two memristors. The defects caused stuck-at faults, transition faults, and IDDQ problem. The faults escape from conventional March tests

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because the fault effects appeard only after restoring from power-off state. A straight forward test algorithm is proposed to detect the faults caused by the mentioned defects. This study has started the study of testing the RRAM-based nvSRAM. Further research in increasing the defect coverage is needed to improve the production yield and endurance.

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