Distribution A – Approved for public release: distribution is unlimited. Ref# 12-07-03_SMXG_046.

A New Class of Test Instrument The FPGA Based Module

Patrick B. Kelly 309th Software Maintenance Wing,

516th Software Maintenance Squadron Hill Air Force Base, Utah

Abstract— Testing involves applying stimulus to a device, called the Unit Under Test (UUT), and evaluating the measured response against the expected values. Traditional systems use discrete instruments to supply the stimulus and measure the response, but most devices are part of a larger system and may be a component of a closed control loop. Many devices are designed to respond to the inputs by generating outputs that are dependent on some part of the output being fed back to the inputs through the rest of the system. To be comprehensive, a test of such a device must include stimulus and response that matches, as closely as possible, the way the device is used in the full system. This requires test equipment that can alter the stimulus in response to the UUT’s outputs. For low speed systems, software can often accomplish this, which is the traditional approach, but systems that require much faster response than practically accomplished in software are simply not tested in this fashion unless custom test hardware is designed to do it. This drives up the cost of test station and test program design, development, and maintenance, making it prohibitive except where crucial. Recent advancements in Field Programmable Gate Array (FPGA) technology have made a new class of instrument available to the test market. Modules based on standard interfaces that provide a large FPGA with external memory, multiple ADC and DAC channels with the digital side interfaced to the FPGA, and a large number of digital I/O pins plus programming interfaces that are fairly easy to use are now available at low cost. These modules can replace custom electronics that were required to achieve satisfactory test results in “Hardware in the Loop” test scenarios at very low acquisition and development cost. FPGA based test instruments allow rapid development of complex control systems without custom hardware development. The future impact of such implementations will be reduced station and test program maintenance cost and problems since the “custom hardware” is contained in the test program and the hardware it runs on is a commercially available standard part number.

Index Terms—FPGA, ATE, Digital Test, Hardware, Mixed Signal, Programmable Hardware, Timing, Control.

I. INTRODUCTION Over the years of developing digital tests, I have struggled

with a primary test philosophy: test the circuit in the way it is used in the system. The reason this has been a struggle is that traditional digital test instrumentation does not allow increasingly complex digital circuitry to be tested as it is used

by the system of which it is a part. This forces the test engineer to use special roll-up test equipment, which for high speed digital is expensive, makes signal integrity difficult to maintain in the connections to the Unit Under Test (UUT), and creates a situation requiring either acceptance of inadequate testing or the designing of custom hardware with the associated expense and long term maintenance challenges. In this paper I will identify some of the fundamental problems with traditional digital test equipment and propose a solution that is cost effective and gives capabilities that previously required custom hardware design to realize.

II. CHALLENGES WITH TRADITIONAL DIGITAL TEST Traditional Digital Word Generators (DWGs) are good at

presenting a preprogrammed pattern to the UUT and recording the responses. There are some that can exceed 50MHz data rates, but most are in the 20 to 25MHz range. This accommodates most of the systems designed in the 70's and 80's, but is totally inadequate for many of the upgrades and newer systems we must now test. One challenge is that very few, if any, DWGs allow external signals to control the behavior of the timing set programmed into them. It can be very difficult to implement a function such as a graceful safety shut down based on either the data being returned or another input. These usually must be implemented in software, but since the host computer is typically a Windows based system, there is a very large uncertainty as to when the shutdown will take effect. Another challenge is that many systems require constant bus and/or timing activity and DWGs typically do not allow data to be altered or responses to be read while the instrument is active, leading to interruptions in the data flow and timing signals. Most UUTs that have requirements for constant clocks and message traffic will not function properly with interruptions caused by test system access, therefore, an alternative to the DWG must be designed. Until recently such alternatives had to be designed in custom hardware and were expensive in terms of time, funds and maintenance. Additionally, DWGs cannot effectively act as a bus interface with the host test computer due to the nature of pattern programming and response recording. This setup and read is essentially a static operation while a bus interface needs to be dynamic. Many newer systems, both upgrades and new weapons systems, use an industry standard bus, such as the compact Peripheral Component Interconnect (PCI) bus, as the main interface to the UUT. These buses require setup sequences that read data from the card and return configuration

978-1-4673-0700-0/12/$31.00 ©2012 IEEE

information based on that data which controls how the card is addressed and functions. Current test stations don't provide such an interface and the dynamic nature of the bus rules out the use of a standard DWG.

III. THE SOLUTION The solution to these challenges is the Field Programmable

Gate Array or FPGA. Wait! I know these devices have been around for decades and they are notorious for being tricky to design into a board as well as tough to program, but in the past few years several vendors have been developing boards that provide one or more FPGA chips as user programmable devices, complete with dynamic data interchange channels to the host computer. Some of these are designed for the PC computer market to provide massive parallel data processing capability, but there are some that are specifically designed as test instruments for standard test buses like PCI eXtensions for Instrumentation (PXI) and PXIe (express) and there are carrier boards available to host these in the VME eXtensions for Instrumentation (VXI) bus as well so test stations that do not have a PXI chassis can still be upgraded to allow true flexible high speed digital testing. FPGA boards and the VXI to PXI carrier boards include driver layer and Application Program Interface (API) software that make developing the host communication links very easy. Program development for the FPGA has also made major strides, with software tools developed by the FPGA chip vendors that do a very good job of optimizing resource usage and timing inside the chips as well as offering schematic input for the logic, which eliminates the challenge of learning a hardware description language. Most chip vendors offer very capable tools at no charge, with options for more powerful software available for purchase. Also, there is an ever increasing library of Intellectual Property (IP) functions that can be dropped into a design, providing verified complex functions without development time and minimal integration time. Some test instrument vendors have even integrated their FPGA boards and program development tightly into their test environments, making the use of their boards virtually seamless. How does the FPGA board revolutionize the digital test industry? Let’s say you have a unit to test that requires two data paths plus several timing signals, one data path is totally asynchronous to all the timing signals and the other bus and has a data clock that also provides general timing for the unit and must not be interrupted (Fig. 1). Traffic must be maintained on this bus with several different words passing in both directions every five milliseconds. One of the data words must be written with every burst but the value

must occasionally change shortly after certain events on the timing signals. Another data path is only active when the timing signals are in a specific state and the data rate is unrelated to other clocks while the data must be dynamic. This scenario would require a complex state machine not possible to implement in a DWG and, in the past has been implemented in custom logic, but it is quite easy to implement in an FPGA since the data paths to the host are dynamic and state machines are natural to the logic environment of the FPGA. What’s more, it is simple to include control signals for other instruments, such as triggers or pulse modulation signals that synchronize the entire test station and allow easy tuning for aligning signal arrival through the various path lengths so the UUT has all its timing satisfied. One can even include safety subsystems that will allow graceful shutdown on various faults, all without concern of timing or response delays from a Windows based operating system. FPGAs are inherently massively parallel in nature so many independent processes can be programmed to run simultaneously, including small embedded microcontrollers, and can interchange data on the fly to coordinate all these processes. Some of the most complex programming, such as bus interfaces like PCI or embedded microcontrollers, can be implemented by inserting a preprogrammed piece of IP - many of which are available without charge. All this development is done in a software-like environment that results in hardware-like response and timing. Integrating and debugging the design is very much like software development and testing - no hardware modifications to implement or circuit boards to lay out. FPGA boards can emulate standard DWGs as well. Some vendors have provided programmable pin electronics that behave like some of the most sophisticated DWGs, but if the board selected does not have this level of output control, drivers appropriate for each UUT can be included in the test adapter. The FPGA hasinternal memory, both block and logic based, and the boards typically have additional memory that can be accessed by the logic in the FPGA and sometimes by the host computer as well. These resources can be programmed to provide the same capability as a DWG. This memory coupled with the dynamic host interface and the powerful logic capabilities of the FPGA make these boards an excellent platform for bus emulation. Anything from standard buses, like the PCI bus, to specialty buses, like 1553, to proprietary buses used inside systems can be linked to the host computer to control the UUT. The only thing that may be required in the test adapter is a buffer card to provide the proper logic levels and conditioning. With an FPGA instrument as part of the test station, special bus

Fig. 1

emulation hardware or other roll-up digital test instrumentation is not needed.

IV. FPGA INSTRUMENT CAPABILITIES Data rates for FPGA boards vary widely, some have very

robust pin drivers that can tolerate applied voltages up to +/- 20 volts, but sacrifice speed, while others handle more typical voltages like +7 to -0.5 and provide data rates as high as 700MHz with the possibility of a few channels of serial data with rates significantly higher. With some care in designing station wiring, patch panel, and test adapter layout, data rates well above 200MHz to the UUT can easily be achieved. With pin counts as high as 160 pins per card and the ability to combine multiple cards, very complex digital testing at high speed is practical. Another option available on some boards is analog Input/Output (IO) coupled to the FPGA. I have used such a board, fully integrated into the test stand, for digital control, logic signal monitoring and reporting, safety shutdown, and simultaneously simulated a high voltage power supply to test a regulator system without having the supply in the circuit. The control voltage was digitized by the FPGA board analog input and the feedback voltage divider voltages were generated by the FPGA based on the value of the control voltage then sent out to the Digital to Analog Converters on the FPGA board. These outputs were then routed to the feedback inputs of the regulator system. The result was the ability to test the regulator in a closed loop mode without having the high voltage section generating dangerous voltages or needing the high input power required by the high voltage section. This application is called “hardware in the loop” simulation and is easily accomplished in this kind of hardware since no real hardware design and implementation is required (Fig. 2). Changes to the response requirements are handled with software-like programming changes, greatly reducing maintenance costs and increasing system value. I have also implemented a safety system that prevents operator exposure to

high power RF leakage by using an antenna and detector to pick up the RF level which is then routed to one of the analog inputs of the FPGA board. The digitized value is compared to a host programmable threshold in the FPGA and if the threshold is exceeded, the excitation to the UUT is turned off, eliminating the hazard. The operator is then informed of the leakage so corrective action can be taken. The response time is in the microseconds, so exposure is very limited and no harm to personnel can occur. All these capabilities are available in a board that costs between $2,000 and $7,000 depending on desired features and FPGA size.

V. CONCLUSION The new capabilities offered by commercial FPGA based

test instruments are so extensive that they can truly be called revolutionary. The ability to integrate multiple functions and bus interfaces into the same device and have them interact in any desired way or be totally independent of each other eliminates most test challenges commonly faced in testing modern systems. The ease that these instruments can be integrated into existing test stations, particularly standard stations like the Versatile Depot Automatic Test System (VDATS), Consolidated Automatic Support System (CASS), and Next Generation Automatic Test System (NGATS), eliminates a primary test station obsolescence issue and expands station capability with very little hardware expense. 320 very high speed IO pins can be installed for less than the price of one digital test module of the most commonly used type whose design is over 20 years old. Complex timing and data handling challenges can now be implemented in a software-like environment, allowing easy maintenance and improvement of the test throughout the life of the UUT. All of these factors combine to greatly reduce the cost of effective test for modern systems.

Fig. 2