Sensitive high frequency envelope detectors based on triple barrier resonant tunneling diodes

Gregor Keller, Anselme Tchegho, Benjamin Münstermann, Werner Prost, and Franz-Josef Tegude. Solid-State Electronics Department, Center for Nanointegration, University of Duisburg Essen,

Lotharstr. 55, D-47057 Duisburg, Germany

Abstract — InP-based resonant tunneling diodes with symmetrical I/V-characteristics have shown their excellent high frequency performance for THz signal generation. We present a modification with an additional third barrier to create an unsymmetrical I/V-characteristic. With their large current densities and low capacitances these devices are promising candidates for zero bias high frequency envelope detectors. Based on simulations two layer stacks are grown by MBE technology. The fabricated devices were measured at dc- and high frequencies. First measurement results for the short circuit responsivity are discussed.

Index Terms — Indium phosphide, Rectifiers, Resonant tunneling devices, Triple barrier RTD

I. INTRODUCTION

RF-Signal detectors have been important devices since the early days of radio technology. These devices require strong asymmetry to allow efficient rectification. Resonant tunneling diodes (RTD) have demonstrated their excellent high frequency performance in THz signal generation [1]. The latest improvements are mainly driven by an increase of current density up to 1000 kA/cm2 [2]. Based on our RTDs with current densities up to 500 kA/cm2, the approach of resonant tunneling diodes with 3 Barriers is investigated [3, 4, 5]. By design of the epitaxial layer structure of the second well and the third barrier, an asymmetry in layer structure leads to an asymmetric current-voltage characteristic.

II. OPTIMIZATION OF THE DEVICES

Fig. 1. Reverse and forward current characteristic

The typical conduction band configuration for a triple barrier resonant tunneling diode (TBRTD) is presented in figure 1. Here the asymmetry is created by a thicker second quantum well, leading to a lower discrete energy level compared to the first one. In reverse direction this difference causes a blocking effect. For larger applied voltages the parasitic thermionic current dominates the characteristic. In forward direction the resonant tunneling through the device is

possible and the device behavior is analog to the well-known RTD.

To optimize the devices for operation as sensitive envelope detector, numerical device simulation based on Green’s function have been performed. Critical parameters for the optimization are the width of the second well and the material and thickness of the third barrier. Here it is important to provide low energy levels in the well to allow low voltage operation of the device. The third barrier must be designed for an optimum between high current density and low thermionic current through the device.

III. LAYER STRUCTURE

Table 1 Layer sequence of the fabricated TBRTD. The material X is AlAs for sample A and InAlAs for sample B.

function Material thickness [nm]

doping [1018cm-3]

Contact layer In0.7Ga0.3As 8 37.4 Contact layer InGaAs 100 37.4 Grading layer InGaAs 50 37.4 to 1 Spacer InGaAs 1.17 Barrier X 1.7 Well, smoothing InGaAs 1.17 Well InAs 2.42 Well, smoothing InGaAs 1.17 Barrier AlAs 1.7 n.i.d. Well, smoothing InGaAs 1.17 Well InAs 1.21 Well, smoothing InGaAs 1.17 Barrier AlAs 1.7 Spacer InGaAs 1.17 Contact layer InGaAs 10 1 Grading layer InGaAs 50 1 to 37.4 Contact layer InGaAs 300 37.4 Substrate s.i. InP

The investigated double quantum well devices are

InAs/InGaAs/AlAs and/or InAlAs-heterostructure grown by molecular beam epitaxy on semi-insulating InP-substrate. Wide band gap materials (AlAs and/or InAlAs) are used to realize barriers. The InGaAs/InAs/InGaAs-quantum wells are sandwiched between 1.7 nm barrier layers [5, 6]. In contrast to the InP-based RTD with double AlAs-barriers presented in [5], a second quantum well with thicker InAs-layer were

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added, to ensure an alignment or misalignment of two quantum levels under forward or reverse voltage bias respectively (fig. 1). The designed layer stack is presented in Table 1. AlAs layer was used for the barriers of sample A. The lattice matched InGaAs layers sandwiched between well and barrier material was used to smooth the surface above the lattice mismatched layers. For sample B, the lattice matched InAlAs was used for the third barrier. To provide good ohmic contacts to the device and therefore low intrinsic series resistance, heavily Si-doped InGaAs contact layers with doping concentration up to 3.74E+19 cm-3 were used.

IV. TECHNOLOGY

Fig. 2. REM picture of a realized 4*2.5*2.5 device

The processing of TBRTD was carried out using optical

lithography, dry and wet etching, and Ti/Pt/Au lift-off technology. Ni is used to protect the metallization during dry etching. First the TBRTD-anodes are patterned with positive photoresist. The metallization was done under vacuum in an evaporation system. Ni was added on the top of this metallization as a mask for ICP-RIE dry etching. After the first etching process, the lower interconnection layer was metallized by a similar process. A wet chemistry etching of the lower InGaAs interconnection layer provides an electrical separation of the devices on the wafer. The air bridge contacts to the top and lower electrodes are connected to an on wafer GSG measurement pad configuration. Figure 2 presents a fabricated device with four active mesa areas, to provide low parasitic capacitances and low contact resistances through the lower contact layer.

V. DC MEASUREMENT RESULTS

The current-voltage characteristics of the fabricated devices were measured on-wafer with a semiconductor parameter analyzer. The results are presented in figure 3. For both samples they show characteristics with good agreement to the theory. In forward direction a fast increasing current can be observed, up to the peak current density, equivalent to single quantum well RTD devices. With the low quasi discrete levels in the quantum well, induced by the InAs material, they show low peak voltages. This is an advantage for rectification of small signals without the need of biasing, because small

voltages in forward direction lead to a fast increase in current density. In backward direction good current blocking can be observed for small voltages. For voltages larger than 0.5 V for sample A and 0.4 V for sample B the increasing of the thermionic current can be observed. Even with three barriers the devices show high current densities comparable to RTDs. The values at peak voltage can be found in table 2.

Table 2 Peak currents of the devices (300K)

device Jpeak [kA/cm2]

Vpeak [V] PVCR

Sample A 80 0.4 1.6 Sample B 230 0.46 3

The peak to valley current ratio (PVCR) in forward

direction also shows competitive values for a three barrier device at room temperature, representing a good quality of the used epitaxial layers.

Fig. 3. Current voltage characteristics of measured devices (300K)

The differences between the samples are caused by the

material used for the third barrier. Here the current density can be improved by the use of InAlAs for sample B. This leads to higher tunnel probability through the last barrier. This improvement comes at the cost of faster increasing the thermionic current in reverse direction, but only for larger voltages. So for rectification of small voltages there is no significant influence. To investigate the rectification of the devices based on the current voltage characteristics, the rectification factor G can be calculated with the knowledge of the forward (JF(Vpos)) and backward (JB(Vneg)) current density.

𝐺 = 𝐽𝐹(𝑉𝑝𝑜𝑠)𝐽𝐵(𝑉𝑛𝑒𝑔)

, �𝑉𝑝𝑜𝑠� = �𝑉𝑛𝑒𝑔� (1)

Results of this calculation can be found in figure 4. Sample A provide a maximum rectification ratio of 10. For the second sample this value is improved up to 20 at a slightly lower voltage. The main task to improve these values is the suppression of the thermionic current in backward direction. In contrast to devices based on Schottky junctions that are mainly defined by the parameters of the used materials [7] the triple barrier rtd approach provides several parameters for

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optimization. Additional to the degree of freedom, by the material used, the doping profile in the contact layers and the thickness of the barriers and wells can be adjusted.

Fig. 4. Comparison of the rectification ratio of both samples at room temperature

Fig. 4. Rectification ratio of sample A at low temperature

To investigate the expected improvements by suppressing

the thermionic current component at low temperatures measurements down to 50 K are performed with sample A. As expected from theory, the current caused by tunneling processes is not significantly influenced by changes in temperature. This leads to improved rectification factors for lower temperature. The values increase up to 37 at 50 K for the investigated sample.

VI. RF MEASUREMENT RESULTS

To analyze the high frequency behavior of the samples, measurements are performed with a vector network analyzer for frequencies up to 50 GHz. All measured data were deembedded by using open and short structures on the investigated wafers. For the analysis of the devices the small signal equivalent circuit, presented in the inset of figure 5 is used. In a first step measurements at peak current densities are performed. These were used to calculate the series resistance

Rs of the device like presented in [8]. For sample A, this leads to a value of 5 Ohm for a device with an active area of 8 µm2. With this knowledge the bias dependent elements Rdiff and CRTD can be calculated. Extracted values for an 8 µm device are presented in figure 5.

Fig. 5. Differential resistance and capacitance of a 8 µm2 device on sample A

The capacitance of the device is one of the key elements for providing rectification for signals at high frequencies. To get an impression in comparison with other possible elements the capacitance for a defined current density is calculated. The capacitance per current density is 0.39 fF/kA for sample A and 0.14 fF/kA for sample B. The speed-index s is calculated by equation 2.

∆𝑉 ∗ 𝐶 = ∆𝐼 ∗ ∆𝑡 ⇒ 𝑠 = ∆𝑡

∆𝑉= 𝐶

∆𝐼�𝑝𝑠𝑉� (2)

For the investigated samples the following table shows the results with fast switching speeds, up to 0.14 ps/V for sample B. Table 3 Speed index of the devices (300K)

Device Jpeak [kA/cm2]

Cpeak / kA [fF/kA]

S [ps/V]

Sample A 80 0.39 0.39 Sample B 230 0.14 0.14

To optimize the capacitance the undoped spacer layer and

the design of the graded contact layer provide possibilities to improve the device performance by lowering the capacitance.

VII. FIRST RESPONSIVITY MEASUREMENTS

Short circuit responsivity is evaluated in first measurements, with a bias tee and an rf-signal source for frequencies up to 20 GHz. The dc-path is short circuited and the current was measured. The short circuit responsivity measured on sample B was nearly constant over frequency up to 20 GHz.

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Fig. 4. Simple detector circuit with a bias tee

Neglecting the losses by cables and coplanar probe, 2.5 A/W can be measured for a 6.25 µm device with -5 dBm input power. This value is factor 5 smaller than theoretical values presented for a 100 µm2 Schottky diode [7]. The measured value could be improved by matching the device to the high frequency source, and by including a correction for the losses of the measurement setup.

VIII. CONCLUSION

In this work we present a triple barrier tunneling diode for zero bias rectification. The nonlinearity is based on an unsymmetrical design of the two quantum wells. While the second well is designed with a thicker InAs layer, the first discrete energy level has significant lower energy. This leads to a blocking behavior for negative voltages. The fabricated elements show high current densities up to 240 kA/cm2 and low capacitances down to 0.14 fF/kA. With this the devices are good candidates for high frequency rectification, perhaps up to the THz frequency range.

REFERENCES

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