A Motor Speed Control System UsingDual-Loop PLL and Speed Feed-Forward/Back

Hidekazu Mchida, Michinobu Kambara, Kouta Tanaka and Fuminori Kobayashi

Abstract— PLL speed control systems can completely rejectspeed error and steady-state phase error for constant-speedinputs. Though it does not usually handle inputs includingacceleration, the dual-loop scheme improves, as a feed-forwardcontrol system, rising time and phase error for accelerationinput. However, since it is fundamentally a third-order PLL,it has slow rising up characteristics than speed feed-back, andcannot avoid over/undershoots. Nonetheless, the first loop hasrapid rising up characteristics and no over/undershoot, since itis an ideal second-order PLL system. In this article, to solve theproblem, we show a hybrid system of the dual-loop PLL andspeed feed-forward/back. It has fast rising up characteristicsand no over/undershoots thanks to the first and third PLL asF/V converter, which cannot be achieved in traditional PLLsystems.

I. INTRODUCTION

PLL, phase locked loop [1], is a control system thatgenerates a signal synchronizing to the phase of a ”reference”signal. PLL has been applied to MSC(motor speed control),originally by Moore [2]. PLL MSC features that systems cantheoretically reject speed error and steady-state phase errorcompletely for input signals with constant speed. Researcheson PLL MSC are being actively published as in [3]-[6].

However, PLL MSC is usually used for constant speed reg-ulator. When used as servo for input including acceleration,such as in CLV (Constant Linear Velocity) control of CDdrives, slow response poses problem. Out-of-lock in phaseeasily occurs, involving oscillatory pull-in behavior.

In the field of radio communication, possible remedy forthis situation called “dual-loop PLL” [7] has been used. Ithas two PLL loops, where first one without loop filter, is thefeedforward component of the second one with loop filter.As a result, it can not only enable high-speed tracking, butalso cancel phase error.

Regrettably, motor control systems differ from circuitsbecause of delays, and phase error cancellation cannot beachieved, if the output of the phase detector of both loops isnot added directly. For this problem, we proposed to cancelthe phase error, a method by inserting a filter in the feedbackof both loops [8].

A problem with this scheme is that, since it is fundamen-tally a third-order PLL, it has slow rising up characteristics

H. Machida and Kouta Tanaka is with the Maizuru nationalcollege of technology, 234 Shiroya, Maizuru, Kyoto, Japanmachida@maizuru-ct.ac.jp

Michimobu Kambara is with the Factory-Automation Electronics Inc.,1-6-14 dai-ni nichidai building 1F, higashinakajima, higasiyodogawa-ku,Osaka, Japan

F. Kobayashi is with the Kyushu Institute of Technology, 680-4 Kawazu,Iizuka, Fukuoka, Japan fkoba@ces.kyutech.ac.jp

than speed feed-back, and cannot avoid over/undershoots.However, the first loop has rapid rising up characteristics,and no over/undershoot, since it is an ideal second orderPLL system. In [9], we proposed hybrid of dual-loop PLLand speed feedforward for these reasons.

In this article, to get faster rising up characteristics, (1) out-of-lock is detected using a five-state phase detector; (2) atout-of-lock, speed control by both feedback and feedforwardis constructed by using the first and third PLL as F/Vconverter; and (3) when it reaches phase synchronization,it immediately returns to PLL. The second step forms a kindof speed feed-back control, generating no overshoot thanksto the rising up characteristics of the first and third PLL.This cannot be achieved in traditional PLL-MSC.

From Sec.II on, a short introduction of PLL systems,including dula-loop scheme, will firstly be given. Sec.IIIreviews dual-loop PLL-MSC speed systems. Sec.IV showshybrid control system of the dual-loop PLL and speed feed-back, with some experimental results, and Sec.V concludesthe article.

II. PLL SYSTEM

A. Basic PLL system

Block diagram of basic PLL [1] is shown in Fig.1. Itconsists of Phase Detector, PD for short, Loop Filter, LFfor short, and VCO, voltage-controlled oscillator, as well asDivider, DIV between the VCO and the feedback input tothe phase detector for frequency synthesizer applications.

When this feedback system is stable in operation, it iscalled locked, and phase error is zero or very small, leadingto synchronization between the input and output frequencies.

PD

’

in K-

Kvs

VCOLFfout

fin F(s)

N1

out

=N fin

fout’ =fin

DIV

Fig. 1. Basic PLL construction

When LF, loop filter, is of PI-type, as

F (s) =τ2s + 1

τ1s(1)

transfer function H(s), from input phase θin to feedbackphase θ′out, can be obtained as follows,

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Proceedings of the 2010 IEEEInternational Conference on Mechatronics and Automation

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H(s) =θ′out(s)θin(s)

=Kτ2s + K

τ1s2 + Kτ2s + K(2)

where K = KφKV

N . Steady-state phase error can be analyzedfrom the following final value theorem:

limt→∞φ(t) = lim

s→0s[1 − H(s)]θin(s)

= lims→0

sτ1s

2

τ1s2 + Kτ2s + Kθin(s) (3)

When input phase signal θin(s) has three components:phase step Δθ, frequency step Δω, and frequency ramp R,

θin(s) =R

s3+

Δω

s2+

Δθ

s. (4)

Steady-state phase error is zero for Δθ and Δω, but notzero for R, because:

limt→∞φ(t) =

τ1

KR (5)

B. Dual-loop PLL system

Dual-loop PLL [7] is intended to be used in fast-movingterminals such as satellites, to solve the problem of Dopplereffect.

In the dual-loop PLL shown in Fig. 2, the first loop doesnot have LF, but the second loop has a filter that maintainsphase margin. VCO of the second PLL is fed both by theLF output of the second loop and by the PD output of thefirst loop. PLL output is fed by the VCO of the second loop.

PD

in

First Loop

Second Loop

K1

-

KV1s

VCO

K2

-

++

fin

in +

fout

1

1N

1’

1N

2’

LF

F(s)

=N fin

KV2s

VCO

PD

DIV

DIV

Fig. 2. Dual-loop PLL construction

When input signal has the form of Eq. (4), steady phaseerror can be zero for frequency ramps with constant accel-eration R in the input. It is for cases where VCO gain KV 1

and motor gain KV 2 are equal, because:

limt→∞φ(t) =

τ1N(KV 1 − KV 2)KV 1KV 2

R = 0 (6)

That is, it can reject phase error for input acceleration andtrack to high speed input, because the system forms a kindof feed-forward structure.

III. DUAL-LOOP PLL-MSC SYSTEM

A. Basic PLL-MSC system

PLL-MSC system [2],[4] can be achieved only by replac-

ing VCO transfer functionKV

sin Fig.1 by motor + rotary

encoder transfer functionKm

s(Tms + 1). Where Tm is the

motor mechanical time-constant, and Km is the motor gain.Because this PLL-MSC system is still only of type two,

from the internal model principle, phase error for inputacceleration remains as: (where K = KφKm

N )

limt→∞φ(t) =

Tmτ1

KR (7)

B. Dual-loop PLL-MSC System

However, direct application of this PLL to motor speedcontrol poses a problem, because the plants are different:the first loop has VCO and the second loop has motor, andcomplete correspondence cannot be expected.

We solved this problem by inserting loop filters into bothfeed back paths as shown in Fig.3. Then, the feed-forwarderror cancellation is caused only when input including accel-eration, and feed-back correction by the second loop is notnecessary.

m Kms(Tms+1)

Motor+Encoder

PD

in

First Loop

Second Loop

K1

-

KV1s

VCO

PD

Km

-

++

LF

F(s)

fin

in +

fout=fm

1

1N

1’

1N

m’

LF

F(s)

=N fin

DIV

DIV

Fig. 3. Dual-loop PLL-MSC

When input signal has the form of Eq. (4), steady phaseerror can be reduced to zero for frequency ramps withconstant acceleration R in the input. It is for cases whereVCO gain KV and motor gain Km are equal, because:

limt→∞φ(t) =

τ1N(KV − Km)KφKV Km

R = 0 (8)

C. Simulation

For a DC motor with brushes, Sawamura SS32G, whereTm=11[msec],Km=3.39[kHz/V], the loop filter was designedby the method of reference [1]. By MATLAB simulation forthe case of single loop PLL-MSC, it is confirmed that steady-state phase does not coincide with inputs with constant

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f1

U/D cnt

1N

enb

clk2

_1

clk

rst

Divider

A

B

A>B

Accumlator

enb

enb

fm'

CMP

AMPMotorEncoder

fm

Up cnt

clk3

PWM

clk

rst

clk2

_2

clk

rst

1N

Divider

f1

f1'

NCOenb

clk

rst

clk4

PFD

clk

lag

lead

clk

data Q

+Kp MUX 0-Kp

+KpMUX

0-Kp

PFDlag

lead

Fig. 6. dual-loop PLL/PWM-MSC system

0 0.2 0.4 0.6 0.8 1-0.2

0

0.2

0.4

0.6

0.8

1

1.2

time [sec]

rota

tiona

l spe

ed[r

pm]

reference inputmotor output

Fig. 4. Responses for inputs with constant acceleration of the single PLL-MSC by MATLAB simulation

acceleration (Fig.4). Here, note that squared ramp is equalto constant acceleration.

On the other hand, in the case of dual loop PLL-MSC, itis confirmed that steady-state phase coincides with for inputswith constant acceleration (Fig.5).

0 0.2 0.4 0.6 0.8 1-0.2

0

0.2

0.4

0.6

0.8

1

1.2

time [sec]

rota

tiona

l spe

ed[r

pm]

reference inputmotor output

Fig. 5. Responses for inputs with constant acceleration of the dual PLL-MSC by MATLAB simulation

D. Dual-loop PWM control

We implement the dual-loop PLL/PWM-MSC system [8]with an FPGA, a programmable LSI. Fig.6 shows that it canbe implemented compactly all in digital by using the 1-bitPWM signal processing of the phase detector(PFD).

In the first loop, NCO, Numerical Controlled Oscillator,is used instead of VCO, Voltage Controlled Oscillator. Inthe second loop, the comparator modulates output of the PIfilter to PWM again, and power MOS-FET droves the motoraccording to its duty ratio.

E. Experimental result

The circuit of Fig.6, using the parameters KP same as thesimulation described in Sec. III-C,

was programmed in a single-chip FPGA, field pro-grammable gate array, a user-programmable LSI, and wasexperimented.

To begin with, it is confirmed that lock is achieved bysetting rotational speed with the programmable divider forall the possible speeds.

Next, oscilloscope observations shown in Fig.7 revealedthat steady-state phase error of the first row and third rowgoes to zero for input with constant acceleration.

reference input in(in acceleration)

first PLL output 1(lag from in)

second PLL-MSC output m(almost following to in)

phase lag occurs

no phase lag occurs

Fig. 7. Waveforms (for input acceleration)

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f1

U/D cnt

1N

enb

clk2

_1

clk

rst

Divider

A

B

A>B

Accumlator

enb

enb

fm'

CMP

AMPMotorEncoder

fm

Up cnt

clk3

PWM

clk

rst

clk2

_2

clk

rst

1N

Divider

f1

f1'

NCOenb

clk

rst

clk4

PFD

clk

lag

lead

PFDlag ilead i

clk

lag o

lead o

data Q

+Kp MUX 0-Kp

+KpMUX

0-Kp

Fig. 11. hybrid of dual PLL and speed feed-forward

Next, we shows frequency step responses obtained fromF/V-converted motor encoder output.

As in Fig.8, it is shown that the first loop acceleratessecond loop, and no over/undershoots occur when gain islow. This characteristic cannot be obtained by single loop,unless with far lower gain, which causes very slow responses.

Fig. 8. Step speed response of dual loop PLL motor speed control system(low KI gain)

However, as shown in Fig.9, It can not avoidover/undershoots when gain is set high for faster responses.

Fig. 9. Step speed response of dual loop PLL motor speed control system(high KI gain)

IV. HYBRID-MSC OF THE DUAL-LOOP PLL AND

FEED-FORWARD/BACK

A. Principle of the Hybrid-MSC

On the other hand, since the dual-loop PLL-MSC sys-tem is fundamentally a third-order PLL, it cannot avoidover/undershoots when gain is set high for fast responses.Nonetheless, the first loop has ideal rapid rising up charac-teristics without over/undershoot, since it is an ideal secondorder PLL system.

To solve the above problem of slow rising up characteris-tics and over/undershoots,

(1) out-of-lock is detected using a five-state phase detector.(as shown in Fig.10);

(2) at out-of-lock, speed feed-forward/back is constructedby using the first and third PLL as F/V converter; and

(3) when it reaches phase synchronization, it immediatelyreturns to PLL. The second step forms a kind of speedfeed-back control, generating no overshoot thanks tothe rising up characteristics of the first PLL.

leadi lock lagi lagoleado

lock in rangeout of range out of range

Fig. 10. Five state PFD

1) Hybrid of dual-loop PLL and speed feed-forward: Inthe step (2), at out-of-lock, integration counter of the secondloop is replaced by the one in the first loop as shown inFig.11. It is constructed as speed feed-forward scheme asshown in Fig.12. That is, first loop PLL is used as ideal F/Vconverter.

1515

f1

U/D cnt

1N

enb

clk2

_1

clk

rst

Divider

A

B

A>B

Accumlator

enb

enb

fm'

CMP

AMPMotorEncoder

fm

Up cnt

clk3

PWM

clk

rst

clk2

_2

clk

rst

1N

Divider

f1

f1'

NCOenb

clk

rst

clk4

PFD

clk

lag

lead

PFDlag ilead i

clk

lag o

lead o

data Q

+Kp MUX 0-Kp

+Kp

MUX

0-Kp

U/D cnt

enb

clk2

_1

clk

rst

Divider

f3'

NCOenb

clk

rst

clk4

PFD

clk

lag

lead

+Kp MUX 0-Kp

1N

fm'

f3

1bitleft shift

Fig. 15. hybrid of dual PLL and speed feed-back

Tms+1Kmfin fm

Motor +Encoder1st PLLas F/V

Fig. 12. speed feed-forward by using PLL as F/V

The rising up characteristic is completely correspondingto first PLL, and no over/undershoots occurs, even if firstPLL gain is set high for fast responses, as shown in Fig.13and 14 . From these figures, it is understood that the firstloop behaves as an idealized model of the second loop.

Fig. 13. Step speed response of hybrid of the dual loop PLL and feed-forward motor speed control system (low KI gain)

Fig. 14. Step speed response of hybrid of the dual loop PLL and feed-forward motor speed control system(high KI gain)

2) Hybrid of dual-loop PLL and speed feed-back: In thestep (2), at out-of-lock, content of the integration counterof the second loop is replaced by the one in the first loop,multiplied by 2, minus the one in the third loop, as shown inFig.15. It is constructed as speed feed-back scheme as shownin Fig.16. That is, first and third loop PLL is used as idealF/V converter. As a result, the time constant is improvedfrom Tm to Tm

2Km+1 .

3rd PLLas F/V

2Tms+1

Kmfin fmMotor +Encoder

1st PLLas F/V

Fig. 16. speed feed-back by using PLL as F/V

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By MATLAB simulation for the case of speed feed-back,it is confirmed that rising up characteristics is improved asshown in Fig.17.

uncontrolled motor output

F/V by first PLL

motor input

controlled motor input

time [sec]

norm

aliz

ed ro

tatio

nal s

peed

[r.p

.m.]

Fig. 17. MATLAB simulation of speed feed-back

B. Experimental Results

The circuit of Fig.15 was programmed in a single-chipFPGA and was experimented.

As shown in Fig.18, motor input voltage is sharper forhybrid of feed-forward and feed-back.

(a) original dual-PLL MSC

(b) hybrid of feed-forward and dual PLL

(c) hybrid of feed-back and dual PLL40 [msec/DIV]

first PLL

motor input

motor input

motor input

first PLL

first PLL

Fig. 18. Motor input voltage

Fig.19 shown the frequency step responses obtained fromF/V-converted motor encoder output. It is understood thatfaster rise-up is possible for feed-forward and feed-back.

(a) original dual-PLL MSC

(b) hybrid of feed-forward and dual PLL

(c) hybrid of feed-back and dual PLL40 [msec/DIV]

first PLL

motor output

motor output

motor output

first PLL

first PLL

Fig. 19. Motor rotational output

V. CONCLUSION

The dual-loop PLL-MSC system can accelerate rising timeand can cansel the phase error in acceleration input. However,it has still slow rising up characteristics than speed feed-back,and cannot avoid over/undershoots.

We show hybrid control system of the dual-loop PLLand feed-forward/back, to solve the above problem. It hasrapid rising up and no overshoot thanks to the rising upcharacteristics of the first and third PLL. This cannot beachieved in traditional PLL-MSC systems.

REFERENCES

[1] R.E. Best:Phase-Locked Loops 6th.ed.,McGraw-Hill, 2007.[2] A.W. Moore : Phase-locked loop motor-speed control, IEEE Spectrum,

pp.61-67, Apr. 1973.[3] Yoon Yong-Ho et al.: PLL control algorithm for precise speed control

of the slotless PM brushless DC motor Using 2 Hall-ICs, 35th IEEEPE Special. Conf., Vol. 2, pp. 1315-1321, 2004.

[4] J.X. Shen and S. Iwasaki; Sensorless control of ultrahigh-speed PMbrushless motor using PLL and third harmonic back EMF, IEEETrans., Vol. IE-53, Issue 2, pp. 421–428, 2006.

[5] J. Deskur and A. Maciejuk: Application of digital phase locked loopfor control of SRM drive, IEEE Europ. Conf. Power Electron. Appl.,pp. 1-6, 2007.

[6] C.T. Pan and E. Fang: A Phase-Locked-Loop-Assisted Internal ModelAdjustable-Speed Controller for BLDC Motors, IEEE Trans., Vol. IE-55, Issue 9, pp. 3415-3425, 2008.

[7] M. Kamata, et al.: Third-order phase locked loops using dual loopsinserting an active filter in the second loop with improved stability,IEICE-A, Vol. J82-A, No. 2, pp. 273–282, in Japanese, 1999.

[8] H. Machida et al.: A PWM Motor Speed Control System based onthe Dual-Loop PLL!$ ICROS-SICE in Fukuoka, 1A18-3, pp. 418-423,2009.

[9] H. Machida et al.: A Motor Speed Control System Using a Hybridof and Dual-Loop PLL and Feed-Forward!$ ACM-2010 in Nagaoka,Japan, NF-000361, pp. 185–190, 2010.

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