Dynamic circuits for Ternary computation inCarbon Nanotube based Field Effect Transistors

Kundan NepalDepartment of Electrical Engineering,

Bucknell University, Lewisburg, PA 17837, USA.

Abstract— As we continue downscaling devices, a numberof nanoscale materials have been proposed as replacementsfor Silicon based devices. Carbon nanotubes have attractedwidespread attention and numerous researchers have shownthat digital circuits can be created using the field-effectproperties of these nanoscale devices. This work investigatesthe design of multi-valued computation in carbon nanotubebased field effect transistor (CNTFET). Using a CompleteModel technique, we show that dynamic ternary logic canbe implemented in CNTFET devices and that the delayand power-consumption of this approach is much lowercompared to previous multi-valued implementations.

I. INTRODUCTION

As we head into the nanometer regime, a number of de-vices and architectures based on nanometer CMOS, non-silicon alternative devices and hybrid CMOS/nano sys-tems have been proposed. The large variety of proposedalternative systems provide circuit designers and systemarchitects with a wonderful array of research possibilitiesand challenges. Some exciting research challenges includethe unreliable behavior of many proposed devices, theproblem of terascale integration, efficient circuit designand their manufacturability, new design tools to handlethe complexity of nanoscale designs and efficient multi-valued computation.

Since its discovery in early 1990s, carbon nanotube hasgained wide popularity and semiconducting nanotubes assmall as 1nm in diameter and as long as a few micronshave been successfully demonstrated [1], [2]. The use ofcarbon nanotubes to create nano-Field Effect Transistors(CNTFETs) has been shown in [3], [4]. It was shownin [4]that both P-type and N-type FETs can be createdby injection of electrons and holes by either doping thenanotube or by simply controlling the metal-nanotubeSchottky barriers at the contacts.

Substrate

nanotubenanotube

oxide

S DG

S DG

Dielectric

(a) (b)Figure 1. (a)Cross-section and (b) top view of a CNTFET structure.

Figure 1 shows the basic cross-sectional and top viewof a CNTFET. An array of nanotubes is grown/placed onan oxide layer over a silicon substrate. A gate contact

and source and drain metal contacts are placed to formthe FET. Since an array of tubes is used, the total widthof the FET is given by the product of the number of thetubes and the pitch of the tube. As in silicon MOSFET, thechannel length is given by the length of the tube under thegate. The fabrication process can yield either a metallicor semiconducting tube depending on the angle of thearrangement of carbon atoms along the tube. This angle ofarrangement is referred to as the chirality vector (n1, n2).The chirality vector determines the diameter, the thresholdvoltage (VTH ) and dictates whether the tube will behaveas a metallic or a semiconducting tube. The diameter ofthe tube is given in terms of the Carbon-Carbon bondlength (aC−C = 1.42A) and the chirality vectors (n1, n2):

dtube =√

3aC−C

π

√(n2

1 + n1n2 + n22) (1)

The threshold voltage is defined in terms of dtube andindirectly in terms of the chirality vectors and can beapproximated as:

VTH ≈ aC−C

dtube3.0333V (2)

In this paper, we use a single-diameter CNTFET to designlogic circuits for multi-valued computation. The rest ofthe paper is organized as follows: Section II provides abrief overview of Ternary logic and presents examples ofprevious design; Section III presents the design and simu-lation results of our dynamic ternary gates and Section IVconcludes this paper.

II. TERNARY LOGIC

TABLE I.SET OF LITERAL OPERATORS

X X 0X0 1X1 2X2

0 2 2 0 01 1 0 2 02 0 0 0 2

A n-variable ternary valued function f(x1, ..., xn) isa mapping f : Sn → S, with the variable xi takingvalues from the set S = {0, 1, 2}. In a logical circuit,the three distinct logic levels 0,1, and 2 correspond tovoltage levels ground (GND), half-of supply (VDD/2) andsupply (VDD). In the binary computing system, the AND,OR and NOT functions serve as a universal set of gatesfrom which all other logic can be implemented. Similarly,a complete ternary logic set involves a set of literaloperators(aXa), the inverse, the minimum (MIN) and

978-1-4244-6805-8/10/$26.00 ©2010 IEEE

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maximum (MAX) functions. Table I shows the inverseand the literal operators. It has been shown that all othermulti-threshold literal operators aXb can be representedusing inverses and the literal operators aXa [5].

VDD

OUT

P2

N2

P1

N3

P3

N1

INX

T2T1INX

VDD

100kΩ

100kΩ

OUT

P1= -0.289VP2= -0.559VP3= -0.428V

N1=0.289VN2=0.559VN3=0.428V

T1= 0.289VT2= 0.559V

VTH

VTH

VTH

(a) (b)

Figure 2. Ternary Inverter from (a) REF [6] and (b) REF [7]. Thethreshold voltages for the different FETs are presented on the side.

The information density in ternary logic is much highercompared to the regular binary logic. It has been shownthat numerous mathematical functions can be operatedwith fewer operations in ternary logic leading to an overalladvantage over binary logic in terms of area, delay andpower. However, the added complexity during fabricationand the overall unfamiliarity with multi-valued algebrahas kept CMOS ternary computation a relatively smallerfield. Researchers have successfully designed differentcurrent and voltage mode multi-valued circuits [8], [9].Different work have also looked at creating a much sim-pler design style and tried to reduce the added complexityduring manufacturing [10].

New nanomaterials provide a new opportunity formulti-valued computation. A number of researchers haveproposed the CNTFET as a foundation for ternary com-puting [6], [7], [11]. The work of [6]proposes the use ofcarbon nanotubes fabricated with different chiral vectorto exploit the different threshold voltage of the differenttubes. The authors proposed a design with large resistorthat constantly pulled the output to VDD. The pull-down network had another resistor and two NFETs topull the output node to either VDD/2 or to GND asshown in Figure 2(a). While the design produces a goodternary inverter, the design requires large resistors to beimplemented which is harder to do with carbon nanotubes.Also the constant pull-up path results in larger powerconsumption. The design for circuits proposed in [11] issimilar in concept to [6] where a resistive network andmultiple-threshold tubes are used.

The authors of [7] propose a resistor-less design butagain use three different types of carbon nanotubes fordifferent threshold voltages. The design is shown inFigure 2(b). While it has been shown that differentdiameter and hence different threshold CNTFETs can beproduced, growing tubes with different chiral vectors onthe same substrate can require very precise control overthe manufacturing process.

In this paper, we introduce CNTFET based dynamic

ternary logic circuits based on Complete Model techniqueproposed in [12]. We show the design for some of thebasic ternary gates and analyze the transient characteris-tics of the gates. Our design do not require that differentdiameter tubes and hence different threshold voltage FETsbe present in the circuit reducing the burden on theprocess of growing nanotubes on a substrate.

III. DESIGN AND SIMULATION

VDD

VDDL

OUTf0 P1

N1 N2 f2f1

Figure 3. Complete Model Structure

The Complete Model structure of [12] uses two powersupplies, a regular supply voltage (VDD) and a lowersupply voltage (VDDL). In the Complete Model structure,as shown in Figure 3, a clear path exists to the output nodefrom each of the reference voltage (VDD, VDDL andGND). A binary function fk acts as a binary-to-ternaryinterface and activates only one of the three paths at anygiven time and thus allows the design of ternary logicwithout the need to rely on multi-threshold FETs.

VDD

VDDL

VDD

PREINY

PRE

OUT

PREINY

INX

P1

N1P2P3

P4

N4

N2

N3

N5

A1

A2

Figure 4. CNTFET dynamic complex gate schematic

A general dynamic complex gate (CMGate) design isshown in Figure 4. The circuit has a pre-charge signal(PRE), which is either at VDD or GND, and acts as thebinary-to-ternary interface. When the PRE signal is atVDD, the output node is pre-charged to VDDL (LOGIC1) through transistor N2. Internal node A1 is pulled upto VDD through PFET P4 and node A2 is pulled downto GND through NFET N1. This allows the output nodeto stay at VDDL (LOGIC 1). Evaluation of the outputnode occurs when PRE is pulled down to GND. Let usconsider the case when INY is at LOGIC 2 (VDD). Thisvalue causes NFET N4 to be ON while PFET P3 to beOFF. Since PRE is 0, transistors N5 and P2 are turnedON. INY=2 causes P3 to be turned OFF so node A2remains at 0 - the value it was pulled down to when PREwas at VDD while A1 gets a voltage value dependent onthe input INX. If INX =0, the NFET transistors N4 andN5 pass the value quite well so A1 = 0 causing OUT to

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be pulled up to VDD (LOGIC 2) through P1. If INX=1,the node at A1 is at LOGIC 1. The node voltage at A1 isslightly higher than the threshold voltage of P1 so nodeOUT is again pulled up to VDD (LOGIC 2) through P1.When INX is at LOGIC 2, the NFET has a harder timepassing high voltage, a threshold drop occurs and voltageat node A1 is just under VDD. At this point, A2 is at 0,A1 is close to VDD, so both P1 and N1 are off. The OUTnode that was pre-charged to LOGIC 1 remains at LOGIC1. By similar analysis, we can find out what happens tooutput node when input INY is at LOGIC 0 and LOGIC1. Table II presents a summary of the logical value atoutput node OUT as a function of input nodes INX andINY during the EVALUATE cycle (i.e. PRE=0).

TABLE II.LOGICAL VALUE AT NODE OUT FOR VARIOUS VALUES AT NODE

INX AND INY

INY0 1 2

INX 0 1 2 2

1 0 1 22 0 0 1

In order to observe the transient behavior of the circuitand to verify the functionality, we use the SPICE modelfrom [13] with the following parameters:

High-Supply Voltage (VDDH) = 0.9VLow-Supply Voltage (VDDL) = 0.45VCNTFET tube Chirality Vector (n1, n2) = (19,0)CNTFET Threshold Voltage (VTH )=0.3VCNTFET tube diameter(dtube )=1.5nmNumber of tubes per FET = 8Pitch = 20nmGate Length = 32nm

Figure 5 shows the results of the SPICE simulation ofthe complex dynamic gate. The pre-charge signal (PRE)oscillates between VDD and GND at a frequency of500MHz. It pre-charges the output node OUT to VDDLfor 1ns and allows evaluation of the node for another 1ns.Inputs INX and INY represent all 9 possible state pairswhere each state pair is active for a duration of 10ns. Theoutput result follows the behavior outlined in Table II.There are some noticeable spikes at the transitions whichcan be attributed to delay of the different paths of thecircuit which causes a time-lag between output node andthe PRE signal going to the pre-charge state and relaxingto the evaluate state.

Now consider the logical behavior of the complex gateshown in Figure 4 shown in Table II. It can be seen fromthe table that if input INY was fixed at LOGIC 1, theoutput of the circuit is the inverse of input INX. Thus, thecircuit can be used as a ternary inverter by simply fixinginput INY to VDDL. Figure 6 verifies the functionalityof the circuit when used as a dynamic ternary inverter.By similar analysis, it can also been seen that the circuitcan also be used as a ternary buffer by varying input INYwhile keeping input INX fixed at LOGIC 1.

Besides the functional verification of the dynamic in-verter, we compare this design to the ternary inverterdesigns of [6] and [7] in terms of the delay and power con-sumption. The average delay of the circuits is computed

Figure 5. SPICE simulation of the complex dynamic gate (CMGate) ofFigure 4.

Figure 6. SPICE simulation of the complex dynamic gate (CMGate)used as a Ternary Inverter. Input INY is fixed at LOGIC 1.

by taking the average of the delay for a transition from onelogic state to the other. Using design parameters discussedearlier, SPICE simulation showed that the new dynamicdesign was only slightly faster than the two previousdesigns. Since the design of [6] uses resistive networkand has a direct path from VDD to GND when the NFETis in conduction, it is clear that its power consumptionwould be the worst. SPICE simulation of the three designsummarized in Table III verifies this. Simulation resultsalso show that the power consumption of the new designwas an order of magnitude lower than the design of [7]making it ideal for low-power operation.

TABLE III.POWER CONSUMPTION AND DELAY ANALYSIS OF TERNARY

INVERTER DESIGN.REF [6] REF [7] This work

Power(uW) 3.79 0.52 0.04Delay(ps) 3.03 2.97 2.75

Using this principle, we show the design of the MINgate that calculates the minimum of the two inputs. TheMAX gate can be designed using similar principle. Thelogical table for the MIN gate is shown in Table IV. In thecircuit shown in Figure 3, let us replace signal f2 with thepre-charge signal (PRE) we discussed in the design of theinverter. To maintain a LOGIC 1 at the output, signals f0

and f1 need to be at LOGIC 2 and 0 respectively to cutoff

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VDD

VDDL

VDD

PREINY

PRE

OUT

PREINY

P1

N1P2P3

P4

N5

N2

N3

N6

A1

A2

INX

P5

INX

N4

VDD

Figure 7. Schematic of the MIN function.

any path from the output to either VDD or GND. To get aLOGIC 2 at the output, during the EVALUATE cycle, weneed both f0 and f1 to be at 0. Similarly, for a 0 at output,we need both f0 and f1 to be at LOGIC 2. Now considerthe circuit shown in Figure 7. Nodes A1 and A2 representf0 and f1 respectively. Since we are implementing theMIN function, anytime one of the input is a 0, the outputmust be a 0. During the EVALUATE cycle, when eitherINX or INY is a 0, node A2 is at VDD (i.e. LOGIC 2).At the same time, transistors N4, N5 and N6 are OFFand node A1 stays at its pre-charged value of 2. Sinceboth A1 and A2 are at LOGIC 2, the output is pulleddown to 0 through NFET N1. By similar analysis whenboth INX and INY are at LOGIC 2, P3 and P5 are OFFcausing node A2 to remain at its pre-charged value of 0.At the same time, N4, N5 and N6 are ON causing nodeA1’s precharged value to discharge to ground. This turnson PFET P1 and allows the output node to be charged toLOGIC 2. When INX and INY are both at LOGIC 1, orwhen one of them is at LOGIC 2 while the other is at 1,A1 and A2 remain at their pre-charged values during theevaluate cycle causing the output node also to stay at itspre-charged value of LOGIC 1. These conditions lead usto the logical function of the MIN gate. SPICE simulationshown in Figure 8 verifies the functional correctness ofthe MIN gate.

TABLE IV.LOGICAL VALUE AT NODE OUT FOR VARIOUS VALUES AT NODE

INX AND INY FOR THE MIN GATE

INY0 1 2

INX 0 0 0 0

1 0 1 12 0 1 2

IV. CONCLUSIONS

A new dynamic structure based on the Complete Modelapproach for implementation of ternary logic in CarbonNanotube FETs (CNTFETs) is presented. Unlike previouswork, the design uses a clock signal to pre-charge andevaluate a node and does not rely on the precise growthof tubes with different diameters and threshold voltages.Using SPICE simulation, we showed that this approachprovides functionally correct circuit that is faster and

Figure 8. SPICE simulation of the MIN Gate.

consumes much less power than the previously reportedternary designs. In this paper, we showed the design acomplex dynamic gate that could be used as an inverter ora buffer. The approach was extended to shown the designof the MIN function gate. Other logic gates such as thedifferent literals and MAX gates can be designed usingthe same recipe presented here. The results from SPICEsimulations are encouraging and show that the dynamicternary logic gate can be a viable approach for low-powerand high speed design in the CNTFET domain.

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