Low-Power 48-GHz CMOS VCO and 60-GHz CMOS LNA for 60-GHz Dual-Conversion Receiver

Yo-Sheng Lin, Tien-Hung Chang, Chang-Zhi Chen, Chi-Chen Chen, Hung-Yu Yang, and Simon S. Wong+

Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, R.O.C.

Tel: 886-4-92912198, Fax: 886-4-92917810, Email : stephenlin@ncnu.edu.tw +Department of Electrical Engineering, Stanford University, Stanford, California, USA

Abstract− A low-power low-phase-noise 48-GHz CMOS LC voltage-control oscillator (VCO) and a low-power 60-GHz CMOS low-noise amplifier (LNA) for 60-GHz dual-conversion receiver are reported. The VCO dissipated 5.556 mW power, and achieved state-of-the-art phase noise of −105 dBc/Hz at 1-MHz offset from 47.84 GHz. The corresponding figure-of-merit (FOM) was −191.1 dBc/Hz, which is better than those of the reported CMOS LC VCOs around 48 GHz in the literature. Besides, the LNA consumed 21.4 mW power, and achieved input return loss (S11) of −10.6~ −37.4 dB, voltage gain (AV) of 10.7~ 18.8 dB, reverse isolation (S12) of −43.5~ −48.1 dB, input referred 1-dB compression point (P1dB-in) of –16.2~ –20.8 dBm, and input third-order inter-modulation point (IIP3) of −4~ −7.5 dBm over the 57-64-GHz-band of interest.

Index Terms− low power, low phase noise, CMOS, LC, VCO, tuning range, LNA

I. INTRODUCTION

Fig. 1 shows a dual-conversion zero-IF receiver architecture for 60-GHz radio, in which a 60-GHz LNA is needed to amplify the small radio-signals received from the 57-64-GHz-band of interest with a good signal-to-noise ratio property. Besides, a 48 GHz VCO is needed for the first-stage down-conversion, and the 12-GHz VCO needed for the second-stage down-conversion can be obtained by dividing the 48 GHz VCO by two twice. Recently, several CMOS VCOs with operation frequency around 48 GHz have been reported [1]-[8]. In [1], it has been demonstrated that a low-power of 1 mW can be achieved for a 51.6-GHz VCO. However, the corresponding phase noise of −85 dBc/Hz (at 1 MHz offset) is not low enough. On the other hand, it has been demonstrated that low-phase-noise of −99 dBc/Hz (at 1 MHz offset) can be achieved for a 50 GHz VCO [2]. However, the corresponding power dissipation of 13 dBm is not satisfactory. To demonstrate that both low-power and low-phase-noise can be achieved for a CMOS VCO for 60-GHz radio, in this work, we present the design and implementation of a 5.556 mW, 48-GHz VCO with excellent phase noise of −105 dBc/Hz (at 1 MHz offset). Besides, a low-power 60-GHz CMOS LNA is also reported.

II. LOW-POWER 48-GHZ VCO 2.1 VCO Design

The standard 1P8M 0.13 μm CMOS process (with substrate resistivity of 8-12 Ω⋅cm) provided by TSMC was adopted to

2÷ 2÷

Fig.1 A possible 60-GHz CMOS receiver architecture: dual-conversion and zero-IF.

design the 48-GHz low-power and low-phase-noise CMOS LC differential VCO. Fig. 2(a) shows the schematic of the VCO, in which the important device parameters are labeled. To save the chip area, the LC-tank inductors are realized by a 1-turn differential spiral inductor (L1) with inner dimension of 74 �m, and metal width of 15 �m. Another advantage of driving an inductor differentially (in contrast to single-ended) is that a higher peak quality factor can be achieved, i.e. smaller power loss. The interconnection lines as well as the differential spiral inductor and the micro-stripline (MSL) inductors (L2~ L5) were placed on the 3.35-�m-thick topmost metal to minimize the resistive loss. The LC-tank was composed of the differential spiral inductor and two identical accumulation-mode NMOS varactors. The cross-coupled NMOS transistors pair (M1 and M2) formed a positive feedback loop to generate the needed negative resistance to compensate for the resistive loss in the LC-tank. To maximize the tuning range, the summed parasitic capacitance of the differential inductor and the cross-coupled NMOS transistors pair is minimized.

The PMOS transistor M3 functions as a current source for sourcing the core circuit. To suppress the flicker noise of M3 which was up-converted to 1/f3-shaped phase noise close to the carrier, large transistor size (W/L = 512.8 �m/0.35 �m) was adopted for M3. M4-M7 were output buffers for measurement, i.e. both for driving the 50-� load, and for increasing the output swing. Fig. 2(b) shows the chip micrograph of the finished circuit. The chip area was 0.94×0.9 mm2, i.e. 0.846 mm2, including the test pads.

2.2 Measurement Results and Discussions

On-wafer spectrum measurement was performed by an Agilent E4448A 50-GHz spectrum analyzer with phase noise measurement utility. The VCO core drew 4.63 mA current

978-1-4244-2782-6/09/$25.00 ©2009 IEEE 88

(a)

(b) Fig. 2 (a) Schematic and (b) chip micrograph of the 48-GHz CMOS LC VCO.

(a)

(b) Fig. 3 The measured (a) oscillation frequency (fosc) versus Vtune characteristics, and (b) phase noise and output power versus Vtune characteristics of the CMOS LC VCO.

Fig. 4 The measured output spectrum of the CMOS VCO.

Table I Summary of the measurement results of this work and the CMOS LC VCOs around 48-GHz in the literature.

from a 1.2 V power supply, i.e. it only consumed 5.556 mW. Fig. 3(a) shows the measured oscillation frequency (ωo) versus control voltage (Vtune) characteristics of the VCO. As can be seen, a tuning range of 760 MHz, from 47.83 GHz to 48.59 GHz, was achieved for Vtune varied from 0 V to 1.2 V. Fig. 3(b) shows the measured phase noise and single-ended output power (i.e. Vout+ or Vout− only, the other port connected to 50 terminal) versus Vtune characteristics of the VCO. As can be seen, state-of-the-art phase noise of −105 dBc/Hz and −102.5 dBc/Hz were achieved at 1-MHz offset from 47.84 GHz (Vtune = 0.4 V) and 47.92 GHz (Vtune = 0.6 V), respectively. Fig. 4 shows the measured single-ended output spectrum of the VCO at Vtune = 0.4 V (or fosc = 47.84 GHz). The corresponding single-ended output power was −19.07 dBm.

A widely-used figure-of-merit (FOM) for a VCO is defined as follows [5].

{ } o dcf PFOM L f 20log 10logf 1 mW

� � � �= Δ − +� � � �Δ� � � � (1)

, where L{�f} is the measured phase noise at �f frequency offset from the carrier frequency fo, and Pdc is the dc power dissipation in mW. Table I is a summary of the implemented 48-GHz CMOS LC VCO, and the recently reported state-of- the-art CMOS LC VCO around 48 GHz in the literature. As can be seen, compared with the measured results in other works, our VCO exhibits small power consumption, lowest phase noise, and the highest FOM. These results show that our implemented 48-GHz CMOS LC VCO is suitable for high-performance 60-GHz-band transceiver front-end applications.

0.0 0.2 0.4 0.6 0.8 1.0 1.247.747.847.948.048.148.248.348.448.548.648.7

Freq

uenc

y (G

Hz)

Vtune (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2-110-100-90-80-70-60-50-40-30-20-10

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Ref. CMOSProcess

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fosc

[GHz]PN

[dBc/Hz]Pdiss

[mW]FOM

This Work 0.13 47.85 -105 5.556 -191.1[1] 0.12 51.6 -85 1 -179.2[2] 0.25* 50 -99 13 -181.8[3] 0.18 49 4 -96 -184[4] 0.18 52.5 -86 41 -164.3[5] 0.13 43 -90 14 -174.2[6] 0.13 SOI 40 -90 11.3 -171.5[7] 0.12 SOI 44 7.5 -101 -185[8] 0.09 SOI 60 -94 9.6 -179.7

* modified substrate

89

(a)

(b) Fig. 5 (a) Complete schematic, and (b) chip micrograph of the 60-GHz CMOS LNA.

III. LOW-POWER 60-GHZ LNA 3.1 LNA Design

The 60-GHz CMOS LNA was designed by a 65 nm bulk CMOS process on a p-type silicon substrate with thickness of 300 �m and resistivity of 10 Ω⋅cm. This CMOS process offers seven metal layers, named M1 to M7 from bottom to top. The interconnection lines as well as the MSL inductors were placed on the 0.9-�m-thick topmost metal (M7). The oxide thickness between M7 and the 0.18 �m-thick M1 (used as ground plane of the MSL inductors), and between M1 and the silicon substrate was 3.67 �m and 0.61 �m, respectively. Fig. 5(a) shows the schematic of the LNA. To achieve sufficient gain, this LNA was composed of three cascade common-source stages followed by a cascode output stage. The output of each stage was loaded with a bandpass combination of L and C to provide parallel resonance, i.e. to maximize the gain, over the 57-64-GHz-band of interest. Simultaneous input impedance and noise matching over the 57-64-GHz-band of interest was achieved by appropriately selecting the values of C1, TL1, TL3, and the size and bias of the input transistor M1, i.e. Cgs1 and gm1. Since the dc current of the third stage of the LNA was reused in the second stage, no additional driving current was needed for the second stage. Table II is a summary of the simulation results.

3.2 Measurement Results and Discussions

The chip micrograph of the finished circuit is shown in Fig. 5(b). The chip area was only 0.849×0.56 mm2, i.e. 0.475

Table II Summary of the simulation results of the 60-GHz CMOS LNA.

(a)

(b)

(c) Fig. 6 The measured (a) S11, (b) voltage gain, and (c) S12 versus frequency characteristics of the 60-GHz CMOS LNA.

mm2, including all the test pads and bypass capacitors. On-wafer measurement was performed by an Agilent’s 67 GHz RFIC measurement system. The LNA was biased at VD1 = VD2 = 1 V, VG1 = VG2 = 0.62 V, and VG3 = 0.66 V. The total drain current was 21.4 mA, that is, the LNA only consumed 21.4 mW power, a relatively low value for a 60-GHz CMOS LNA.

inRF

D1V

G3V

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1C 1TL

G1R

2M

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2C

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15C

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RFin RFout

VG1 VG2 VG4 GND GND not used

GND

GND

GND

GND

VD1 VD1 VG3 VD2 GND GND

60 GHz 57-64 GHzSupply Voltage (V)Power Consumption (mW)S11 (dB) -19.5 -13 ~ -20.5S22 (dB) -19.53 -13.5 ~ -19.9S21 (dB) 15.1 11.9 ~ 15.9S12 (dB) -49.8 -49.8 ~ -53NF (dB) 7.6 7.6 ~ 8.5

126.7

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VD1 = VD2 = 1 V VD1 = VD2 = 1.2 V VD1 = VD2 = 1.6 V

52 54 56 58 60 62 64 660

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VD1 = VD2 = 1 V VD1 = VD2 = 1.2 V VD1 = VD2 = 1.6 V

52 54 56 58 60 62 64 66-60-55-50-45-40-35-30-25-20-15-10-50

S 12 (d

B)

Frequency (GHz)

VD1 = VD2 = 1 V VD1 = VD2 = 1.2 V VD1 = VD2 = 1.6 V

90

Fig. 7 The measured IIP3 of the LNA at 60 GHz.

Table III Summary of the measurement results in [9]-[10] and the 60-GHz CMOS LNA in this work.

Fig. 6(a) shows the measured S11 versus frequency characteristics of the CMOS LNA. S11 was smaller than –10 dB for frequencies ranging from 53.3 to 64.7 GHz, covering the 57-64-GHz-band of interest. Minimum S11 of –37.4 dB was achieved at 58.5 GHz. Since this LNA is intended for integrated front-end circuits, AV instead of S21 is reported here. Fig. 6(b) shows the measured AV versus frequency characteristics of the LNA. AV of 10.67-18.45 dB was achieved over the 57-64-GHz band of interest. Maximum AV of 18.76 dB was achieved at 58.5 GHz. Fig. 6(c) shows the S12 versus frequency characteristics of the CMOS LNA. S12 was smaller than –43.2 dB for frequencies ranging from 52 to 66 GHz, and smaller than –43.5 dB over the 57-64-GHz-band of interest. Minimum S12 of –53 dB was achieved at 54 GHz.

Fig. 7 shows the measured IIP3 of the CMOS LNA at 60 GHz. The corresponding IIP3 was −6.9 dBm. Table III is a summary of the measurement results of the CMOS LNAs in [9]-[10] and the CMOS LNA in this work. As can be seen, excellent S11 was achieved in this work. Besides, the power-consumption (21.4 mW) of our LNA was only 27% of that (79.2 mW) of the 56-GHz LNA in [9], and was only 39.6% of that (54 mW) of the 60-GHz LNA in [10]. The NF (8.2 dB) of our LNA was comparable to that (7.6 dB) of the

56-GHz LNA in [9], and that (8.8 dB) of the 60-GHz LNA in [10]. This NF result is acceptable since the top metal thickness of the CMOS technology adopted was 0.9 �m, only 27.3% of that (3.3 �m) of the CMOS technology in [9]. The simulation result shows NF better than 6.5 dB can be achieved if a thicker top metal layer of 3.3 �m is used. Moreover, the layout area (0.475 mm2) of our LNA was only 36.5% of that (1.3 mm2) of the 40 and 60 GHz CMOS LNAs in [9], and was comparable to the 56-GHz LNA in [10].

IV. CONCLUSION

In this work, we demonstrate a low-power (5.556 mW) and low-phase-noise (−105 dBc/Hz at 1 MHz offset) 48-GHz CMOS VCO and a low-power (21.4 mW) 60-GHz CMOS LNA for 60-GHz radio. Compared with the measured results of the reported CMOS VCOs around 48 GHz in this literature, our VCO exhibits the highest FOM. Nice results from this work show that our implemented VCO and LNA are suitable for high-performance 60-GHz-band or even higher frequency-band receiver front-end applications.

ACKNOWLEDGEMENT

This work is supported by the National Science Council of the R.O.C. under Contract NSC96-2212-E-260-001. The authors are very grateful for the support from CIC, Taiwan, for chip fabrication, and NDL, Taiwan, for measurements.

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[2] H. M. Wang, "A 50 GHz VCO in 0.25 �m CMOS," IEEE ISSCC, Tech. Dig, pp. 372 -373, Feb. 2001.

[3] T. N. Luo, S. Y. Bai, Y. J. E. Chen, H. S. Chen, D. Heo, "A 1-V CMOS VCO for 60-GHz applications," IEEE Asia-Pacific Microw. Conf., vol. 1, 2005, pp. 101-104.

[4] H. Shigematsu, T. Hirose, F. Brewer, and M. Rodwell, "Millimeter-wave CMOS design," IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 472-477, Feb. 2005.

[5] A. P. van der Wel, S. L. J. Gierkink, R. C. Frye, V. Boccuzzi, B. Nauta, "A Robust 43 GHz VCO in Standard CMOS for OC-768 SONET Applications," European Solid-State Circuits Conference, Tech. Dig., 16-18 pp.345-348, Sep. 2003.

[6] N. Fong, J. O. Plouchart, N. Zamdmer, L. Duixian, L. Wagner, P. Garry, and G. Tarr, "A 40 GHz VCO with 9 to 15% Tuning Range in 0.13 �m SOI CMOS," IEEE VLSI Symp., Digest of Technical Papers, pp.186-189, Jun. 2002.

[7] J. Kim, J. O. Plouchart, N. Zamdmer, R. Trzcinski, K. Wu, B. J. Gross, and M. Kim, "A 44GHz Differentially Tuned VCO with 4 GHz Tuning Range in 0.12 �m SOI CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech Papers, 2005, pp .416-417.

[8] F. Ellinger, T. Morf, G. Buren, C. Kromer, G. Sialm, L. Rodoni, M. Schmatz, and H. Jackel, "60 GHz VCO with Wideband Tuning Range Fabricated on VLSI SOI CMOS Technology," IEEE MTT-S IMS, Dig., vol. 3, pp.1329-1332, Jun. 2004.

[9] C. M. Lo, C. S. Lin, and H. Wang, "A miniature V-band 3-stage Cascode LNA in 0.13 �m CMOS," 2006 IEEE International Solid-State Circuits Conference, pp. 1254-1263.

[10] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Broderson, "Millimeter-Wave CMOS Design," IEEE Journal of Solid-State Circuits, vol. 40, pp. , no. 1, pp. 144-155, Jan. 2005.

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IIP3 = −6.9 dBm

Frequency: 60 GHz

56 GHzLNA [9]

60 GHzLNA [10]

40 GHzLNA [10]

S11 (dB) -19.8 -19.2 -19.9 -8.5 <-15 <-15 S21 (dB) 17.1* 20.3* 24.2* 24.7 12 19 S12 (dB) -46.4 -47.2 -46.8 -- <-45 <-50 NF (dB) 8.2 7.6 7.1 7.6 8.8 -- P1dB-in (dBm) -19 -22.3 -23 -22 -10 -18.1 IIP3 (dBm) -6.9 -11.1 -12.2 -12 -- -7.4 Supply Voltage (V) (CMOS Technology)

1(65 nm)

1.2(65 nm)

1.6(65 nm)

2.4(0.13 μm)

1.5(0.13 μm)

1.5(0.13 μm)

PowerConsumption (mW)

21.4 37.2 68.8 79.2 54 36

Chip Area (mm2) 0.48 1.3 1.3*Voltage Gain

60 GHz LNA(This Work)

0.475

91