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Abstract— In this paper, discrete-time full and reduced order anti-windup design for general linear cascade control systems under actuator saturation constraint is considered. Based on decoupled architecture with multi-loop compensation, 2 l gain reduction, discrete-time Block Diagonal Quadratic Lyapunov Function, and sector bounded-ness, LMI conditions are developed for full and reduced order anti-windup design which guarantees the stability and performance of overall closed-loop system. Results are demonstrated through a simulation example from process control. Index TermsLinear Matrix Inequalities (LMIs), Discrete- time Cascade Control Systems, Full and Reduced Order Anti- windup Compensator, 2 l gain, Multi-loop Compensation. I. INTRODUCTION CTUATOR saturation is one of the common nonlinearities often present in various control systems which can limit the performance of a closed-loop system with undesirable results like large overshoots, large settling time, lag and instability [1]. During the last decade, scientists, engineers and researchers had made wonderful efforts and struggles for developing anti-windup schemes in continuous [2-4] and discrete-time [5-9] domains and applied them to practical systems for the single loop non-cascade systems [10- 12]. It is proved for single loops systems that there is always an AWC existing for stable plants having order equal to the order of plant and called Full order AWC [4]. Some of these techniques are successfully implemented on highly practical problems of Hard Disk control [10], aircrafts [11] and AC motor speed control system [12]. As most of controllers are implemented in discrete-time domain, so various efforts are made for designing AWC in discrete-time domain using 2 l gain reduction and discrete-time Lyapunov stability [5-9]. But all these schemes [2-9] (both for continuous time and discrete-time) are usually developed for single loop non-cascade control systems. Such techniques can also be used for cascade control systems by using inner loop compensation or by making both cascade plants as single MIMO plant but the first one limit the performance while second one increases the order of AWC. Saturation present in the inner loop also affects the outer loop performance, so anti- windup scheme must be used in such a way that it compensates the affect of saturation in both inner and outer loops and order must not increase than the sum of order of both plants. This type of compensation is called Multi-loop or Cascade loop compensation. As in process industry, there are large numbers of cascade plants controlled by cascade controllers, so efforts are required to develop anti-windup schemes for cascade control systems. In this regard, this paper is an effort to provide a framework for designing AWC for cascade control systems with actuator saturation. We follow two step approach [3], [9] in which first unconstraint controller is designed and then an AWC is designed for performance improvement. Scheme is based on concept of decoupled architecture which has been presented for single loop systems in [2], [7-9]. The basic motivations are taken for working on discrete-time systems from [6], [7], [9] in which 2 l gain reduction based AWC are developed for single loop discrete-time systems. The work presented in this paper is based on stability of AWC by using discrete-time block diagonal quadratic Lyapunov function, performance improvement by using 2 l gain reduction, decoupled architecture with multi-loop compensation and sector bounded-ness. Besides from traditional discrete-time AWC schemes [5-9] when used for cascade control systems, our scheme uses block diagonal Lyapunov which divides the compensator into inner and outer compensators and they work independently from each other. Multi-loop compensation allows the canceling of saturation at each loop level. In our case, compensator order is equal to sum of order of both plants, while consideration of single complex loop by using non-cascade schemes makes the AWC order higher. Full order AWC is considered to be composed of co- prime factors of actual plants as in [9, 10 and 13]. While reduced order AWC is considered to be composed of co-prime factors of reduced order version of plants. LMI conditions are developed ensuring global stability and performance. Various aspects of proposed methodology are shown on a single simulation example. II. PROBLEM FORMULATION Suppose two linear stable cascade systems described by 1 1 () () () in d p G z G z G z = and 2 2 () () () out d p G z G z G z = . The Discrete-time full and reduced order anti- windup compensator synthesis for constraint cascade control systems: an LMI based approach Muhammad Rehan, Abrar Ahmed and Naeem Iqbal Department of Electrical Engineering, PIEAS [email protected], [email protected], [email protected] A 2009 International Conference on Emerging Technologies 978-1-4244-5632-1/09/$26.00 ©2009 IEEE 347

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Abstract— In this paper, discrete-time full and reduced order anti-windup design for general linear cascade control systems under actuator saturation constraint is considered. Based on decoupled architecture with multi-loop compensation, 2l gain

reduction, discrete-time Block Diagonal Quadratic Lyapunov Function, and sector bounded-ness, LMI conditions are developed for full and reduced order anti-windup design which guarantees the stability and performance of overall closed-loop system. Results are demonstrated through a simulation example from process control.

Index Terms— Linear Matrix Inequalities (LMIs), Discrete-time Cascade Control Systems, Full and Reduced Order Anti-windup Compensator, 2l gain, Multi-loop Compensation.

I. INTRODUCTION

CTUATOR saturation is one of the common nonlinearities often present in various control systems

which can limit the performance of a closed-loop system with undesirable results like large overshoots, large settling time, lag and instability [1]. During the last decade, scientists, engineers and researchers had made wonderful efforts and struggles for developing anti-windup schemes in continuous [2-4] and discrete-time [5-9] domains and applied them to practical systems for the single loop non-cascade systems [10-12]. It is proved for single loops systems that there is always an AWC existing for stable plants having order equal to the order of plant and called Full order AWC [4]. Some of these techniques are successfully implemented on highly practical problems of Hard Disk control [10], aircrafts [11] and AC motor speed control system [12].

As most of controllers are implemented in discrete-time domain, so various efforts are made for designing AWC in discrete-time domain using 2l gain reduction and discrete-time

Lyapunov stability [5-9]. But all these schemes [2-9] (both for continuous time and discrete-time) are usually developed for single loop non-cascade control systems. Such techniques can also be used for cascade control systems by using inner loop compensation or by making both cascade plants as single MIMO plant but the first one limit the performance while second one increases the order of AWC. Saturation present in the inner loop also affects the outer loop performance, so anti-windup scheme must be used in such a way that it compensates

the affect of saturation in both inner and outer loops and order must not increase than the sum of order of both plants. This type of compensation is called Multi-loop or Cascade loop compensation.

As in process industry, there are large numbers of cascade plants controlled by cascade controllers, so efforts are required to develop anti-windup schemes for cascade control systems. In this regard, this paper is an effort to provide a framework for designing AWC for cascade control systems with actuator saturation. We follow two step approach [3], [9] in which first unconstraint controller is designed and then an AWC is designed for performance improvement. Scheme is based on concept of decoupled architecture which has been presented for single loop systems in [2], [7-9]. The basic motivations are taken for working on discrete-time systems from [6], [7], [9] in which 2l gain reduction based AWC are developed for single

loop discrete-time systems. The work presented in this paper is based on stability of

AWC by using discrete-time block diagonal quadraticLyapunov function, performance improvement by using 2l

gain reduction, decoupled architecture with multi-loop compensation and sector bounded-ness. Besides from traditional discrete-time AWC schemes [5-9] when used for cascade control systems, our scheme uses block diagonal Lyapunov which divides the compensator into inner and outer compensators and they work independently from each other. Multi-loop compensation allows the canceling of saturation at each loop level. In our case, compensator order is equal to sum of order of both plants, while consideration of single complex loop by using non-cascade schemes makes the AWC order higher. Full order AWC is considered to be composed of co-prime factors of actual plants as in [9, 10 and 13]. While reduced order AWC is considered to be composed of co-prime factors of reduced order version of plants. LMI conditions are developed ensuring global stability and performance. Various aspects of proposed methodology are shown on a single simulation example.

II. PROBLEM FORMULATION

Suppose two linear stable cascade systems described by

1 1( ) ( ) ( )in d pG z G z G z⎡ ⎤= ⎣ ⎦ and 2 2( ) ( ) ( )out d pG z G z G z⎡ ⎤= ⎣ ⎦ . The

Discrete-time full and reduced order anti-windup compensator synthesis for constraint

cascade control systems: an LMI based approach

Muhammad Rehan, Abrar Ahmed and Naeem Iqbal Department of Electrical Engineering, PIEAS

[email protected], [email protected], [email protected]

A

2009 International Conference on Emerging Technologies

978-1-4244-5632-1/09/$26.00 ©2009 IEEE 347

state space representations for these plants can be written as follow.

1 1 1 1 1

1 11 1 1 1 1

( ) ~ , ( ) ~p p p p d

p dp p p p d

A B A BG z G z

C D C D

⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

(1)

2 2 2 2 2

2 22 2 2 2 2

( ) ~ , ( ) ~p p p p d

p dp p p p d

A B A BG z G z

C D C D

⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

(2)

Here ( )inG z is representation of inner plant with 1 ( )pG z as

plant model and 1( )dG z as disturbance model respectively.

Similarly ( )outG z is representation of outer plant with 2 ( )pG z

as plant model with 2 ( )dG z as disturbance. Suppose two

discrete-time controllers [ ]1 2( ) ( ) ( )in i iK z K z K z= and

[ ]1 2( ) ( ) ( )out o oK z K z K z= are given by the following state

space realizations.

11 1 2 11 11

1 211 1 2 11 11

( ) ~ , ( ) ~c c y c c

i ic c y c c

A B A BK z K z

C D C D

⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

(3)

2 2 2 2

1 22 2 2 2

( ) ~ , ( ) ~c c r c c

o oc c r c c

A B A BK z K z

C D C D

⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

(4)

The inner plant is supposed to have a saturation constraint as given by following relation.

1 1( ( )) [ ( ( )),..., ( ( ))]Tin in m inmsat u k sat u k sat u k= (5)

For any 0W > dead zone and saturation satisfy the following sector bounded-ness [13], [14].

( ( )) [ ( ) ( ( ))] 0Tin in inDz u k W u k Dz u k− ≥ (6)

( ( )) [ ( ) ( ( ))] 0Tin in insat u k W u k sat u k− ≥ (7)

Assumptions: (1) The plants ( )inG z and ( )outG z are asymptotically stable.

(2) Inner and outer loops without saturation constraints are considered to be well-posed. (3) Inner and outer unconstraint closed-loops are supposed to be stable having all poles in open unit disk

A. AWC Configuration

In case of discrete-time cascade control systems, if the inner plant ( )inG s has input saturation then it also affects the

performance of outer loop. So AWC scheme must be able to provide compensation in both inner and outer loops. The AWC configuration used for cascade control systems with actuator saturation is shown in Fig. 1. AWC takes the difference of saturation block input and output and it emits three signals du , 1dy , 2dy and which enter control signal and

outputs of both loops respectively. For full order AWC, 1M

and 2M are taken as a part of co-prime factors of discrete-time

plants 1( )pG z and 2 ( )pG z respectively.

r

2py( )inK z

1d 2d

( )outK z ( )inG z ( )outG z1py

2

1

( ( ) )ii

M z I=

−∑

1 1( ) ( )pG z M z2 2( ) ( )pG z M z

du

u%

linu

1dy2dy 1liny

2liny

inu

Fig. 1. Discrete-time Cascade Control System with conditioning using M1 and M2 which is used in order to cancel the windup affect of saturation

r

2py( )inK z

1d 2d

( )outK z ( )inG z ( )outG z1py

2

1

( )ii

M I=

−∑

1 1( ) ( )pG z M z 2 2( ) ( )pG z M z

duu%

linu1dy

2dy

1liny 2liny

Non Linear Loop Disturbance Filter I Disturbance Filter II

inu

Fig. 2. Equivalent of figure 2, Decoupling AWC into Non-linear loop and disturbance filters which separates the linear and non-linear parts.

348

Fig. 2 shows an equivalent decoupled architecture for the configuration shown in Fig. 1. Besides from [9], here we use two decoupled disturbance filter which works independently and filter the affect of non-linear system at each output level. Secondly the non-linear loop uses a sum of two terms each of which tries to negate the non-linear affect.

B. Problem Statement

Consider a cascade system described by (1) and (2) and controlled by unconstraint cascade controllers described by (3) and (4) having an actuator constraint of (5). Design a full (or reduced) order AWC having order equal to (or less than) the sum of order of 1 ( )pG z and 2 ( )pG z as shown in Fig. 1 and

improve the response of the overall closed-loop system.

III. MAIN RESULTS

A. Full order AWC Design

Co-prime factors of both plants can be described as 1 1

1 1 1 2 2 2( ) ( ) ( ), ( ) ( ) ( )p pG z N z M z G z N z M z− −= = (8)

1 1 1 11

11

1 1 1 1

( )~ 0

( )

p p p

p p p

A B F BM z I

FN z

C D F D

⎡ ⎤+−⎡ ⎤ ⎢ ⎥

⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎢ ⎥+⎣ ⎦

(9)

2 2 2 22

22

2 2 2 2

( )~ 0

( )

p p p

p p p

A B F BM z I

FN z

C D F D

⎡ ⎤+−⎡ ⎤ ⎢ ⎥

⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎢ ⎥+⎣ ⎦

(10)

1F and 2F must be chosen in such a way that 1 1 1p pA B F+ and

2 2 2p pA B F+ are Hurwitz. The state space representing of

AWC with state 1 2( ) x ( )TT T

p px k k⎡ ⎤⎣ ⎦ and input u% is given as

1 1 1 1

2 2 2 2

1 21

1 1 1 12

2 2 2 2

0

0

0~

0

0

p p p

p p pd

d

p p pd

p p p

A B F B

A B F Bu

F Fy

C D F Dy

C D F D

+⎡ ⎤⎢ ⎥

+⎡ ⎤ ⎢ ⎥⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥⎢ ⎥ +⎣ ⎦ ⎢ ⎥

⎢ ⎥+⎣ ⎦

(11)

While1 2

1 1

2 2

( ) ( )

( )

( )

d

d

d

u M z I M z I

y N z u

y N z

− + −⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥

=⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥⎣ ⎦ ⎣ ⎦

%

Lemma 1: Simultaneously stabilizing the systems of (9) and (10) in sense of Lyapunov, guarantees the stability of (11).

Proof: If a quadratic Lyapunov 1 1 1 1( ) ( ) ( )Tp pV k x k P x k= and

2 2 2 2( ) ( ) ( )Tp pV k x k P x k= are used to stabilize the state equation

of (9) and (10) respectively, then by connecting both quadratic Lyapunov functions, we get the following

1 11

2 22

( ) ( )0( )

( ) ( )0

T

p p

p p

x k x kPV k

x k x kP

⎡ ⎤ ⎡ ⎤⎡ ⎤= ⎢ ⎥ ⎢ ⎥⎢ ⎥

⎣ ⎦⎣ ⎦ ⎣ ⎦(12)

This discrete-time Lyapunov with block diagonal structure can be used to stabilize the system of (11). Lemma 2: The following objective function ensures the asymptotic stability, well-posedness and 2l gain of AWC from

( )linu k to 1 2( ) (k) ( )TT T

d d dy k y y k⎡ ⎤= ⎣ ⎦ less than γ .

2 221 ( ) ( ) ( ) 0d linJ V k y k u kγ= ∆ + − < (13)

Proof: The objective function, Lemma 2 and proof are similar to [9] and [13]. The difference is only the use of Block Diagonal

Lyapunov and ( )dy k as a vector equal to 1 2( ) ( )TT T

d dy k y k⎡ ⎤⎣ ⎦ .

We just give the summary of proof as follow.

1. When ( ) 0linu k = , then 2

( ) 0dy k ≥ and ( ) 0V k∆ <

guarantees asymptotic stability. 2. Summing (13) from 0 to ∞ shows that the 2l gain of

AWC from ( )linu k to 1 2( ) (k) ( )TT T

d d dy k y y k⎡ ⎤= ⎣ ⎦ is less

than γ .

3. As there is no direct feed-through from u% to

1 2d d du u u= + . So according to [13], there is no

algebraic loop which ensures well-posedness from signal ( )linu k to ( )dy k .

Theorem I: Consider two cascade systems described by (1) and (2) with cascade controllers for unconstraint system given by (3) and (4) having actuator saturation of (5). Full Order Discrete-time AWC can be found by solving the following problemMinimize γ

Subject to 1 0Q > , 2 0Q > , 0U > and diagonal, 0γ > and LMI

of Box I given at the end of page . Full Order AWC parameters 1F and 2F can be obtained by

solving 11 1 1F L Q−= and 1

2 2 2F L Q−= which further can be used to

find 1M , 1N , 2M and 2N by (9) and (10). AWC can be

implemented according to Fig. (1).

1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2

1 2 1 2

1

2

0 0 0 0

* 0 0 0

* * 2

* * * 0 0 0 00

* * * * 0 0 0

* * * * * 0 0

* * * * * * 0

* * * * * * *

T T T T T Tp p p p

T T T T T Tp p p p

T T T Tp p p p

Q L Q C L D Q A L B

Q L Q C L D Q A L B

U I UD UD UB UB

ILMIa

I

I

Q

Q

γ

γ

γ

⎡ ⎤− − + +⎢ ⎥

− − + +⎢ ⎥⎢ ⎥−⎢ ⎥

−⎢ ⎥= <⎢ ⎥−⎢ ⎥

−⎢ ⎥⎢ ⎥

−⎢ ⎥⎢ ⎥−⎣ ⎦

(Box I)

349

Proof: To avoid non-linear affects; it is required to stabilize the

system from ( )linu k to 1 2( ) (k) ( )TT T

d d dy k y y k⎡ ⎤= ⎣ ⎦ with minimum

2l gain and well-posedness. This is guaranteed by objective

function (13). By combining the objective function (13) with sector condition (6) by using S-procedure [14] with variableτ , we get the following objective function:

[ ]

221 2

2

1 2

( )( 1) ( ) ( )

( )( ) 0

2 ( ) ( ) ( ) ( )

dlin

d

Tlin d d

y kV k V k u k

y kJ k

u X u k u k u k u k

γ⎫⎧⎪⎪ + − + −⎪ ⎪

= <⎨ ⎬⎪ ⎪

+ − − −⎪ ⎪⎩ ⎭% %

(14)

Here X Wτ= . Putting the Lyapunov function of (12) for ( )V k

and ( 1)V k + , putting 1( )dy k and 2 ( )dy k from (11) and using

1 1 1( )d pu F x k= , 2 2 2 ( )d pu F x k= , we get

11 13

22 23

332

0 0

* 0( ) 0

* *

* * *

F F

F FT

F

V V

V VJ k z z

V W

⎡ ⎤⎢ ⎥⎢ ⎥= <⎢ ⎥⎢ ⎥

−⎣ ⎦

(15)

With 11 1 1 1 1 1 1T T

FV A P A P C C= − +

22 2 2 2 2 2 2T T

FV A P A P C C= − +

13 1 1 1 1 1 1T T T

F p pV A PB C D F X= + −

23 2 2 2 2 2 2T T T

F p pV A P B C D F X= + −

33 1 1 2 2 1 1 1 2 2 2 2T T T TF p p p p p p p pV D D D D B PB B P B X= + + + −

1 1 1 1p pA A B F= + , 1 1 1 1p pC C D F= + ,

2 2 2 2p pA A B F= + , 2 2 2 2p pC C D F= +

and

1 2(z) (z) (z) ( )TT T T T

p p linz x x u u z⎡ ⎤= ⎣ ⎦%

By applying Schur Complement and Congruence transform with 1 1 1

1 2( , , , , , , , )diag P P X I I I I I− − −− − (see [9], [13] and [14]), and

then using 11 1Q P−= , 1

2 2Q P−= , 1U X −= , 1 1 1L F Q= and

2 2 2L F Q= , we finally obtain LMI of Box I. Note that 1Q , 2Q

and U are positive definite as their inverses are positive definite.

B. Reduced order AWC Design

Let 1 ( )p rG z and 2 ( )p rG z are reduced order versions of

1 ( )pG z and 2 ( )pG z . Use state space of 1 ( )p rG z instead of

1( )pG z and state space of 2 ( )p rG z instead of 2 ( )pG z in

Theorem I and design a reduced order AWC. It is better to use reduced order plant for AWC design rather than reducing the order of full order AWC because first will at least give the minimum 2l gain while in second case, 2l gain will not remain

optimal. Although it may not always guarantee performance because the AWC designed in this case is basically for reduced order plants and not for full order plants. But if it is possible, (as most of the times seen in simulations) then it has two advantages. First no tuning weights are required as in low order AWC case of [9]. Secondly, this can be used as initial weights

for designing low order AWC (see [9] also). In this way, Full order AWC framework can be used for Low order AWC.

IV. SIMULATION EXAMPLE

Consider the cascade plants and controllers taken from [15] which is model of an industrial process and given below.

1

1

(2 1)(2 1)pGs s

=+ +

, 2

1

(10 1)(3 1)pGs s

=+ +

1

(2 1)(2 1)

4 (1 1)

s sK

s s

+ +=

+, 2

(10 1)(3 1)

10 (2.5 1)

s sK

s s

+ +=

+

Actuator saturation limits are taken as [-1 1]. Plants are discretized using zero-order-hold and controllers are discretized using bilinear approximation for sampling time of 0.1 second. The various parameters for full order and reduced order AWC obtained by solving using Theorem I for both are shown in Table I.

TABLE I FULL AND REDUCED ORDER AWC PARAMETERS

Sr. No.

AWC Type

AWC Parameters Obtained

optγ

1 Full Order1 [0.24 0.22]F = − ,

2 [0.28 0.27]F = − 1

2 Reduced Order

1 0.1989F = ,

2 0.1109F =1.2

Responses due to full order are compared with unconstraint and constraint responses and shown in Fig. 3. Response of reduced order AWC is not shown because it is almost same as response of Full order AWC.

0 200 400 600 800 1000

-1

-0.5

0

0.5

1

1.5

Time

Out

put

Unconstraint response

Constraint responseFull Order AWC response

Refrence Signal

Fig. 3. Full Order AWC response with sampling-time of 0.1 sec.

It is seen that constraint response has a lag for 200 to 260 seconds of time and then goes out of control for 270 to 550 seconds while full order AWC responses is following the reference and closed to unconstraint response.

V. CONCLUSION

In this paper, a framework is provided for full and reduced order discrete-time anti-windup compensator design for cascade control systems with actuator constraints using LMI which can

350

be used for industrial applications. The developed AWC schemes are based on the fact that the compensation for discrete-time cascade control systems must be made in each primary and secondary loop and it must guarantee the stability and performance of overall closed-loop system. For this purpose, a discrete-time Lyapunov with block diagonal structure is used which divides the compensator into inner and outer discrete-time compensators. LMI conditions are developed which guarantee the asymptotic stability and performance for overall closed-loop system. AWC order is lower than the conventional discrete-time AWC schemes when applied to cascade control systems. This contribution can open further avenues for scientists and engineers towards solving industrial cascade control problems with actuator saturation constraint using AWC.

ACKNOWLEDGEMENT

The authors owe a debt of gratitude to Dr. Ian Postlethwaite and Dr. Matthew C. Turner of University of Leicester and Dr. Guido Herrmann of University of Bristol for their insight on the design of AWC. Thanks to Dr. Guido Herrmann for emailing some useful material on discrete-time AWC design.

REFERENCES

[1]. J.-K. Park and C.-H. Chois, “Dynamical anti-reset windup method for discrete-time saturating systems,” Automatica, vol. 33. No. 6, pp. 1055-1072, 1997.

[2]. P. F. Weston and I. Postlethwaite, “Linear conditioning for systems containing saturating actuators,” Automatica, vol. 36, pp. 1347-1354, 2000.

[3]. M. C. Turner and I. Postlethwaite, “A new prespective on static and low order anti-windup synthesis,” International Journal of Control, vol. 77, no. 1, pp. 27-44, 2004.

[4]. G. Grimm, J. Hatfield and I. Postlethwaite, A. R. Teel, M. C. Turner, and Luca Zaccarian, “Antiwindup for stable linear systems with Input Saturation: An LMI-Based Synthesis,” IEEE Transactions on Automatic Control, vol. 48, no. 9, pp.1509-1525, 2003.

[5]. J.M. Gomes da Silva Jr. and S. Tarbouriech, “Anti-windup design with guaranteed regions of stability for discrete-time linear systems,” Systems & Control Letters, vol. 55, pp. 184-192, 2006.

[6]. Gene Grimm, Andrew R. Teel and Luca Zaccarian, “The l2 anti-windup problem for discrete-time linear systems: Definition and Solutions,” Systems & Control Letters, vol. 57, pp. 356-364, 2008.

[7]. M. C. Turner, G. Herrmann, and I. Postlethwaite, “Discrete-time anti-windup: Part1 - stability and performance,” Proceedings of the European Control Conference, Cambridge, UK, 2003.

[8]. G. Herrmann, M. C. Turner, and I. Postlethwaite, “Discrete-time anti-windup: Part2 – extension to sample data case,” In Proceedings of the European Control Conference, Cambridge, UK, 2003.

[9]. G. Herrmann, M. C. Turner, and I. Postlethwaite. “Discrete-time and sampled data antiwindup synthesis: stability and performance,” International Journal of Systems Science, vol. 37, no. 2, pp. 91–113, 2006.

[10]. G. Herrmann, Matthew C. Turner, I. Postlethwaite and G. Guo “Practical implementation of a novel anti-windup scheme in a HDD-Dual-Stage servo system,” IEEE Transactions on Mechatronics, vol. 9, no. 3, pp.580-592, 2004.

[11]. O. Brieger, M. Kerr, D. Leibling, I. Postlethwaite, J. Sofrony and M.C. Turner, “Flight testing of a rate saturation compensation scheme on the ATTAS aircraft,” Aerospace Science and Technology, accepted in press, (2008).

[12]. M. Rehan, A. Ahmed, N. Iqbal and M. S. Nazir, “Experimental comparison of different anti-windup schemes for an AC motor speed control system,” Accepted in IEEE / ICET, Islamabad, 2009.

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