A Novel, Low-Cost Deep Trench Decoupling Capacitor

for High-Performance, Low-Power Bulk CMOS Applications

Chengwen Pei*, Roger Booth, Herbert Ho, Naoyoshi Kusaba, Xi Li, MaryJane Brodsky, Paul Parries,Huiling Shang, Rama Divakaruni, and Subramanian Iyer

IBM Semiconductor Research & Development Center, 2070 Route 52, Hopewell Junction, NY 12533, USA

*Email: piecl@us.ibm.com

Abstract

We present an overview and electrical resultsfor a novel deep trench decoupling capacitor.The process of this decoupling capacitor borrowsfrom the regular embedded DRAM trenchprocess, but with significant processsimplification for decoupling use which providereduced cost and reduced process cycle time.This capacitor can provide significant chip-levelarea savings, using only 1/8 silicon real estate tofabricate the same capacitance as standard planargate oxide capacitors. Additionally, the trenchdecap demonstrates a dramatic improvement inleakage compared to standard planar gate oxidecapacitors - as much as 105 improvement inleakage can be realized using trench decapsinstead of conventional planar decap designs.

IntroductionOne unfortunate feature of wIfing and

packaging of semiconductor chips is inductance.Switching of current produces L(di/dt) noise onthe power supply (Vdd) which can havedetrimental impact on circuit performance.Decoupling capacitors - commonly referred to as"decaps" - reduce the magnitude of this inducednoise by providing a low impedance path toground. Decoupling is an important part of chipperformance, and as clock speeds increase, sodoes the need for effective decoupling. Decapsare commonly planar oxide devices using, forexample, an Nwell as one plate and a gate as thesecond plate. However, planar decaps mayexacerbate across chip linewidth variations(ACLV) if there is a high density of decapsembedded in the design. Moreover, gatedielectric leakage limits the amount of chargethat one can obtain from planar decaps and areoften found to contribute to standby leakage. Thefact that decaps can account for more than 10%

978-1-4244-2186-2/08/$25.00 ©2008 IEEE

of the total chip area of some designs, though,speaks to the importance of this feature of high­speed circuit designs.

We report here a novel decap design whichutilizes IBM's unique eDRAM trench technology[1-6] and which we call "DZ decaps". The DZdecap is presently being implemented in 2 bulktechnology nodes in IBM manufacturing - 90 nm(9SF) & 65 run (IOSF). DZ decaps offer IBMcustomers extremely high capacitance/area, verylow leakage/tF, and series resistancescompetitive with planar gate oxide decaps.

Process Comparison of DZ Capacitors vs. DTCapacitors

DZ trench capacitors are fabricated in asimilar manner to bulk eDRAM deep trench(DT) capacitors - only simpler. Figure 1 & 2 are

Figure 1 - Cross section (after MI) and topview(before CA) ofDZ Capacitor array

xSEM views of a DZ capacitor and DT capacitor.DZ & DT capacitors share exactly the same - (a)pad films, (b) oxide hardmask used for trenchdefinition, (c) lithography process, (d) buriedplate process (i.e. outer electrode formation), and

Figure 2 - Cross section of OT Capacitor (withWord Line and Passing Word Line on top)

(e) node dielectric formation process. However,after the node dielectric process, finishing off theOZ capacitor module is much simpler than a OTcapacitor. ForOZ, there is no need for a resistrecess and collar oxide formation (whichprevents a vertical parasitic device from turningon in a trench eORAM cell). Thus, the full,vertical OZ trench surface can be used for thedecoupling capacitor. In addition, the number ofpolyfills and poly recesses are reduced for theOZ decap. The OZ decap is ideally filled andrecessed only once; for the 9SF-eORAM trench,three polyfills and three recesses are necessary.Because the collar oxide is eliminated, and twopolyfills and two recesses are also eliminatedfrom the capacitor process, the OZ decap savesapproximately 350/0 in process cost and in rawprocess time (RPT) to that of an eORAM OTcapacitor. The OZ process has been qualified inthe 90 nm and 65 nm bulk logic technologies,demonstrated in the 45nm bulk logic technologyand has not shown to cause degradation of logiccircuit performance.

Device design

From a design perspective, the OZ decapmacro is formed by drawing an array of squaresin the OZ design level with two active areacontacts. One contact lands in the middle of theOZ square and one contact above the bulksubstrate in an Nwell (see Figure 3). To ensurelow series resistance, the OZ contact lands on asilicided trench top. The Nwell is the standardbulk POR well and is used to ensure that all OZburied plates are connected. The capacitorsforming the array are wired in parallel on the 1stmetal level which means that the ensemble ofcapacitors exhibit far lower series resistance thanwould a single trench.

n+~""­burledplate

Figure3: Schematic cross section of OZ capacitor

Electrical Results of DZ Decaps

Figure 4 shows a CV curve of a OZ capacitorbuilt in a 45 degree substrate with 6853 trenches(an array of 77 trenches in X and 89 trenches inV), measured at 50 Hz, 1kHz, and IMHz. Thenegative bias voltage region of the curve showsthe buried plate in depletion. The positivevoltage shows the trench poly in depletion. Thepeak of the curve at IV positive bias correspondsto approximately 310pF at IMHz. This meanswe are measuring about 45fF per trench with thisprocess.

50Hz

25e-10

2.0..-10 L...........-_--L-__--'--__-L.-_----'.... 00 -2 00 0 2 00

v ... ·

Figure 4: C-V curve of an IILP OZ capacitorwith approximately 6800 trenches, measured at 3different frequencies (as notes on graph)

Figure 5 shows an IV curve of the samecapacitor shown in Figure 4. The leakageobserved is very low for a 340pF capacitor with6853 trenches - on the order of I fA per trench.This is similar to the leakage level observed in10SF eORAM "OT" trenches, which use anidentical buried plate, dielectric, and trench fillprocess.

1 0e-8'5 OE>-.g

10e-9'5 0e-10

~ ~ g:~~~

i ~ ~=~;i 10e-12:! Eo 09-13

109-135 0e-14

1 0...-14

'5 0.-1: L.-oo--.....&......------L..-~--=-"=_=__--:-'Figure 5: I-V curve of an IILP DZ capacitorwith approximately 6800 trenches

One DZ process step that can be simplifiedeven further is the buried plate process. Thecurrently-practiced buried plate process consistsof: (a) depositing an ASG film, (b) depositing acap TEOS layer, (c) outdiffusing the As fromASG into the Si substrate using a high­temperature furnace anneal, and (d) stripping theASG and cap TEOS layer. This processeffectively forms the outer electrode of thetrench decoupling capacitor. We haveexperimented with replacing the ASG plateprocess with a simple high-dose, N+ implantplate process using As or P. This implant isconducted immediately after the trench has beenetched into the Si and uses the oxide hardmaskas a shield so that the implant is blocked frompenetrating the pad SiN film. By substituting animplant process for the ASG process, there isadditional 6% cost savings and 18% process timesavings.

clearly indicated in Figure 7, capacitorsfabricated with implanted plate process (right 6wafers) can achieve very compatible capacitanceas conventional ASG process does (two wafersin left side), but with much less processcomplexity and reduced cost.

In experiments we have also found that athigh frequency - such as 1MHz - a DZ arraywith large number of trenches shows lesscapacitance per trench than smaller array (seeFigure 7). This observation can be explained bythe parasitic resistance from wire in the DZ arraymacro. An array with a large number of trencheshas much larger wire resistance in series. Theother components of parasitic resistance - causedby trench N+ poly and Nwell sheet resistances ­are actually lower since these components arewired in parallel. An equivalent circuit model ofthe DZ trench array is in Figure 8. The total

2 0e-10

10e-10

The behavior of the capacitor with the trenchpoly in depletion is not strongly affected. As is

Figure 7: DZ capacitance per trench measured atfrequency of 1MHz from DZ array macros with7K, 120K, 470K and 1M trenches.

Figure 6: Comparison of ASG out-diffusedburied plate (blue curve) to implanted buriedplate (black).

Figure 8, Equivalent circuit of DZ capacitor withsmall (left) and larger array.

parasitic resistance of a DZ capacitor iscompetitive with a planar gate-oxide capacitor.For example, one typical nfet-in-nwell capacitorthat is being offered has layout dimensions of20um x 4um x 21 fingers. This has a capacitanceof approximately 25pF and a series resistance ofapproximately 50hms as extracted fromhardware. An equivalent array of DZ trencheswould have 700 trenches, occupy approximately1/8th the area, and have a series resistance ofapproximately 7 ohms. However, there is adistributed nature to the capacitance of the deeptrench, so in practice the capacitor behaves asthough it had less series resistance than thecalculation predicts.--Capacitance(IF/um2) 120 < IS*

Leakage(pAlum2) -8.02 1400

Leakage (pAlfF) < 0.001 - 90

oVh'

OL..--__...L.--__--'--__----l-__---'

-400

I 7K DZ array macro It { t -- t ----~t - i ---t- ------1

POR : Implanted plate 120K DZ array macr1

--+~~---~ ~ --+-- + ~

: . -.-47~~::::;,::;:jI i I I

I)

Figure 6 shows a comparison of anexperimental implanted plate process to the ASGout-diffused process. As can be seen from thefigure, the early implanted plate process haslower doping in the buried plate, resulting inlower capacitance when the plate is in depletion.

I-ozcap I-GateOxCap

1.00E-01 1.00E+OO 1.00E+01 1.00E+02

Freq(GHz)

1.00E-01 +--_-+-_-+-_--+----L..-_1.00E-02

1.00E+OO -l----+----I---\---+--+----

i100E~1 +-----+------P.--~+-----

1.00E+03~-~-~-~--

1.00E+02 -l-----I--~--I--------+---

compact model simulations for a DZ capacitoroccupying the same area as a 23pF gate oxidecapacitor. It suggests, even at GHz frequency orhigher, a DZ cap with the same area can providemore than 5X capacitance than a planar oxidecapacitor does.

Fig. 9B, DZ Cap compared to Gate Oxide capfor a fixed area

Comparison of DZ Caps to Planar Gate OxideCaps

Table II shows a comparison of the DZCapacitor to that of a typical planar gate-oxidecapacitor (in this case, a nfet-in-nwell capacitorusing an IsA gate oxide). A DZ capacitordesign would only need I/Sth chip area to providethe same capacitance since the DZ capacitor is avertical device compared to the typical planargate-oxide capacitor. In addition, leakage fromDZ capacitor arrays is nearly 5 orders lower thanthat of a typical planar gate-oxide capacitor ­this is largely the result of the thicker SiNdielectric (,,-,43A) used for DZ decaps. Thedielectric used for planar capacitors is restrictedby the gate oxide that is offered in the particularprocess technology. Thus, a planar gate oxide

Table II: Comparison of DZ capacitor to 11 LPSGNCAP

e:J......•...............~ ..-G*()ICap

-e-~

G:' 1.0CE-.Q1a

11~~~

1.CJE.01 .J---~--~--+---l~"---l1 0(E.(I2' 1 ()(E{)1 1.f.IE+(D 1 tKE+01 1 CllE--a2

f .... fGHE)

Fig. 9A, DZ Cap model (blue curve) andhardware results (squares) compared to GateOxide cap (pink curve) for a fixed capacitance

capacitor cannot provide the high decouplingcapacitance and low leakage as the DZ decapdoes. Figure9A shows a comparison of compactmodel simulations for a thin gate oxide capacitorcompared to aDZ capacitor of the samecapacitance (about 23pF). As can be seen fromthe simulation, the DZ capacitor at a similarcapacitance has similar high frequency behaviorto the gate oxide capacitor, but occupys onlyl/Sth the area. The hardware results (squares inFigure 9A) are perfectly close to the model ofDZ decap. Figure 9B shows a comparison of

Conclusion

We have described a novel decoupling decapdesign that utlizes the attributes of IBM'seDRAM trench technology. Results indicate thatDZ decaps can offer more than SX morecapacitance/unit area and 105 reduction inleakage than planar decaps. The area/leakageefficiencies intrinsic to DZ caps allow forimproved flexibility in present high-performanceand future low-power CMOS designs.

References[1] 1. Barth et aI., "A 500MHz Random Cycle,I.5ns-Iatency, SOl Embedded DRAM MacroFeaturing a 3T Micro Sense Amplifier,"ISSCC'07[2] G. Wang et aI., "A 0.127um2 HighPerformance 65nm SOl Based EmbeddedDRAM for on-Processor Applications." IEDM'06[3] T. Kirihata et aI., "An SOOMHz EmbeddedDRAM with a Concurrent Refresh Mode."ISSCC'04[4] R. Matick and S. Chuster, "Logic-basedeDRAM: Origins and Rationale for use,"IBMJRD, Jan. '05[5] S. Iyer et aI., "Embedded DRAM:Technology Platform for the BlueGene/LChip,"IBM JRD, March-May '05[6] S. Iyer and H. Kalter, "Embedded DRAMTechnology: Opportunities andChallenges,"IEEE Spectrum, 4/99