ieee 10/100/1000m ethernet/ pon network bridge...

RTL9601B-CG

IEEE 10/100/1000M ETHERNET/ PON NETWORK BRIDGE PROCESSOR

PRELIMINARY DATASHEET (CONFIDENTIAL: Development Partners Only)

Rev. 0.1

08 May 2014

Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan

Tel.: +886-3-578-0211. Fax: +886-3-577-6047

www.realtek.com

wei_zhao

Not For Public Release

RTL9601B

Preliminary Datasheet

IEEE 10/100/1000M Ethernet/PON Network Bridge Processor ii Rev. 0.1

COPYRIGHT

©2014 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,

transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements

and/or changes in this document or in the product described in this document at any time. This document

could include technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document

are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document provides detailed user guidelines to achieve the best performance when implementing the

Realtek Ethernet/PON network bridge processor.

Though every effort has been made to ensure that this document is current and accurate, more information

may have become available subsequent to the production of this guide.

REVISION HISTORY Revision Release Date Summary

0.1 2014/05/08 Preliminary release.

RTL9601B


IEEE 10/100/1000M Ethernet/PON Network Bridge Processor iii Rev. 0.1

Table of Contents

1. GENERAL DESCRIPTION .............................................................................................................................................. 1

2. FEATURES ......................................................................................................................................................................... 2

3. SYSTEM APPLICATIONS ............................................................................................................................................... 5

3.1. ONT IN SFU APPLICATION ........................................................................................................................................... 5 3.2. STICK ONU IN SFP TRANSCEIVER MODULE ................................................................................................................. 6

4. BLOCK DIAGRAM ........................................................................................................................................................... 7

5. PIN ASSIGNMENTS ......................................................................................................................................................... 8

5.1. PACKAGE IDENTIFICATION ........................................................................................................................................... 8 5.2. PIN ASSIGNMENTS TABLE ............................................................................................................................................ 9

6. PIN DESCRIPTIONS....................................................................................................................................................... 11

6.1. GBE PHY MEDIA CONNECTION PINS ........................................................................................................................ 11 6.2. LAN PORT SERDES INTERFACE PINS ......................................................................................................................... 11 6.3. PON PORT INTERFACE PINS ....................................................................................................................................... 11 6.4. GPIO PINS ................................................................................................................................................................. 12 6.5. I2C PINS..................................................................................................................................................................... 14 6.6. EJTAG PINS .............................................................................................................................................................. 14 6.7. LED PINS ................................................................................................................................................................... 15 6.8. EMBEDDED SWITCH REGULATOR PINS ...................................................................................................................... 15 6.9. UART PINS ................................................................................................................................................................ 15 6.10. SPI FLASH INTERFACE PINS ..................................................................................................................................... 16 6.11. CONFIGURATION PINS ................................................................................................................................................ 16 6.12. MISCELLANEOUS PINS ............................................................................................................................................... 17 6.13. RAM INTERFACE PINS ............................................................................................................................................... 18 6.14. POWER AND GROUND PINS ........................................................................................................................................ 18

7. INTERFACE FUNCTIONAL OVERVIEW .................................................................................................................. 19

7.1. GIGA PHY MDI INTERFACE ...................................................................................................................................... 19 7.1.1. 1000Base-T Transmit Function ............................................................................................................................ 19 7.1.2. 1000Base-T Receive Function .............................................................................................................................. 19 7.1.3. 100Base-TX Transmit Function............................................................................................................................ 19 7.1.4. 100Base-TX Receive Function.............................................................................................................................. 19 7.1.5. 10Base-T Transmit Function ................................................................................................................................ 20 7.1.6. 10Base-T Receive Function .................................................................................................................................. 20 7.1.7. Auto-Negotiation for UTP .................................................................................................................................... 20 7.1.8. Crossover Detection and Auto Correction ........................................................................................................... 20 7.1.9. Polarity Correction .............................................................................................................................................. 20

7.2. PON INTERFACE ........................................................................................................................................................ 22 7.2.1. PON SerDes Interface .......................................................................................................................................... 22 7.2.2. BEN ...................................................................................................................................................................... 24

7.3. LAN SERDES INTERFACE .......................................................................................................................................... 25 7.4. MASTER I2C INTERFACE ............................................................................................................................................ 25 7.5. SLAVE I2C INTERFACE ............................................................................................................................................... 26 7.6. SPI (SERIAL PERIPHERAL INTERFACE) ....................................................................................................................... 27 7.7. EJTAG ...................................................................................................................................................................... 28 7.8. UART ........................................................................................................................................................................ 29 7.9. LED INDICATOR ........................................................................................................................................................ 29

RTL9601B


IEEE 10/100/1000M Ethernet/PON Network Bridge Processor iv Rev. 0.1

8. GENERAL FUNCTION DESCRIPTION ...................................................................................................................... 31

8.1. POWER ON SEQUENCE ................................................................................................................................................ 31 8.2. RESET ........................................................................................................................................................................ 32

8.2.1. Hardware Reset .................................................................................................................................................... 32 8.2.2. Software Reset ...................................................................................................................................................... 33

8.3. CLOCK CIRCUIT ......................................................................................................................................................... 33 8.4. REGULATOR ............................................................................................................................................................... 33 8.5. PON ........................................................................................................................................................................... 34

8.5.1. GPON ................................................................................................................................................................... 34 8.5.2. EPON ................................................................................................................................................................... 34

8.6. REALTEK PROCESSOR ................................................................................................................................................ 35 8.7. MEMORY CONTROLLER ............................................................................................................................................. 35 8.8. IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................ 35 8.9. HALF DUPLEX FLOW CONTROL ................................................................................................................................. 35

8.9.1. Back-Pressure Mode ............................................................................................................................................ 36 8.10. SEARCH AND LEARNING ............................................................................................................................................ 36 8.11. SVL AND IVL/SVL ................................................................................................................................................... 37 8.12. ILLEGAL FRAME FILTERING ....................................................................................................................................... 37 8.13. IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL ............................................................................. 38 8.14. BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL ..................................................................................... 39 8.15. PORT SECURITY FUNCTION ........................................................................................................................................ 39 8.16. MIB COUNTERS ......................................................................................................................................................... 39 8.17. VLAN FUNCTION ...................................................................................................................................................... 39

8.17.1. Port-Based VLAN ............................................................................................................................................ 40 8.17.2. IEEE 802.1Q Tag-Based VLAN ....................................................................................................................... 40 8.17.3. Protocol-Based VLAN ..................................................................................................................................... 41 8.17.4. Port VID .......................................................................................................................................................... 41

8.18. QOS FUNCTION .......................................................................................................................................................... 42 8.18.1. Input Bandwidth Control ................................................................................................................................. 42 8.18.2. Priority Assignment ......................................................................................................................................... 42 8.18.3. Priority Queue Scheduling............................................................................................................................... 42 8.18.4. IEEE 802.1p/Q and DSCP Remarking ............................................................................................................ 43 8.18.5. ACL-Based Priority ......................................................................................................................................... 43

8.19. CLASSIFICATION ........................................................................................................................................................ 44 8.20. GREEN ETHERNET ...................................................................................................................................................... 44

8.20.1. Link-On and Cable Length Power Saving ....................................................................................................... 44 8.20.2. Link-Down Power Saving ................................................................................................................................ 44

8.21. IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ............................................................................... 45

9. DC SPECIFICATIONS .................................................................................................................................................... 46

9.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 46 9.2. OPERATING CONDITIONS ........................................................................................................................................... 46 9.3. TOTAL POWER CONSUMPTION ................................................................................................................................... 47 9.4. DC PARAMETERS ....................................................................................................................................................... 47 9.5. SWITCH REGULATOR ................................................................................................................................................. 47

10. AC SPECIFICATIONS .................................................................................................................................................... 48

10.1. SPI INTERFACE TIMING .............................................................................................................................................. 48 10.2. JTAG BOUNDARY SCAN ............................................................................................................................................ 49 10.3. I2C MASTER INTERFACE TIMING ............................................................................................................................... 50 10.4. I2C SLAVE INTERFACE TIMING .................................................................................................................................. 50 10.5. 1000BASE-X/SGMII ELECTRICAL CHARACTERISTICS ............................................................................................. 51 10.6. ONU SERDES ELECTRICAL CHARACTERISTICS ......................................................................................................... 52

11. THERMAL CHARACTERISTICS ................................................................................................................................ 53

RTL9601B


IEEE 10/100/1000M Ethernet/PON Network Bridge Processor v Rev. 0.1

12. MECHANICAL DIMENSIONS...................................................................................................................................... 54

13. ORDERING INFORMATION ........................................................................................................................................ 55

RTL9601B


IEEE 10/100/1000M Ethernet/PON Network Bridge Processor vi Rev. 0.1

List of Tables TABLE 1. PIN ASSIGNMENTS TABLE ............................................................................................................................................. 9 TABLE 2. GBE PHY MEDIA CONNECTION PINS ......................................................................................................................... 11 TABLE 3. LAN PORT SERDES INTERFACE PINS .......................................................................................................................... 11 TABLE 4. PON PORT INTERFACE PINS ........................................................................................................................................ 11 TABLE 5. GPIO PINS ................................................................................................................................................................... 12 TABLE 6. I2C PINS ...................................................................................................................................................................... 14 TABLE 7. EJTAG PINS ................................................................................................................................................................ 14 TABLE 8. LED PINS .................................................................................................................................................................... 15 TABLE 9. EMBEDDED SWITCH REGULATOR PINS ........................................................................................................................ 15 TABLE 10. UART PINS ............................................................................................................................................................... 15 TABLE 11. SPI FLASH INTERFACE PINS .................................................................................................................................... 16 TABLE 12. CONFIGURATION PINS ............................................................................................................................................... 16 TABLE 13. MISCELLANEOUS PINS ............................................................................................................................................... 17 TABLE 14. RAM INTERFACE PINS .............................................................................................................................................. 18 TABLE 15. POWER AND GROUND PINS ........................................................................................................................................ 18 TABLE 16. MEDIA DEPENDENT INTERFACE PIN MAPPING .......................................................................................................... 20 TABLE 17. EJTAG INTERFACE PINS ........................................................................................................................................... 28 TABLE 18. UART CONTROL INTERFACE PINS ............................................................................................................................ 29 TABLE 19. LED BASIC ELEMENTS .............................................................................................................................................. 29 TABLE 20. CRYSTAL AND OSCILLATOR REQUIREMENTS ............................................................................................................ 33 TABLE 21. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE ....................................................................................... 38 TABLE 22. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 46 TABLE 23. OPERATING CONDITIONS ........................................................................................................................................... 46 TABLE 24. DC PARAMETERS ...................................................................................................................................................... 47 TABLE 25. SWITCH REGULATOR ................................................................................................................................................. 47 TABLE 26. SPI FLASH INTERFACE TIMING .................................................................................................................................. 48 TABLE 27. JTAG BOUNDARY SCAN INTERFACE TIMING VALUES .............................................................................................. 49 TABLE 28. I2C MASTER MODE TIMING VALUES ........................................................................................................................ 50 TABLE 29. I2C SLAVE MODE TIMING VALUES ........................................................................................................................... 50 TABLE 30. 1000BASE-X TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................. 51 TABLE 31. SGMII TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................................................ 51 TABLE 32. 1000BASE-X/SGMII RECEIVER ELECTRICAL CHARACTERISTICS ............................................................................ 51 TABLE 33. ONU SERDES TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................. 52 TABLE 34. ONU SERDES RECEIVER ELECTRICAL CHARACTERISTICS ........................................................................................ 52 TABLE 35. ORDERING INFORMATION .......................................................................................................................................... 55

RTL9601B


IEEE 10/100/1000M Ethernet/PON Network Bridge Processor vii Rev. 0.1

List of Figures FIGURE 1. ONT IN SFU APPLICATION .......................................................................................................................................... 5 FIGURE 2. STICK ONU IN SFP TRANSCEIVER MODULE ................................................................................................................ 6 FIGURE 3. BLOCK DIAGRAM ......................................................................................................................................................... 7 FIGURE 4. PIN ASSIGNMENTS ........................................................................................................................................................ 8 FIGURE 5. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION .................................................................................................. 21 FIGURE 6. PON SERDES RX CML MODE ................................................................................................................................... 22 FIGURE 7. PON SERDES TX CML MODE ................................................................................................................................... 22 FIGURE 8. PON SERDES TX LVPECL MODE0........................................................................................................................... 23 FIGURE 9. PON SERDES TX LVPECL MODE1........................................................................................................................... 23 FIGURE 10. SINGLE-ENDED BENP HIGH ACTIVE ........................................................................................................................ 24 FIGURE 11. SINGLE-ENDED BENN LOW ACTIVE ........................................................................................................................ 24 FIGURE 12. 1000BASE-X AND SGMII SIGNAL DIAGRAM ......................................................................................................... 25 FIGURE 13. I2C MASTER ACCESS SEQUENCE ............................................................................................................................. 25 FIGURE 14. I2C SLAVE 8BIT ADDRESS STANDARD MODE ACCESS SEQUENCE ........................................................................... 26 FIGURE 15. SPI INTERFACE DIAGRAM ........................................................................................................................................ 27 FIGURE 16. EJTAG USING A 5-SIGNAL JTAG INTERFACE TO ACCESS DATA BLOCK ................................................................. 28 FIGURE 17. PULL-UP AND PULL-DOWN OF LED PINS FOR LED ................................................................................................. 30 FIGURE 18. POWER ON SEQUENCE ............................................................................................................................................. 32 FIGURE 19. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART ............................................................................... 41 FIGURE 20. RTL9601B MAX-MIN SCHEDULING DIAGRAM ...................................................................................................... 43 FIGURE 21. SPI FLASH INTERFACE TIMING ................................................................................................................................ 48 FIGURE 22. BOUNDARY-SCAN GENERAL AND RESET TIMING .................................................................................................... 49 FIGURE 23. I2C MASTER MODE TIMING ..................................................................................................................................... 50 FIGURE 24. I2C SLAVE MODE TIMING ........................................................................................................................................ 50

RTL9601B


IEEE 10/100/1000M Ethernet/PON Network Bridge Processor 1 Rev. 0.1

1. General Description

The RTL9601B is a new generation Ethernet/PON network bridge processor, designed to facilitate the

realization of more cost effective optical network terminals (ONTs) in Single Family Unit (SFU)

application. With the small package and the RBOM(Rest of Bill of Materials) saving design, the

RTL9601B is suitable for the implementation of the stick ONU in SFP transceiver module.

The RTL9601B delivers a universal PON MAC and a high-performance SerDes to support both GPON

and EPON application. Other features include a powerful RealTek application CPU, an embedded RAM

as packet buffer and the program and data memory for the CPU, a SerDes for the 1000BASE-X/SGMII

interface or a Gigabit Ethernet physical layer transceiver with Energy Efficient Ethernet supported for the

network interface of residential side.

For peripheral interfaces, the RTL9601B has six hardware timers and one watchdog timer to provide

accurate timing and watchdog functionalities. The RTL9601B also supports one 16550-compatible

UART, a standard 5-signal P1149.1 compliant EJTAG test interface for CPU testing and software

development, and has up to 18 GPIO pins for extension and flexibility.

With integration and high performance, the RTL9601B supports high Quality of Service (QoS). Via table

configuration and look-up, the RTL9601B can perform hard-wired network traffic forwarding. The

Realtek application CPU at 550MHz speed can be used to handle upper layer functions, such as DHCP,

HTTP, and some other protocols.

The RTL9601B features an embedded 3.3V-1.0V switch regulator for the sake of the lowest BOM cost of

the power supply circuit.

RTL9601B



2. Features

CPU

Realtek 550MHz CPU

I-Cache: 32KB, 4-way set

D-Cache: 16KB, 4-way set

Virtually indexed, physically tagged

PREF instruction

Power-down mode (Sleep instruction)

Internal real-time timer interrupts

(Count/Compare registers)

2 hardware instruction breakpoint/1

hardware data breakpoint.

Network Interface Circuit for CPU

The NIC DMA support multiple-

descriptor-ring architecture for QoS

applications

Serial Flash interface (SPI Type) for boot

UART and EJTAG interfaces for debug and

control

Supports six hardware timers and one

watchdog timer

18 GPIOs

4 parallel LED indications

I2C interface for master mode

I2C interface for slave mode

Configurable physical interface for the user

network port

One Gigabit Ethernet physical layer

transceiver

One SerDes supporting 1000BASE-

X/SGMII interface

GPON

Compliant with ITU G.984.x

Bandwidth upstream: 1.24416G/

downstream: 2.48832G

Supports 8 TCONT, 32 GEM

Supports AES, key switching

Supports upstream and downstream FEC

Supports DBRu

Hardware dying gasp

EPON

Compliant with IEEE 802.3 EPON MAC

standard

Bandwidth upstream: 1.25G/

downstream: 1.25G

Supports downstream/upstream FEC

Supports Multiple LLID

Supports OAM

Supports downstream traffic decryption

US scheduling

Per Queue rate control setting

(CIR/PIR)

Support Strict Priority and

Weighted Fair Queuing (WFQ)

mode

Counter–Support RFC4837

Hardware dying gasp

Basic Forwarding Capabilities

Non-blocking wire-speed reception and

transmission and non-head-of-line-

blocking/forwarding

Internal 256 entry 4-way hash L2 look-

up table

RTL9601B



Supports source and destination MAC

address filtering

Full-duplex and half-duplex operation

with IEEE 802.3x flow control and

backpressure

Supports ACL Rules

Supports MAC, IP, TCP/UDP, ICMP,

IGMP, IPv6 Format

Supports trap or copy to CPU, dropping,

priority adjustment, traffic policing,

interrupt, DSCP remarking and IP

remarking.

Supports 4 templates of user defined

ACL rule format

Supports VID/IP/L4 Port /Packet Length

range check

Up to 16 user defined field selectors

Support 256 PON Classification Rules

Supports SVLAN tagging/removing

Supports CVLAN tagging/removing

Supports indirect LLID/GEMPort

assignment

Supports forced UNI ports forwarding

and queuing priority assignment

VLAN translation/aggregation functions

Supports IEEE 802.1Q VLAN

Supports 4096 VLAN

Supports Untag definition in each VLAN

Supports Port Based and Port-and-

Protocol-based VLAN

Supports MAC-based VLAN auto

learning

Supports IEEE 802.1ad Stacking VLAN

Supports 4096 SVLAN

Supports IVL, SVL and IVL/SVL

Supports 256 MAC Address Table

4-way hash

Supports Spanning Tree

IEEE 802.1w Rapid Spanning Tree

Supports Quality of Service (QoS)

Traffic classification based on IEEE

802.1P/Q priority definition, physical

Port, IP DSCP field, ACL definition,

SVLAN based priority

8 priority queues per port

Supports per port Ingress Bandwidth

Control and Egress Bandwidth Control

Per queue flow control

Min-Max Scheduling

Strict Priority and Weighted Fair

Queuing (WFQ) /Weigth Round-

Robin(WRR) to provide minimum

bandwidth

One leaky bucket (APR) to

constraint average rate of each queue

Supports 8 shared meter with 8kbps

granularity

Supports MIB Counters

MIB-II (RFC 1213)

Ethernet-like MIB (RFC 3635)

Interface Group MIB (RFC 2863)

RMON (RFC 2819)

Bridge MIB (RFC 1493)

Bridge MIB Extension (RFC 2674)

ITU G.984.4 OMCI ME MIBs

RFC 4837 Managed Object of EPON

User defined Logging Counter

IGMP/MLD snooping function

RTL9601B



Storm Filtering Control for broadcast,

multicast, unknown unicast with 8Kpbs

granularity rate.

Supports Green Ethernet

Cable length power saving

Link down power saving

Supports IEEE 802.3az Energy Efficient

Ethernet ability for 1000Base-T,

100Base-TX in full duplex operation and

10Base-T in full/half duplex mode

Configurable auto-crossover function

3.3V-1.0V switch regulator with power

MOS

Single 25MHz crystal clock

QFN88 E-PAD package

RTL9601B



3. System Applications

3.1. ONT in SFU application

RTL9601B

10BASE-T

/100BASE-TX

/1000BASE-T

UTP

SPINOR Flash

PON Transceiver

Fiber Cable

Figure 1. ONT in SFU Application

RTL9601B



3.2. Stick ONU in SFP transceiver module

Host network device

I2C

Slave

RTL9601B

1000 BASE-X

/SGMII

SPI

EEPROM

I2C

Master

Laser Driver

NOR Flash

BOSA Device

Fiber Cable

Figure 2. Stick ONU in SFP Transceiver Module

RTL9601B



4. Block Diagram

Switch CoreGMAC0

GMAC2GMAC1

GPHY

PONController

PON MAC

SERDES AFEGPON: 1.24416G / 2.48832G

EPON: 1.25G / 1.25G

NIC

UART JTAG

I2C Slave

LED

DyingGasper

I2C Master

3.3V 1V

Regulator

GPIO

Application Processor32KB I-Cache16KB D-Cache

SerDes AFE1000BASE-X/SGMII

Memerory controller

SPI Master for Flash

RAM

Figure 3. Block Diagram

RTL9601B



5. Pin Assignments

LSO

PLS

OP

AV

DD

LA

VD

DL

AV

DD

HA

VD

DH

DVDDHDVDDH

1111

1212

2828

2727

2626

1919

1818

1717

1616

1515

1414

1313

2929

3939

3838

3737

3636

3535

3434

3333

3232

3131

3030

4040

4444

4343

4242

4141

11 9988776655443322 1010

5252

5353

5555

5454

5656

5757

4949

5050

5151

4848

RTL9601BLLLLLLLTXXXX TAIWAN

RTL9601BLLLLLLLTXXXX TAIWAN

DG_VINDG_VIN

DVDDHDVDDH

DVDDLDVDDL

MVDDHMVDDH

MVDDHMVDDH

VREFVREF

DVDDLDVDDL

MVDDHMVDDH

DVDDLDVDDL

DVDDLDVDDL

DVDDLDVDDL

DV

DD

LD

VD

DL

SVD

DL

SVD

DL

MD

IAP

MD

IAP

LSO

NLS

ON

MVDDHMVDDHG

PIO

5/L

ED2

/JTA

G_T

DI

GP

IO5

/LED

2/J

TAG

_TD

I

LSIN

LSIN

LSIP

LSIP

GP

O4

/JTA

G_T

DO

/DIS

_JTA

GG

PO

4/J

TAG

_TD

O/D

IS_J

TAG

DV

DD

LD

VD

DL

SD/L

OS

SD/L

OS

5858

5959

6060

6161

6262

6363

6464

6565

6666

6767

6868

6969

7070

7171

7272

7373

MD

IBP

MD

IBP

AV

DD

LA

VD

DL

MD

IAN

MD

IAN

GP

IO3

/LED

1/J

TAG

_TM

SG

PIO

3/L

ED1

/JTA

G_T

MS

PSI

NP

SIN

ZQZQ

DVDDLDVDDL

MVDDHMVDDH

BEN

NB

ENN

PSO

NP

SON

PSO

PP

SOP

BEN

PB

ENP

SVD

DH

SVD

DH

MVDDHMVDDH

DVDDLDVDDL

VREFVREF

SVD

DL

SVD

DL

XIXI

XOXO

PSI

PP

SIP

MVDDLMVDDL

GP

IO0

/MSD

AG

PIO

0/M

SDA

GP

IO6

/LED

3/J

TAG

_RST

#G

PIO

6/L

ED3

/JTA

G_R

ST#

MD

IBN

MD

IBN

7474

7575

7676

7777

7878

7979

8080

8181

8282

8383

8484

8585

GP

IO2

/LED

0/J

TAG

_CK

GP

IO2

/LED

0/J

TAG

_CK

GP

IO1

/MSC

KG

PIO

1/M

SCK

2222

2121

2020

RG

ND

RG

ND

DV

DD

HD

VD

DH

RG

ND

RG

ND

AVDDHAVDDH

PVDDLPVDDL

PGNDPGND

8686

8787

8888

2525

2424

2323

RTTRTT

4646

4747

4545

AV

DD

LA

VD

DL

IBR

EFIB

REF

SPIF_IO0/DIS_SI2CSPIF_IO0/DIS_SI2C

SPIF_CLK/EN_4BSPIFSPIF_CLK/EN_4BSPIF

GPO17/SPIF_RST#/DIS_RSTCMDGPO17/SPIF_RST#/DIS_RSTCMD

SPIF_IO1SPIF_IO1

SPIF_CS#/RSVDSPIF_CS#/RSVD

DVDDLDVDDL

GPIO16GPIO16

GPIO15GPIO15

GPIO14GPIO14

GPIO13GPIO13

GPIO12/SSCKGPIO12/SSCK

GPIO11/SSDAGPIO11/SSDA

GPIO10/UTXGPIO10/UTX

GPIO9/URXGPIO9/URX

RESET#RESET#

GPIO8/TXSDGPIO8/TXSD

GPIO7/DISTXGPIO7/DISTX

SWRISWRI

SWRISWRI

SWROSWRO

SWROSWRO

MD

IDP

MD

IDP

MD

IDN

MD

IDN

AV

DD

HA

VD

DH

MD

ICP

MD

ICP

MD

ICN

MD

ICN

AV

DD

LA

VD

DL

Figure 4. Pin Assignments

5.1. Package Identification

Green package is indicated by the ‘G’ in GXXXX (Figure 4).

RTL9601B



5.2. Pin Assignments Table

Upon Reset: Defined as a short time after the end of a hardware reset.

After Reset: Defined as the time after the specified ‘Upon Reset’ time.

I: Input Pin AI: Analog Input Pin

O: Output Pin AO: Analog Output Pin

I/O: Bi-Directional Input/Output Pin AI/O: Analog Bi-Directional Input/Output Pin

P: Digital Power Pin AP: Analog Power Pin

G: Digital Ground Pin AG: Analog Ground Pin

I/OPU: Input Pin With Pull-Up Resistor;

(Typical Value = 75K Ohm)

I/OPU: Output Pin With Pull-Up Resistor;


I/OPD: Input Pin With Pull-Up Resistor;


I/OPD: Output Pin With Pull-Up Resistor;


Table 1. Pin Assignments Table

Name Pin No. Type

XI 1 AI

XO 2 AO

SVDDH 3 AP

PSON 4 AO

PSOP 5 AO

SVDDL 6 AP

BENN 7 AO

BENP 8 AO

PSIP 9 AI

PSIN 10 AI

SD/LOS 11 I

DVDDL 12 P

GPIO0/MSDA 13 I/OPU

GPIO1/MSCK 14 I/OPU

GPIO2/LED0/JTAG_CK 15 I/OPU

GPIO3/LED1/JTAG_TMS 16 I/OPU

GPO4/JTAG_TDO/DIS_JTAG 17 I/OPU

GPIO5/LED2/JTAG_TDI 18 I/OPU

GPIO6/LED3/JTAG_RST# 19 I/OPU

DVDDH 20 P

Name Pin No. Type

RGND 21 AG

RGND 22 AG

SWRO 23 AO

SWRO 24 AO

SWRI 25 AP

SWRI 26 AP

GPIO7/DISTX 27 I/OPU

GPIO8/TXSD 28 I/OPU

RESET# 29 IPU

GPIO9/URX 30 I/OPU

GPIO10/UTX 31 I/OPU

GPIO11/SSDA 32 I/OPU

GPIO12/SSCK 33 I/OPU

GPIO13 34 I/OPU

GPIO14 35 I/OPU

GPIO15 36 I/OPU

GPIO16 37 I/OPU

DVDDL 38 P

SPIF_CS#/RSVD 39 I/OPU

SPIF_IO1 40 I/OPU

RTL9601B



Name Pin No. Type

GPO17/SPIF_RST#/DIS_RST

CMD 41 I/OPU

SPIF_CLK/EN_4BSPIF 42 I/OPD

SPIF_IO0/DIS_SI2C 43 I/OPU

DVDDH 44 P

RTT 45 AI/O

AVDDL 46 AP

IBREF 47 AO

AVDDH 48 AP

MDIAP 49 AI/O

MDIAN 50 AI/O

AVDDL 51 AP

MDIBP 52 AI/O

MDIBN 53 AI/O

AVDDL 54 AP

MDICP 55 AI/O

MDICN 56 AI/O

AVDDL 57 AP

MDIDP 58 AI/O

MDIDN 59 AI/O

AVDDH 60 AP

LSON 61 AO

LSOP 62 AO

LSIP 63 AI

LSIN 64 AI

SVDDL 65 AP

Name Pin No. Type

DVDDL 66 P

DG_VIN 67 AI

DVDDH 68 P

DVDDL 69 P

DVDDL 70 P

MVDDH 71 P

DVDDL 72 P

MVDDH 73 P

VREF 74 AI/O

DVDDL 75 P

DVDDL 76 P

MVDDH 77 P

MVDDH 78 P

MVDDL 79 AP

MVDDH 80 P

DVDDL 81 P

VREF 82 AI/O

MVDDH 83 P

DVDDL 84 P

ZQ 85 AO

PVDDL 86 AP

PGND 87 AG

AVDDH 88 AP

GND EPAD G

RTL9601B



6. Pin Descriptions

6.1. GBE PHY Media Connection Pins

Table 2. GBE PHY Media Connection Pins

Pin Name Pin No. Type Description

MDIAP, MDIAN

MDIBP, MDIBN

MDICP, MDICN

MDIDP, MDIDN

49, 50

52, 53

55, 56

58, 59

AI/O Differential Transmit and Receive Data Pair.

Supports 1000Base-T, 100Base-TX, 10Base-T.

For 1000Base-T operation, differential data from the media is transmitted

and received on all four pairs. For 100Base-Tx and 10Base-T operation,

only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs

MDIAP/N and MDIBP/N.

Each of the differential pairs has an internal 100Ω termination resistor.

6.2. LAN Port SerDes Interface Pins

Table 3. LAN Port SerDes Interface Pins


LSIP, LSIN 63, 64 AI Differential receive data input pair of LAN port SerDes.

Supports 1000Base-X and SGMII mode.

LSOP, LSON 62, 61 AO Differential transmit data input pair of LAN port SerDes.

Supports 1000Base-X and SGMII mode.

6.3. PON Port Interface Pins

Table 4. PON Port Interface Pins


PSIP, PSIN 9, 10 AI Differential receive data input pair of PON port SerDes. Supports EPON

and GPON mode.

PSOP, PSON 5, 4 AO Differential transmit data output pair of PON port SerDes.

Supports EPON and GPON mode.

BENP,BENN 8, 7 AO Differential Transceiver Burst Enable output pair.

Both BENP and BENN can be set to single end LVTTL signal via

register.

SD/LOS 11 I Signal Detect or Loss of Signal input. The definition of this pin is

determined by the polarity setting via register.

For SD:

1: signal is detected

0: signal loses

For LOS:

1: signal loses

0: signal is detected

RTL9601B



GPIO8/TXSD 28 IPU PON Optical Transmit Signal Detect. The active indication signal of the

transmit laser is expected to feed on this pin.

1: the laser is currently activated

0: the laser is currently disabled

It is a shared pin with GPIO8. The default function is GPIO8. It can be

switched to the TXSD via register. Please refer to Table 5

GPIO7/DISTX 27 OPU PON Optical Transmit Disable. It is used to control the PON Optical

signal Transmitting.

1: disable the transmitting

0: enable the transmitting

It is a shared pin with GPIO7. The default function is GPIO7. It can be

switched to the DISTX via register. Please refer to Table 5

6.4. GPIO Pins

Table 5. GPIO Pins


GPIO0/MSDA 13 I/OPU General Purpose Input/output 0

It is a shared pin with MSDA. The default function is GPIO0. It can be

switched to the MSDA via register. Please refer to Table 6

GPIO1/MSCK 14 I/OPU General Purpose Input/output 1

It is a shared pin with MSCK. The default function is GPIO1. It can be

switched to the MSCK via register. Please refer to Table 6

GPIO2/LED0/JTAG_C

K

15 I/OPU General Purpose Input/output 2

It is a shared pin with LED0 and JTAG_CK.

If the pin DIS_JTAG = 1 upon reset, the default function is GPIO2. It can

be switched to the LED0/JTAG_CK via register.

If the pin DIS_JTAG = 0 upon reset, the default function is JTAG_CK. It

can be switched to the LED0/GPIO2 via register.

Please refer to Table 7 and Table 8

GPIO3/LED1/JTAG_T

MS


It is a shared pin with LED1 and JTAG_TMS.


be switched to the LED1/JTAG_TMS via register.

If the pin DIS_JTAG = 0 upon reset, the default function is JTAG_TMS.

It can be switched to the LED1/GPIO3 via register.


GPO4/JTAG_TDO/DI

S_JTAG

17 OPU General Purpose output 4

It is a shared pin with JTAG_TDO and DIS_JTAG.

Upon reset, this pin is DIS_JTAG function to determine if the JTAG

interface is available by default.

After reset,

If the pin DIS_JTAG = 1 upon reset, The default function of this pin is

GPO4. It can be switched to the JTAG_TDO via register.

If the pin DIS_JTAG = 0 upon reset, the default function is JTAG_TDO.

It can be switched to the GPO4 via register.


RTL9601B



GPIO5/LED2/JTAG_T

DI


It is a shared pin with LED2 and JTAG_TDI.


be switched to the LED2/ JTAG_TDI via register.

If the pin DIS_JTAG = 0 upon reset, the default function is JTAG_TDI. It

can be switched to the LED2/GPIO5 via register.


GPIO6/LED3/JTAG_R

ST#


It is a shared pin with LED3 and JTAG_RST#.


be switched to the LED3/ JTAG_RST# via register.

If the pin DIS_JTAG = 0 upon reset, the default function is JTAG_RST#.

It can be switched to the LED3/GPIO6 via register.


GPIO7/DISTX 27 I/OPU General Purpose Input/output 7

It is a shared pin with DISTX. The default function is GPIO7. It can be

switched to the DISTX via register. Please refer to Table 4.

GPIO8/TXSD 28 I/OPU General Purpose Input/output 8

It is a shared pin with TXSD. The default function is GPIO8. It can be

switched to the TXSD via register. Please refer to Table 4.

GPIO9/URX 30 I/OPU General Purpose Input/output 9

It is a shared pin with URX. The default function is GPIO9. It can be

switched to the URX via register. Please refer to Table 10.

GPIO10/UTX 31 I/OPU General Purpose Input/output 10

It is a shared pin with UTX. The default function is GPIO10. It can be

switched to the UTX via register. Please refer to Table 10.

GPIO11/SSDA 32 I/OPU General Purpose Input/output 11

It is a shared pin with SSDA. Please refer to Table 6.

If the pin DIS_SI2C = 1 upon reset, The default function of this pin is

GPIO11.


SSDA.

These 2 functions can be switched via register after reset.

GPIO12/SSCK 33 I/OPU General Purpose Input/output 12

It is a shared pin with SSCK. Please refer to Table 6.


GPIO12.


SSCK.

These 2 functions can be switched via register after reset.

GPIO13 34 I/OPU General Purpose Input/output 13




RTL9601B



GPO17/SPIF_RST#/DI

S_RSTCMD

41 OPU General Purpose output 17

It is a shared pin with SPIF_RST#/DIS_RSTCMD.

Upon reset, this pin is DIS_RSTCMD function.

After reset, the default function of this pin is SPIF_RST#. It can be

switched to the GPO17 function via register. Please refer to Table 11 and

Table 12.

6.5. I2C Pins

Table 6. I2C Pins


GPIO0/MSDA 13 I/OPU Serial Data Input/Output for Master I2C interface.

It is a shared pin with GPIO0. Please refer to Table 5.

GPIO1/MSCK 14 OPU Serial Clock Output for Master I2C interface.


GPIO11/SSDA 32 I/OPU Serial Data Input/Output for Slave I2C interface.


GPIO12/SSCK 33 IPU Serial Clock Input for Slave I2C interface.


6.6. EJTAG Pins

Table 7. EJTAG Pins


GPIO2/LED0/JTAG_C

K

15 IPU EJTAG Test Clock Input

It is a shared pin with LED0 and GPIO2. Please refer to Table 5 and Table

8.

GPIO3/LED1/JTAG_T

MS

16 IPU EJTAG Test Mode Select.


8.

GPO4/JTAG_TDO/DI

S_JTAG

17 OPU EJTAG Test Data Output

It is a shared pin with GPO4 and DIS_JTAG. Please refer to Table 5 and

Table 12.

GPIO5/LED2/JTAG_T

DI

18 IPU EJTAG Test Data Input.


8.

GPIO6/LED3/JTAG_R

ST#

19 IPU EJTAG Test Reset.


8.

RTL9601B



6.7. LED Pins

Table 8. LED Pins


GPIO2/LED0/JTAG_C

K

15 OPU LED 0 Output. It is used to drive LED component directly for the

indication of some device information. The information indicated is

defined by register.

It is a shared pin with JTAG_CK and GPIO2. Please refer to Table 5 and

Table 7.

GPIO3/LED1/JTAG_T

MS




It is a shared pin with JTAG_TMS and GPIO3. Please refer to Table 5 and

Table 7.

GPIO5/LED2/JTAG_T

DI




It is a shared pin with JTAG_TDI and GPIO5. Please refer to Table 5 and

Table 7.

GPIO6/LED3/JTAG_R

ST#




It is a shared pin with JTAG_RST# and GPIO6. Please refer to Table 5

and Table 7.

6.8. Embedded Switch Regulator Pins

Table 9. Embedded Switch Regulator Pins


RGND 21, 22 AG Regulator Ground.

SWRO 23, 24 AO Regulator PWM output. It should connect to the external inductor.

SWRI 25, 26 AP Regulator Power Supply Input.

6.9. UART Pins

Table 10. UART Pins


GPIO9/URX 30 IPU Serial Input of UART Data Receive.


Note: If this pin is configured as URX and floated, it should be pulled up

via an external 4.7K ohm resistor.

GPIO10/UTX 31 OPU Serial Output of UART Data Transmit


RTL9601B



6.10. SPI FLASH Interface Pins

Table 11. SPI FLASH Interface Pins


SPIF_CS#/RSVD 39 OPU SPI FLASH Chip Select Output.

It is a shared pin with RSVD. Upon reset, it is the RSVD pin for chip

configuration. After reset, it is SPIF_CS# pin. Please refer to Table 12

SPIF_IO1 40 I/OPU SPI FLASH Serial Data Input&Output 1 for Dual IO mode and Serial

Data Input (MISO) for Single IO mode. It is Serial Data Input in single

IO mode by default.

GPO17/SPIF_RST#/DI

S_RSTCMD

41 OPU SPI FLASH Hardware Reset Output.

It is used to reset the external FLASH device via the FLASH’s reset pin.

If the hardware reset signal output is selected by the DIS_RSTCMD pin,

it will output the reset signal once the chip is reset.

It is a shared pin with GPO17/DIS_RSTCMD.

Upon reset, this pin is DIS_RSTCMD function.

After reset, the default function of this pin is SPIF_RST#. It can be

switched to the GPO17 function via register. Please refer to Table 12 and

Table 5.

SPIF_CLK/EN_4BSPI

F

42 OPD SPI FLASH Clock Output.

It is a shared pin with EN_4BSPIF. Upon reset, it is the EN_4BSPIF pin

for chip configuration. After reset, it is SPIF_CLK pin. Please refer to

Table 12

SPIF_IO0/DIS_SI2C 43 I/OPU SPI FLASH Serial Data Input&Output 0 for Dual IO mode and Serial

Data Output (MOSI) for Single IO mode.

It is Serial Data Output in single IO mode by default.

It is a shared pin with DIS_SI2C. Upon reset, it is the DIS_SI2C pin for

chip configuration. After reset, it is SPIF_IO0 pin. Please refer to Table

12

6.11. Configuration Pins

Table 12. Configuration Pins


SPIF_CS#/RSVD 39 IPU Reserved for internal test. It should be ‘1’ upon reset for normal

operation.

It is a strapping pin for configuration. ‘Strapping pin’ means the voltage

level on this pin will be latched upon reset for the function configurations

and it will not act as the configuration pin after reset.

1: normal operation mode

0: internal debug mode.

It is a shared pin with SPIF_CS#. Upon reset, it is RSVD. After reset, it is

SPIF_CS#. Please refer to Table 11.

RTL9601B



GPO17/SPIF_RST#/DI

S_RSTCMD

41 IPU Disable Reset Command.

It is a strapping pin to select the method of resetting the external SPI

FLASH when the chip is reset. To synchronize the status of the host chip

and the FLASH device, it is necessary to reset the FLASH device when

the host chip is reset. There are two ways supported to reset the FLASH

device: reset signal on SPIF_RST# pin and specific reset command on

SPIF_IO0 pin.

1: Disable reset command and enable SPIF_RST# pin to output reset

signal when chip is reset.

0: Enable reset command and disable the output of the SPIF_RST# pin.

It is a shared pin with GPO17/SPIF_RST#. Upon reset, it is

DIS_RSTCMD. After reset, it is GPO17 or SPIF_RST#. Please refer to

Table 11 and Table 5.

SPIF_CLK/EN_4BSPI

F

42 IPD Enable 4-byte address mode for SPI FLASH access.

It is a strapping pin.

1: 4-byte address mode by default

0: 3-byte address mode by default

It is a shared pin with SPIF_CLK. Upon reset, it is EN_4BSPIF. After

reset, it is SPIF_CLK. Please refer to Table 11.

SPIF_IO0/DIS_SI2C 43 IPU Disable Slave I2C interface.


1: Disable Slave I2C interface

0: Enable Slave I2C interface

It is a shared pin with SPIF_IO0. Upon reset, it is DIS_SI2C. After reset,

it is SPIF_IO0. Please refer to Table 11.

GPO4/JTAG_TDO/DI

S_JTAG

17 IPU Disable EJTAG interface.


1: Disable EJTAG interface

0: Enable EJTAG interface

It is a shared pin with GPO4/JTAG_TDO. Upon reset, it is DIS_JTAG.

After reset, it is GPO4/JTAG_TDO. Please refer to Table 5 and Table 7.

6.12. Miscellaneous Pins

Table 13. Miscellaneous Pins


XI 1 AI 25MHz Crystal Clock Input and Feedback Pin.

25MHz ±50ppm tolerance crystal reference or external clock input. When

a crystal is used, a loading capacitor should be connected between this pin

and ground. When used as external clock input, this pin is connected with

an oscillator or driven by an external 25MHz clock from another device.

XO 2 AO 25MHz Crystal Clock Output Pin.

When a crystal is used, a loading capacitor should be connected between

this pin and ground. When an external clock source is used, the XO pin

should be left floating.

RTL9601B



RESET# 29 IPU System Reset Input.

Pull the RESET# Pin low to force the whole chip to reset all the circuits.

To complete the reset function, this pin must be asserted for at least 40µs.

It must be pulled high for normal operation.

RTT 45 AI/O Reserved for Internal Use. It should be left floating

IBREF 47 AO Reference Resistor for PHY Band gap.

A 2.49KΩ (1%) resistor should be connected between IBREF and GND.

DG_VIN 67 AI Voltage Detect Input for Dying Gasp. When the voltage on this pin is

lower than 1.2V±5%, the dying gasp event is triggered.

6.13. RAM Interface Pins

Table 14. RAM Interface Pins


ZQ 85 AO External Reference Pin for Calibration. A 240Ω (1%) resistor should be

connected between ZQ and ground.

VREF 74

82

AI/O SSTL reference voltage.

When internal reference generator is enabled, this pin outputs the SSTL

reference voltage and should be left floating.

When internal reference generator is disabled, this pin should be fed in

the external SSTL reference voltage.

6.14. Power and Ground Pins

Table 15. Power and Ground Pins


DVDDL 12, 38, 66,

69, 70, 72,

75, 76, 81,

84

P Digital Low Voltage Power

PVDDL 86 AP PLL Low Voltage Power

SVDDL 6, 65 AP SerDes Low Voltage Power

AVDDL 46, 51, 54,

57

AP Analog Low Voltage Power

MVDDL 79 AP Memory Controller Low Voltage Power

AVDDH 48, 60, 88 AP Analog High Voltage Power

MVDDH 71, 73, 77,

78, 80, 83

P Memory IO High Voltage Power for both the memory controller and the

memory device.

SVDDH 3 AP SerDes High Voltage Power

DVDDH 20, 44, 68 P Digital IO High Voltage Power

PGND 87 AG PLL Ground

GND EPAD G System Ground

RTL9601B



7. Interface Functional Overview

7.1. Giga PHY MDI Interface

The RTL9601B embeds one 10/100/1000M Ethernet PHY. The Ethernet PHY uses a single common

MDI interface to support 1000Base-T, 100Base-TX, and 10Base-T. This interface consists of four signal

pairs-A, B, C, and D. Each signal pair consists of two bi-directional pins that can transmit and receive at

the same time. The MDI interface has internal termination resistors, and therefore reduces BOM cost and

PCB complexity. For 1000Base-T, all four pairs are used in both directions at the same time. For 10Base-

T /100Base-TX links and auto-negotiation, only pairs A and B are used.

7.1.1. 1000Base-T Transmit Function

The 1000Base-T transmit function performs scrambling and 4D-PAM5 encoding. These code groups are

passed through a waveform-shaping filter to minimize EMI effects, and are transmitted onto 4-pair CAT5

cable at 125MBaud/s through a D/A converter.

7.1.2. 1000Base-T Receive Function

Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the

transmitted signal from the input signal for effective reduction of near-end echo. The received signal is

then processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)

correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5

decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz.

The RX MAC retrieves the packet data from the internal receive MII/GMII interface and sends it to the

packet buffer manager.

7.1.3. 100Base-TX Transmit Function

The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,

NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then

scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such

that EMI effects can be reduced significantly.

The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit

stream is driven onto the network media in the form of MLT-3 signaling. The MLT-3 multi-level

signaling technology moves the power spectrum energy from high frequency to low frequency, which

also reduces EMI emissions.

7.1.4. 100Base-TX Receive Function

The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to

compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to

convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error

rate. A de-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL

circuit. Finally, the converted parallel data is fed into the MAC.

RTL9601B



7.1.5. 10Base-T Transmit Function

The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The

internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external

filter.

7.1.6. 10Base-T Receive Function

The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit

detects the signal level is above squelch level.

7.1.7. Auto-Negotiation for UTP

The RTL9601B obtains the states of duplex, speed, and flow control ability for each port in UTP mode

through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During auto-

negotiation, each port advertises its ability to its link partner and compares its ability with advertisements

received from its link partner. By default, the RTL9601B advertises full capabilities (1000Full, 100Full,

100Half, 10Full, 10Half) together with flow control ability.

7.1.8. Crossover Detection and Auto Correction

The RTL9601B automatically determines whether or not it needs to crossover between pairs (see

Table 16) so that an external crossover cable is not required. When connecting to another device that does

not perform MDI crossover, when necessary, the RTL9601B automatically switches its pin pairs to

communicate with the remote device. When connecting to another device that does have MDI crossover

capability, an algorithm determines which end performs the crossover function.

The crossover detection and auto correction function can be disabled via register configuration. The pin

mapping in MDI and MDI Crossover mode is given below.

Table 16. Media Dependent Interface Pin Mapping

Pairs MDI MDI Crossover

1000Base-T 100Base-TX 10Base-T 1000Base-T 100Base-TX 10Base-T

A A TX TX B RX RX

B B RX RX A TX TX

C C Unused Unused D Unused Unused

D D Unused Unused C Unused Unused

7.1.9. Polarity Correction

The RTL9601B automatically corrects polarity errors on the receiver pairs in 1000Base-T and 10Base-T

modes. In 100Base-TX mode, the polarity is irrelevant.

In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle

symbols. Once the de-scrambler is locked, the polarity is also locked on all pairs. The polarity becomes

unlocked only when the receiver loses lock.

RTL9601B



In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The

detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The

polarity becomes unlocked when the link is down.

RX

TX

+

_

+

_

TX

RX

+

_

+

_+

_

RT

L9

60

1B

Lin

k P

art

ne

r

Figure 5. Conceptual Example of Polarity Correction

RTL9601B



7.2. PON Interface

7.2.1. PON SerDes Interface

The RTL9601B delivers a universal PON MAC and a high-performance SerDes to support both GPON

and EPON application. The speed rates of the downstream/upstream are 2.48832Gbps/1.24416Gbps for

GPON application, and 1.25Gbps /1.25Gbps for EPON application.

The PON SerDes Interface of the RTL9601B supports CML and LVPEL mode on the SerDes Tx side,

and CML mode to a Fiber Transceiver on the SerDes Rx side.

7.2.1.1 RX CML Mode

Level

Shifter

Z0=50 ohm

Z=

50

oh

m

Z=

50

oh

m

Z0=50 ohm

VDDH

OE module

CML output

or LVPECL output

Z=

50

oh

m

Z=

50

oh

m

SVDDH

RTL9601B

CML input

PCB

Blocking capacitor

Figure 6. PON SerDes RX CML Mode

7.2.1.2 TX CML Mode

CML

Driver

Z0=50 ohm

Z=

50

oh

m

Z=

50

oh

m

Z0=50 ohm

SVDDH

RTL9601B

CML output

Z=

50

oh

m

Z=

50

oh

m

VDDH

OE module

CML input

PCB

Figure 7. PON SerDes TX CML Mode

RTL9601B



7.2.1.3 TX LVPECL Mode

CML

Driver

Z0=50 ohm

Z=

50

oh

m

Z=

50

oh

m

Z0=50 ohm

Open

RTL9601B

LVPECL output

Z=

50

oh

m

Z=

50

oh

m

OE module

LVPECL input

PCB

R=

69

oh

m

R=

69

oh

m

VDDH

R=

18

3 o

hm

R=

18

3 o

hm

Open

Remote Termination

Figure 8. PON SerDes TX LVPECL Mode0

CML

Driver

Z0=50 ohm

Z=

50

oh

m

Z=

50

oh

m

Z0=50 ohm

SVDDH

RTL9601B

LVPECL output

R=

13

0 o

hm

R=

13

0 o

hm

VDDH

OE module

LVPECL input

PCB

R=

82

2 o

hm

R=

82

2 o

hm

R=

82

oh

m

R=

82

oh

m

Figure 9. PON SerDes TX LVPECL Mode1

RTL9601B



7.2.2. BEN

The BENP/BENN is a differential transceiver burst enable output pair. As with the PON SerDes, the

differential pair supports CML and LVPEL mode.

Both BENP and BENN can be set to a single-end LVTTL signal via register, while the BENP is high

active and the BENN is low active.

R=

4.7

K o

hm

BENBENP

RTL9601B OE module

Figure 10. Single-ended BENP High Active

R=

4.7

K o

hm

SVDDH

BENBENN

RTL9601B OE module

Figure 11. Single-ended BENN Low Active

RTL9601B



7.3. LAN SerDes Interface

The RTL9601B delivers a high-performance SerDes to support 1000BASE-X and SGMII for the

implementation of the stick ONU in SFP transceiver module or other applications using the 1000BASE-

X/SGMII as connection interface.

SGMII (Serial Gigabit Media Independent Interface) operates in both half and full duplex, and at all port

speeds. It includes 2 differential pairs to convey frame data and link rate information between the PHY

and MAC. The data signals operate at 1.25Gbps. These signals is carried as a differential pair, thus

providing signal integrity while minimizing system noise.

RX

TX

+

_

+

_

TX

RX

+

_

_

+

Lin

k P

artn

er

MA

C s

ide

RT

L9

60

1B

PH

Y s

ide

Figure 12. 1000BASE-X and SGMII Signal Diagram

7.4. Master I2C Interface

The master I2C interface of the RTL9601B is used to access SMI Slave device, such as EEPROM, laser

driver and so on. There are two IO pins—MSDA and MSCK. The RTL9601B drives MSCK and MSDA

to read or write the registers of the SMI Slave device. MSDA is the bidirectional data signal, MSCK is

the clock signal. The clock frequency can be configured by register.

The I2C master supports 7-bit device address, A6~A0. Both of the address and data can be configured

into either one byte or two bytes. The access sequences are shown in Figure 13.

A4A5A6

Addr [15:8]S A2R/

W

A

C

K

1 CONTROL BYTE N DATA BYTES

PA1 A0

N ADDRESS BYTES

A

C

K

N

O

A

C

KS A2

R/

W

A

C

K

1 CONTROL BYTE

A1 A0

W

R

I

T

E

R

E

A

D

Read

Write

P

Addr [15:8]S A3 A2R/

W

A

C

K

1 CONTROL BYTE

A1 A0

N ADDRESS BYTES

A

C

K

W

R

I

T

E

Addr [7:0]

A

C

K

Addr [7:0]

A

C

K

A4A5A6 A3 A4A5A6 A3 Data [7:0]

A

C

K

Data [15:8]

N DATA BYTES

P

N

O

A

C

KPData [7:0]

A

C

K

Data [15:8]

Figure 13. I2C Master Access Sequence

RTL9601B



7.5. Slave I2C Interface

The RTL9601B supports I2C slave mode to access the Digital Diagnostic Memory Map Specific Data

Field in EEPROM while used as stick ONU in SFP transceiver module. The information of the Digital

Diagnostic Memory Map Specific Data Field is mirrored into the internal SRAM. When the RTL9601B is

powered on or hardware is reset, software will trigger the information auto download into the mirror

image. The external CPU can directly read or write the mirror image to get or modify the information.

Naturally, ASIC will automatically write the contents to the Digital Diagnostic Memory Map Specific

Data Field after writing operation.

There are two I/O pins (SSDA and SSCK) for the serial management interface. SSDA is the bidirectional

data signal, and SSCK is the clock signal input. The external host device can drive SSCK and SSDA to

access the internal SRAM. The clock is fed into the SSCK pin. The read/write data sequence is shown in

Figure 14. The device address (A2 A1 A0) is 0 and 1.

When the external CPU wants to read/write data from/to the mirror image, it must set the read/write bit

(read is 1, and write is 0) correspondingly.

Addr [7:0]S 1 0 1 0 A2R/

W

A

C

K

1 CONTROL BYTE 1 DATA BYTE

PA1 A0

1 ADDRESS BYTE

A

C

K

N

O

A

C

KS 1 0 1 0 A2

R/

W

A

C

K

1 CONTROL BYTE

A1 A0

W

R

I

T

E

R

E

A

D

Read

Write

Data [7:0] P

Addr [7:0]S 1 0 1 0 A2R/

W

A

C

K

1 CONTROL BYTE 1 DATA BYTE

PA1 A0

1 ADDRESS BYTE

N

O

A

C

K

A

C

K

W

R

I

T

E

Data [7:0] P

Figure 14. I2C Slave 8bit Address Standard Mode Access Sequence

RTL9601B



7.6. SPI (Serial Peripheral Interface)

The Serial Peripheral Interface (SPI) is used to communicate with an external SPI NOR Flash. The SPI

NOR Flash stores code and data for the embedded Realtek CPU of the RTL9601B.

The RTL9601B supports SPI Flash with the following features:

SPI flash frequency: up to 100MHz

Supports 8M/16M/32M Bytes Nor Flash

Supports one chip

In addition to a programmed I/O interface, also supports a memory-mapped I/O interface for read

operation

Supports Read and Fast Read in memory-mapped I/O mode

Supports cached read access for better performance

The RTL9601B supports serial I/O mode and dual I/O mode on the SPI flash interface:

1. Serial I/O mode:

SI: flash chip input pin

SO: flash chip output pin

2. Dual I/O mode:

SPIF_D0 (SI): flash chip bi-directional pin. This is LSB

SPIF_D1 (SO): flash chip bi-directional pin. This is MSB

GPIOB[3]/SPI_CS#

SPIF_CLK/EN_4BSPIF

SPIF_IO0/DIS_SI2C

GPO17/SPIF_RST#/DIS_RSTCMD

RT

L9

60

1B

CS

SCK

SI/IO0

RESET

No

r FL

AS

H

SPIF_IO1 SO/IO1

Figure 15. SPI Interface Diagram

To synchronize the status of the host chip and the FLASH device, it is necessary to reset the FLASH

device when the host chip is reset. There are two ways supported to reset the FLASH device: reset signal

on SPIF_RST# pin and specific reset command on SPIF_IO0 pin. It can be selected by the strapping pin

“DIS_RSTCMD” (refer to Table 12).

RTL9601B



7.7. EJTAG

EJTAG is inexpensive, and easy to implement. EJTAG utilizes the 5-signal IEEE 1149.1 JTAG (Joint

Test Action Group) specification for off-chip communication. The interface pins are shown in Table 17.

Table 17. EJTAG Interface Pins

Pin Name Signal Name Type Description

GPIO2/LED0/JTAG_CK TCK Output Test Clock

GPIO3/LED1/JTAG_TMS TMS Output Test Mode Select

GPO4/JTAG_TDO/DIS_JTAG TDO Output Test Data Out

GPIO5/LED2/JTAG_TDI TDI Input Test Data In

GPIO6/LED3/JTAG_RST# TRST# Output (Optional) Test Reset

TAP Controller

Instruction, Data, and

Control Registers

EJTAG Circuitry

Direct Memory

Access

Processor

Access

CPU

Debug

Registers

System

Memory

Address / Data Busses

A+ D

A+ D

A+ D

Data

Addr .

Data

Addr.TDI

TDO

TCK

TMS

TRST

Figure 16. EJTAG Using a 5-Signal JTAG Interface to Access Data Block

EJTAG provides a path to access internal debug registers and circuitry that monitor and control the

address and data busses of the processor. The DMA and Processor circuit blocks are used to setup and

monitor the processor’s internal busses and to execute the code from the EJTAG interface.

When an access is detected, the EJTAG circuitry makes the transaction address available in the EJTAG

Address Register, and the appropriate data available in the EJTAG Data Register.

RTL9601B



7.8. UART

The RTL9601B provides one UART, which contains a 16-byte FIFO buffer. A programmable baud rate

generator allows division of any input reference clock by 1 to 65535, and generates an internal 16x clock.

The RTL9601B provides a fully programmable serial interface.

In addition to the above functions, the RTL9601B provides fully prioritized interrupt control and

loopback functionality for diagnostic capabilities.

The UART interface pins are shown in the following table.

Table 18. UART Control Interface Pins

Pin Name Signal Name Type Description

GPIO10/UTX UARTTX Output Transmit Data

GPIO9/URX UARTRX Input Receive Data

7.9. LED Indicator

The RTL9601B provides a flexible LED display to show the port link status and other information for

indication. All the LED pins are shared pins with JTAG interface and GPIO. Refer to section 6.7 LED

Pins, page 15 for pin details.

The RTL9601B supports 4 parallel LEDs. Each LED can indicate any port link status via register setting,

and composes the following basic elements (defined in Table 19) to achieve indicator information, e.g.,

Indicator ‘Link’, select ‘Spd1000’, ‘Spd100’, ‘Spd10’; Indicator ‘Link/Act’, select ‘Spd1000’, ‘Spd100’,

‘Spd10’, ‘Spd1000 Act’, ‘Spd100 Act’, ‘Spd10 Act’.

For 1000BASE-X mode, the corresponding LEDs can only selected the basic elements as “Spd1000”,

“Spd100”, “Spd1000 Act”, “Spd100 Act”, “TX_Act” or “RX_Act”. CPU can also enable ‘LED Force

Mode’ and select “LED on/off/blinking” via registers to indicate the PON port status.

The LED blinking time can be configured via registers. Each LED can be controlled via registers

individually to indicate some customized information. When the RTL9601B is powered on or hardware is

reset, all the LEDs will indicate the current port status if the related pins are functionally selected as LED

pins.

Table 19. LED Basic Elements

LED Statuses Description

Spd1000 1000Mbps Speed Indicator.

ON for 1000Mbps link established.

OFF for 10 or 100 Mbps link established or link down.




RTL9601B



LED Statuses Description




Dup Duplex Indicator.

ON for full duplex.

OFF for half duplex or link down.

No Blink even in half duplex and collision.

Spd1000 Act 1000Mbps Activity Indicator. Blinking when the corresponding port is transmitting or

receiving.


receiving.


receiving.

RX_Act Receiving Activity Indicator.

Blink for receiving

OFF for link down or transmitting.

TX_Act Transmitting Activity Indicator.

Blink for Transmitting

OFF for link down or Receiving.

Col Collision Indicator.

Blinking when collision occurs. OFF when no collision happens or link down.

All LED pins’ statuses are represented as active-low or active-high depending on the input value. If the

pin input is pulled high upon reset, the pin output is active low (LED will be on if the pin outputs low

level and off if the pin outputs high level) after reset. If the pin input is pulled down upon reset, the pin

output is active high (LED will be on if the pin outputs high level and off if the pin outputs low level)

after reset. For details refer to Figure 17. Typical values for pull-up/pull-down resistors are 4.7K.

RTL9601B

DVDDIO

LED Pin

Pull-Up

LED Pin

Pull-Down

4.7K

ohm

470 ohm

470 ohm

LED Pins Output Active Low LED Pins Output Active High

RTL9601B

4.7K

ohm

Figure 17. Pull-Up and Pull-Down of LED Pins for LED

RTL9601B



8. General Function Description

8.1. Power on Sequence

Three power domains are required for the RTL9601B normal operation, 3.3V, 1.0V and 1.8V. The

constraints shown below should be complied with for reliable power-on initialization.

T1 is the time when the 3.3V power starts rising

T2 is the time when the 1V power starts rising

T3 is the time when the 1.8V power starts rising

T4 is the time when the 1V power is higher than 0.76V (±5%). The 1V power never falls lower than

0.76V (±5%) after T4

T5 is the time when the 1V power is ready

T6 is the time when the 3.3V power is higher than 2.64V (±5%). The 3.3V power never falls lower

than 2.64V (±5%) after T6

T7 is the time when the 3.3V power is ready

T8 is the time when the 1.8V power is ready

T9 is the time when the pin reset signal is de-asserted

The requirements are:

The rising time of 3.3V power (time between T1 and T7) should be more than 0.001ms.

The rising time of 1.8V power (time between T3 and T8) must be no greater than 200ms.

T5 should be less than 10ms after T4.

T7 should be less than 10ms after T6.

T8 should be less than 100ms after the later of T4 and T6.

T9 is recommended to be later than T5 and T7.

RTL9601B



3.3V Power

1.0V Power

Pin Reset

GND

2.64V

GND

0.76V

GND

3.3V

T1 T2 T4T5T6T7 T9

1.8V Power

T3

T8

Figure 18. Power On Sequence

8.2. Reset

8.2.1. Hardware Reset

8.2.1.1 Power on Reset

The RTL9601B monitors the voltage of both the 1V and the 3.3V power, the RTL9601B will initiate a

power on reset when either of them is lower than the pre-setting threshold (for the 3.3V power, the

threshold is 2.64V±5%; for the 1V power, the threshold is 0.76V±5%). The power on reset will complete

the reset initialization procedures below:

Determine the settings of the strapping pins at the end of the RESET# signal

Initialize the packet buffer descriptor allocation and the output queue

Initialize the internal CPU

Initialize GPHY and SerDes

Auto load the boot code and system image from SPI FALSH

8.2.1.2 Pin Reset

Pin reset is triggered by pulling the RESET# pin low (for at least 10µs). Pin reset forces the RTL9601B to

reset all the circuits and power on sequence is the same as described in Power on Reset section above.

RTL9601B



8.2.2. Software Reset

The RTL9601B supports various reset which can be used to reset some parts of the circuit. Reset sources

are the signals that will trigger the reset command via registers to the chip. All reset signals are low active

and will be self-cleared once set to ‘1’.

8.2.2.1 Chip Reset

This reset is used to reboot the whole chip.

8.2.2.2 Switch Core Reset

This reset is used to reinitialize the switch engine.

8.2.2.3 PON SerDes Reset

This reset is used to reinitialize the GPON/EPON port.

8.3. Clock Circuit

Crystal circuit needs 25MHz±50ppm tolerance crystal reference or oscillator input. When using a crystal,

the RTL9601B should connect a loading capacitor from each pin to ground. Whether using an oscillator

or driving an external 25MHz clock from another device, the external clock should be fed into the XI pin

and the XO pin should be left floating.

Table 20. Crystal and Oscillator Requirements

Parameter Condition Minimum Typical Maximum Unit

Frequency - - 25 - MHz

Frequency Stability Ta=0°C~70°C -30 - 30 ppm

Frequency Tolerance - -50 - 50 ppm

Equivalent Series Resistance of Crystal - - - 50 ohm

Duty Cycle - 40 - 60 %

Broadband Peak-to-Peak Jitter - - - 200 ps

Oscillator Input Vpeak-to-peak - 3.15 3.3 3.45 V

Oscillator Input Rise Time (10%~90%) - - - 12.5 ns

Oscillator Input Fall Time (10%~90%) - - - 12.5 ns

Operating Temperature Range - 0 - 70 °C

8.4. Regulator

The RTL9601B embeds a 3.3V-1.0V switch regulator to simplify the power solution. The 1.0V output

power is used for the digital core and analog circuits. Do not use the regulator for other chips, even if the

rating is enough.

RTL9601B



8.5. PON

8.5.1. GPON

The RTL9601B supports a PON interface compliant with ITU G.984. It supports upstream and

downstream FEC, downstream AES and key switching, DBRu, hardware dying gasp, etc.

The RTL9601B has 32 GEM ports and 8 TCONTs. It has 32 queues in a PON port. For upstream

direction, it supports multiple GEM mapping to one queue; and supports one queue mapping to multiple

GEMs.

Each TCONT can schedule up to 32 queues. Each queue scheduling type can be configured as Strict

Priority (SP), Weighted Round Robin (WRR) and Weighted Fair Queuing (WFQ). It supports mixed

mode SP+WFQ / SP+WRR in one scheduler (TCONT).

It supports per queue configurable Committed Information Rate (CIR) and Peak Information Rate (PIR),

with SP/WFQ/WRR/SP+WFQ/SP+WRR operating simultaneously. It is compliant with the traffic

management option in ITU G.988.

8.5.2. EPON

The RTL9601B supports an EPON interface that is compliant with the IEEE 802.3 EPON MAC standard.

Point to Multi-point protocol with interoperability

Single Copy Broadcast (SCB)

Queue set report

It supports upstream and downstream FEC, downstream traffic decryption, queue set reporting, RFC4837

MIB counter, hardware dying gasp, etc.

Each queue scheduling type can be configured as Strict Priority (SP), Weighted Fair Queuing (WFQ) and

Weighted Round Robin(WRR). It supports mixed mode SP+WFQ/SP+WRR.

It supports per queue configurable Committed Information Rate (CIR) and Peak Information Rate (PIR),

with SP/WFQ/WRR/SP+WFQ/SP+WRR operating simultaneously.

RTL9601B



8.6. Realtek Processor

The RTL9601B features a 550MHz Realtek processor with 32KB I-Cache, 16KB D-Cache, 32KB SRAM,

embedded RAM which maintains system-wide operations, managing packet descriptors and buffers,

memory allocation, bridging, supporting all system IO's and high level applications.

For EPON mode, the Realtek processor will parser, handle, reponse (ack) OAM packet, and implentent

OAM protocol stack; For GPON mode, the Realtek processor will parser, handle, reponse (ack) PLOAM

packet and OMCI packet.

8.7. Memory Controller

The RTL9601B integrates a memory control module to access the internal RAM and the external Flash

memory. The embedded RAM is used as packet buffer and the program and data memory for the CPU.

The memory size is up to 512Mb and the memory speed is configurable in registers.

The RTL9601B also supports a flash memory chip. The interface supports SPI flash memory. When

Flash is used, the system will boot at virtual address 0xBFC0_0000 (physical address: 0x1FC0_0000).

The flash size is configurable from 8M to 32M bytes for each chip. If flash size is set to 8M, 16M, or

32M byte, 0xBFC0_0000 still maps the first 4M bytes of flash, and there will be a new memory mapping

from 0xBD00_0000 (0xBD00_0000 maps to chip 0 byte 0).

8.8. IEEE 802.3x Full Duplex Flow Control

The RTL9601B supports IEEE 802.3x flow control in 10/100/1000M modes. Flow control can be decided

in two ways:

When Auto-Negotiation is enabled, flow control depends on the result of Negotiation

When Auto-Negotiation is disabled, flow control depends on register definition

8.9. Half Duplex Flow Control

In half duplex mode, the CSMA/CD media access method is the means by which two or more stations

share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the

medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If

the message collides with that of another station, then each transmitting station intentionally transmits for

an additional predefined period to ensure propagation of the collision throughout the system. The station

remains silent for a random amount of time (backoff) before attempting to transmit again.

RTL9601B



When a transmission attempt has terminated due to a collision, it is retried until it is successful. The

scheduling of the retransmissions is determined by a controlled randomization process called “Truncated

Binary Exponential Backoff”. At the end of enforcing a collision (jamming), the switch delays before

attempting to retransmit the frame. The delay is an integer multiple of slot time (512 bit times). The

number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed

random integer ‘r’ in the range:

0 ≤ r < 2k

where:

k = min (n, backoffLimit). The backoffLimit for the RTL9601B is 10.

The half duplex back-off algorithm in the RTL9601B does not have the maximum retry count limitation

of 16 (as defined in IEEE 802.3) by default. This means packets in the switch will not be dropped if the

back-off retry count is over 16.

8.9.1. Back-Pressure Mode

In Back-Pressure mode, the RTL9601B sends a 12-byte jam pattern (preamble+SFD+4bytes 0xAA) to

collide with incoming packets when congestion control is activated. The Jam pattern collides at the eighth

byte counted from the preamble. The RTL9601B supports 48PASS1, which receives one packet after 48

consecutive collisions (data collisions and jam collisions). Enable this function to prevent port partition

after 63 consecutive collisions (data collisions + consecutive jam collisions).

8.10. Search and Learning

Search

When a packet is received, the RTL9601B has two kinds of search key. One uses the destination MAC

address to search the 256-entry look-up table. The other uses the destination MAC address, VID to search

the look-up table. The 48-bit MAC address or 12-bit VID use a hash algorithm to calculate an 9-bit index

value. The RTL9601B uses the index to compare the packet MAC address with the entries (MAC

addresses) in the 4-way look-up table. This is the ‘Address Search’. If the destination MAC address is not

found, the switch will broadcast the packet according to VLAN configuration.

Learning

The RTL9601B has two kinds of search key. It can use the source MAC address, or use the source MAC

address and VID of the incoming packet to hash into a 9-bit index. It then compares the source MAC

address with the data (MAC addresses) in this index of 4-way look-up table. If there is a match with one

of the entries, the RTL9601B will update the entry with new information. If there is no match and the 4-

way entries are not all occupied by other MAC addresses, the RTL9601B will record the source MAC

address and ingress port number into an empty entry. This process is called ‘Learning’.

If the look-up table is full, the source MAC address will not be learned in the RTL9601B.

RTL9601B



Address aging is used to keep the contents of the address table correct in a dynamic network topology.

The look-up engine will update the time stamp information of an entry whenever the corresponding

source MAC address appears. An entry will be invalid (aged out) if its time stamp information is not

refreshed by the address learning process during the aging time period. The aging time of the RTL9601B

is can be set to 0.1 ~ 200, 000 seconds.

8.11. SVL and IVL/SVL

In default operation, all VLAN entries belong to the same FID. This is called Shared VLAN Learning

(SVL). The RTL9601B also supports IVL mode for L2 search and learning. In IVL mode, the search key

is MAC address and VID, the same source MAC address with different VIDs can be learned into different

look-up table entries. This is called Independent VLAN Learning and Shared VLAN Learning (IVL/SVL).

8.12. Illegal Frame Filtering

Illegal frames such as CRC error packets, runt packets (length < 64 bytes), and oversize packets (length >

maximum length) will be discarded by the RTL9601B. The maximum packet length may be set to 16 ~

16K bytes.

RTL9601B



8.13. IEEE 802.3 Reserved Group Addresses Filtering Control

The RTL9601B supports the ability to drop/forward IEEE 802.3 specified reserved group MAC addresses:

01-80-C2-00-00-00 to 01-80-C2-00-00-2F. The default setting enables forwarding of these reserved

group MAC address control frames. Frames with group MAC address 01-80-C2-00-00-01 (802.3x Pause)

and 01-80-C2-00-00-02 (802.3ad LACP) will always be filtered. Table 21 shows the Reserved Multicast

Address (RMA) configuration mode from 01-80-C2-00-00-00 to 01-80-C2-00-00-2F.

Table 21. Reserved Multicast Address Configuration Table

Assignment Value

Bridge Group Address 01-80-C2-00-00-00

IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation 01-80-C2-00-00-01

IEEE Std 802.3ad Slow Protocols-Multicast Address 01-80-C2-00-00-02

IEEE Std 802.1X PAE Address 01-80-C2-00-00-03

Provider Bridge Group Address 1-80-C2-00-00-08

Undefined 802.1 Address 01-80-C2-00-00-04 ~

01-80-C2-00-00-07

&

01-80-C2-00-00-09 ~

01-80-C2-00-00-0C

&

01-80-C2-00-00-0F

Provider Bridge MVRP Address 01-80-C2-00-00-0D

IEEE Std 802.1AB Link Layer Discovery Protocol Address 01-80-C2-00-00-0E

All LANs Bridge Management Group Address 01-80-C2-00-00-10

Load Server Generic Address 01-80-C2-00-00-11

Loadable Device Generic Address 01-80-C2-00-00-12

Undefined 802.1 Address 01-80-C2-00-00-13 ~

01-80-C2-00-00-17

&

01-80-C2-00-00-19

&

01-80-C2-00-00-1B ~

01-80-C2-00-00-1F

Generic Address for All Manager Stations 01-80-C2-00-00-18

Generic Address for All Agent Stations 01-80-C2-00-00-1a

GMRP Address 01-80-C2-00-00-20

GVRP Address 01-80-C2-00-00-21

Undefined GARP Address 01-80-C2-00-00-22

|

01-80-C2-00-00-2F

RTL9601B



8.14. Broadcast/Multicast/Unknown DA Storm Control

The RTL9601B enables or disables per-port broadcast/multicast/unknown DA storm control by setting

registers (default is disabled). After the receiving rate of broadcast/multicast/unknown DA packets

exceeds a reference rate, all other broadcast/multicast/unknown DA packets will be dropped. The

reference rate is set via register configuration.

8.15. Port Security Function

The RTL9601B supports three types of security function to prevent malicious attacks:

Per-port enable/disable SA auto-learning for an ingress packet

Per-port enable/disable look-up table aging update function for an ingress packet

Per-port enable/disable drop all unknown DA packets

8.16. MIB Counters

The RTL9601B supports a set of counters to support management functions.

MIB-II (RFC 1213)

Ethernet-Like MIB (RFC 3635)

Interface Group MIB (RFC 2863)

RMON (RFC 2819)

Bridge MIB (RFC 1493)

Bridge MIB Extension (RFC 2674)

ITU G.984.4 OMCI ME MIBs

RFC 4837 Managed Object of EPON

User defined Logging Counter

8.17. VLAN Function

The RTL9601B supports 4K VLAN groups. These can be configured as port-based VLANs,

IEEE 802.1Q tag-based VLANs, and Protocol-based VLANs. Two ingress-filtering and egress-filtering

options provide flexible VLAN configuration:

RTL9601B



Ingress Filtering

The acceptable frame type of the ingress process can be set to ‘Admit All’ or ‘Admit All Tagged’

‘Admit’ or ‘Discard’ frames associated with a VLAN for which that port is not in the member set

Egress Filtering

‘Forward’ or ‘Discard’ Leaky VLAN frames between different VLAN domains

‘Forward’ or ‘Discard’ Multicast VLAN frames between different VLAN domains

The VLAN tag can be inserted or removed at the output port. The RTL9601B will insert a Port VID

(PVID) for untagged frames, or remove the tag from tagged frames. The RTL9601B also supports a

special insert VLAN tag function to separate traffic from the WAN and LAN sides in Router and

Gateway applications.

In router applications, the router may want to know which input port this packet came from. The

RTL9601B supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on egress.

Using this function, VID information carried in the VLAN tag will be changed to PVID. The RTL9601B

also provides an option to admit VLAN tagged packets with a specific PVID only. If this function is

enabled, it will drop non-tagged packets and packets with an incorrect PVID.

8.17.1. Port-Based VLAN

This default configuration of the VLAN function can be modified via an attached flash or UART

interface. The 4K-entry VLAN Table designed into the RTL9601B provides full flexibility for users to

configure the input ports to associate with different VLAN groups. Each input port can join with more

than one VLAN group.

Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a

VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to

determine their VLAN association. All the packets received on a given input port will be forwarded to

this port’s VLAN members.

8.17.2. IEEE 802.1Q Tag-Based VLAN

The RTL9601B supports 4K VLAN entries to perform 802.1Q tag-based VLAN mapping. In 802.1Q

VLAN mapping, the RTL9601B uses a 12-bit explicit identifier in the VLAN tag to associate received

packets with a VLAN. The RTL9601B compares the explicit identifier in the VLAN tag with the 4K

VLAN Table to determine the VLAN association of this packet, and then forwards this packet to the

member set of that VLAN. Two VIDs are reserved for special purposes. One of them is all 1’s, which is

reserved and currently unused. The other is all 0’s, which indicates a priority tag. A priority-tagged frame

should be treated as an untagged frame.

When ‘802.1Q tag aware VLAN’ is enabled, the RTL9601B performs 802.1Q tag-based VLAN mapping

for tagged frames, but still performs port-based VLAN mapping for untagged frames. If ‘802.1Q tag

aware VLAN’ is disabled, the RTL9601B performs only port-based VLAN mapping both on non-tagged

and tagged frames. The processing flow when ‘802.1Q tag aware VLAN’ is enabled is illustrated below.

RTL9601B



Two VLAN ingress filtering functions are supported in registers by the RTL9601B. One is the ‘VLAN

tag admit control, which provides the ability to receive VLAN-tagged frames only. Untagged or priority

tagged (VID=0) frames will be dropped. The other is ‘VLAN member set ingress filtering’, which will

drop frames if the ingress port is not in the member set.

8.17.3. Protocol-Based VLAN

The RTL9601B supports a 4-group Protocol-based VLAN configuration. The packet format can be RFC

1042, LLC, or Ethernet, as shown in Figure 19. There are 4 configuration tables to assign the frame type

and corresponding field value. Taking IP packet configuration as an example, the user can configure the

frame type to be ‘Ethernet’, and value to be ‘0x0800’. Each table will index to one of the entries in the

4K-entry VLAN table. The packet stream will match the protocol type and the value will follow the

VLAN member configuration of the indexed entry to forward the packets.

DA/SA TYPE ……Ethernet

DA/SA Length DSAP/SSAPLLC_Other

Frame Input

Type/Length is

00-00~05-FF?

Frame Type

= Ethernet

Frame Type

= RFC_1042

Frame Type

= LLC_ Other

No

No

DA/SA LengthRFC_1042 AA-AA-03 00-00-00 TYPE

……

……

6 bytes after

Type/Length are

AA-AA-03-00-00-00?

Figure 19. Protocol-Based VLAN Frame Format and Flow Chart

8.17.4. Port VID

In a router application, the router may want to know which input port this packet came from. The

RTL9601B supports Port VID (PVID) for each port to insert a PVID in the VLAN tag for untagged or

priority tagged packets on egress. When 802.1Q tag-aware VLAN is enabled, VLAN tag admit control is

enabled, and non-PVID Discard is enabled at the same time. When these functions are enabled, the

RTL9601B will drop non-tagged packets and packets with an incorrect PVID.

RTL9601B



8.18. QoS Function

The RTL9601B supports 8 priority queues and input bandwidth control. Packet priority selection can

depend on Port-based priority, 802.1p/Q Tag-based priority, IPv4/IPv6 DSCP-based priority, and ACL-

based priority. When multiple priorities are enabled in the RTL9601B, the packet’s priority will be

assigned based on the priority selection table.

Each queue has one leaky bucket for Average Packet Rate. Per-queue in each output port can be set as

Strict Priority (SP), Weighted Round Robin (WRR) or Weighted Fair Queuing (WFQ) for packet

scheduling algorithm.

8.18.1. Input Bandwidth Control

Input bandwidth control limits the input bandwidth. When input traffic is more than the RX Bandwidth

parameter, this port will either send out a ‘pause ON’ frame, or drop the input packet depending on

register setup. Per-port input bandwidth control rates can be set from 8Kbps to 1Gbps (in 8Kbps steps).

8.18.2. Priority Assignment

Priority assignment specifies the priority of a received packet according to various rules. The RTL9601B

can recognize the QoS priority information of incoming packets to give a different egress service priority.

The RTL9601B identifies the priority of packets based on several types of QoS priority information:

Port-based priority

802.1p/Q-based priority

IPv4/IPv6 DSCP-based priority

ACL-based priority

SVLAN-based priority

8.18.3. Priority Queue Scheduling

The RTL9601B supports MAX-MIN packet scheduling.

Packet scheduling offers two modes:

Average Packet Rate (APR) leaky bucket, which specifies the average rate of one queue

Weighted Fair Queuing (WFQ), which decides which queue is selected in one slot time to guarantee

the minimal packet rate of one queue

In addition, each queue of each port can select Strict Priority or WFQ packet scheduling according to

packet scheduling mode. Figure 20 shows the RTL9601B packet-scheduling diagram.

RTL9601B



Scheduler

Guaranteed Max. Guaranteed Min.

Queue 0

Queue 1

Queue 7

APR Leaky

BucketWFQ Leaky Bucket

Figure 20. RTL9601B MAX-MIN Scheduling Diagram

8.18.4. IEEE 802.1p/Q and DSCP Remarking

The RTL9601B supports the IEEE 802.1p/Q and IP DSCP (Differentiated Services Code Point)

remarking function. When packets egress from one of the 8 queues, the packet’s 802.1p/Q priority and IP

DSCP can optionally be remarked to a configured value. Each output queue has a 3-bit 802.1p/Q, and a 6-

bit IP DSCP value configuration register.

8.18.5. ACL-Based Priority

The RTL9601B supports 64-entry ACL (Access Control List) rules. When a packet is received, its

physical port, Layer2, Layer3, and Layer4 information are recorded and compared to ACL entries.

If a received packet matches multiple entries, the entry with the lowest address is valid. If the entry is

valid, the action bit and priority bit will be applied.

If the action bit is ‘Drop’, the packet will be dropped. If the action bit is ‘CPU’, the packet will be

trapped to the CPU instead of forwarded to non-CPU ports (except where it will be dropped by rules

other than the ACL rule)

If the action bit is ‘Permit’, ACL rules will override other rules

If the action bit is ‘Mirror’, the packet will be forwarded to the mirror port and the L2 lookup result

destination port. The mirror port indicates the port configured in the port mirror mechanism

The priority bit will take effect only if the action bit is ‘CPU’, ‘Permit’, and ‘Mirror’. The Priority bit

is used to determine the packet queue ID according to the priority assignment mechanism

RTL9601B



8.19. Classification

The RTL9601B supports 256-entry classification rules. When a packet is received, its physical port, ether

type, VLAN, IP ToS, GPON stream ID, and internal priority are recorded and compared to classification

entries.

If a received packet matches valid entries, the actions of the first matched entry will be applied. The

action can be devided to upstream action and downstream action. For upstream action, it includes:

S-tag action

C-tag action

User priority action

GPON stream ID action

DSCP remarking

DROP action

For downstream action, it includes:

S-tag action

C-tag action

User priority action

Forwarding port mask

DSCP remarking

8.20. Green Ethernet

8.20.1. Link-On and Cable Length Power Saving

The RTL9601B provides link-on and dynamic detection of cable length and dynamic adjustment of

power required for the detected cable length. This feature provides high performance with minimum

power consumption.

8.20.2. Link-Down Power Saving

The RTL9601B implements link-down power saving on a per-port basis, greatly cutting power

consumption when the network cable is disconnected. After detecting an incoming signal, it wakes up

from link-down power saving and operates in normal mode.

RTL9601B



8.21. IEEE 802.3az Energy Efficient Ethernet (EEE) Function

The RTL9601B support IEEE 802.3az Energy Efficient Ethernet ability for 1000Base-T, 100Base-TX in

full duplex operation.

The Energy Efficient Ethernet (EEE) optional operational mode combines the IEEE 802.3 Media Access

Control (MAC) sub-layer with 100Base-TX and 1000Base-T Physical Layers defined to support

operation in Low Power Idle mode. When Low Power Idle mode is enabled, systems on both sides of the

link can disable portions of the functionality and save power during periods of low link utilization.

For 1000Base-T PHY: Supports Energy Efficient Ethernet with the optional function of Low Power

Idle

For 100Base-TX PHY: Supports Energy Efficient Ethernet with the optional function of Low Power

Idle

The RTL9601B MAC uses Low Power Idle signaling to indicate to the PHY, and to the link partner, that

a break in the data stream is expected, and components may use this information to enter power saving

modes that require additional time to resume normal operation. Similarly, it informs the LPI Client that

the link partner has sent such an indication.

RTL9601B



9. DC Specifications

9.1. Absolute Maximum Ratings

WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to

the device, or device reliability will be affected. All voltages are specified reference to GND unless

otherwise specified.

Table 22. Absolute Maximum Ratings

Parameter Min Max Units

Junction Temperature (Tj) - +125 C

Storage Temperature -45 +125 C

DVDDH, AVDDH, SVDDH, SWRI, Supply Referenced to GND,

AGND, RGND GND-0.3 +3.63 V

MVDDH, Supply Referenced to GND GND-0.3 +2.3 V

DVDDL, AVDDL, PVDDL, SVDDL, MVDDL, Supply

Referenced to GND, AGND. GND-0.3 +1.1 V

9.2. Operating Conditions

Table 23. Operating Conditions

Symbol Parameter Min. Typ. Max. Units

Ta Ambient Operating Temperature 0 - 70 C

DVDDH Digital I/O High Voltage Power 3.135 3.3 3.465 V

DVDDL Digital Low Voltage Power. 0.95 1.0 1.05 V

AVDDH Analog High Voltage Power. 3.135 3.3 3.465 V

AVDDL Analog Low Voltage Power. 0.95 1.0 1.05 V

PVDDL PLL Low Voltage Power. 0.95 1.0 1.05 V

SVDDH SerDes Analog High Voltage Power. 3.135 3.3 3.465 V

SVDDL SerDes Analog Low Voltage Power. 0.95 1.0 1.05 V

SWRI Regulator Power Supply Input. 3.135 3.3 3.465 V

MVDDH Memory IO High Voltage Power. 1.7 1.8 1.9 V

MVDDL Memory Controller Low Voltage Power. 0.95 1.0 1.05 V

VREF SSTL Reference Voltage 0.49*

MVDDH

0.5*

MVDDH

0.51*

MVDDH V

RTL9601B



9.3. Total Power Consumption

TBD

9.4. DC Parameters

Table 24. DC Parameters

Symbol Parameter Conditions Min. Typ. Max. Units Notes

VIH Input-High Voltage LVTTL 2.0 - - V 2

VIL Input-Low Voltage LVTTL - - 0.8 V 2

VOH Output-High Voltage - 2.4 - - V 2

VOL Output-Low Voltage - - - 0.4 V 2

IIL Input-Leakage Current VIN=3.3V or 0 -10 1 10 A 2

IOZ Tri-State Output-Leakage Current - -10 1 10 A 2

RPU Internal Pull-Up Resistance - - 75 - KΩ 1, 2

RPD Internal Pull-Down Resistance - - 75 - KΩ 1, 2

Note 1: These values are typical values checked in the manufacturing process and are not tested.

Note 2: These values are for the following signals: I2C, SPI, UART, GPIO, JTAG, LED, Reset and PON interface (except

the differential signals)

9.5. Switch Regulator

Table 25. Switch Regulator


ILIM Current Limit 1.4 1.8 2.1 A

FSW Oscillator Frequency - 2 - MHz

TSS Soft-Start Time - 4 - ms

RTL9601B



10. AC Specifications

10.1. SPI Interface Timing

Table 26. SPI Flash Interface Timing


FSLCK Clock frequency of the SPI_SCLK - - TBD MHz

TR Clock rise time (peak to peak) TBD - - V/ns

TF Clock fall time (peak to peak) TBD - - V/ns

TCS_S CS# active setup time TBD - - ns

TCS_H CS# active hold Time TBD - - ns

TNCS_S CS# not active hold Time TBD - - ns

TNCS_H CS# not active setup time TBD - - ns

TCSH CS# deselect time TBD ns

TMO_S Data Output setup time TBD - - ns

TMO_H Data Output hold time TBD - - ns

TMI_S Data Input setup time TBD - - ns

TMI_H Data Input hold time TBD - - ns

TCS_S

TCSH

TR TF

TMI_S TMI_H

TMO_H

LSB OUT

CS#

(output)

SCLK

(output)

MISO

(input)

MOSI

(output)

TMO_S

TCS_H

TNCS_STNCS_H

Figure 21. SPI Flash Interface Timing

RTL9601B



10.2. JTAG Boundary Scan

Table 27. JTAG Boundary Scan Interface Timing Values

Symbol Parameter Min. Typ. Max. Units Notes

TTCK_L JTAG Clock Low Time TBD - - ns 1

TTCK_H JTAG Clock High Time TBD - - ns 1

TTAPTCK TDI, TMS Setup Time to Rising Edge of TCK TBD - - ns -

TTCKTAP TDI, TMS Hold Time from Rising Edge of TCK TBD - - ns -

TTRST# TDO Output from Falling Edge of TCK - - TBD ns -

TTCK_L JTAG Reset Period TBD - - ns -

Note 1: JTAG clock TCK may be stopped indefinitely in either the low or high phase.

Data Valid

TMSTDI

TCK

TDO

TTAPTCK T TCKTAP

T TCKTDO

TR TF

TRST#

TF TR

TTRST#

Figure 22. Boundary-Scan General and Reset Timing

RTL9601B



10.3. I2C Master Interface Timing

Table 28. I2C Master Mode Timing Values


t1 SCK high time TBD - - ns

t2 SCK low time TBD - - ns

t3 START condition setup time TBD - - ns

t4 START condition hold time TBD - - ns

t5 Data Input hold time TBD - - ns

t6 Data Input setup time TBD - - ns

t7 data to clock output delay TBD - - ns

t8 STOP condition setup time TBD - - ns

SDA Data Output

SCK

t1 t2

t3 t4 t5 t6t8t7

Data Output Data Input Data Input

Figure 23. I2C Master Mode Timing

10.4. I2C Slave Interface Timing

Table 29. I2C Slave Mode Timing Values


t1 SCK high time TBD - - ns

t2 SCK low time TBD - - ns

t3 START condition setup time TBD - - ns

t4 START condition hold time TBD - - ns

t5 Data Input hold time TBD - - ns

t6 Data Input setup time TBD - - ns

t7 data to clock output delay TBD - - ns

t8 STOP condition setup time TBD - - ns

SDA Data Input

SCK

t1 t2

t3 t4 t5 t6t8t7

Data Input Data Output

Figure 24. I2C Slave Mode Timing

RTL9601B



10.5. 1000BASE-X/SGMII Electrical Characteristics

Table 30. 1000BASE-X Transmitter Electrical Characteristics

Symbol Parameter Min Typ Max Units Notes

VTX-DIFFp-p Output Differential Voltage TBD TBD TBD mV

TXTJ Total jitter - - TBD UI Total jitter is defined at 10-12

BER

TTX-RISE Output Rise Time TBD - TBD ps 20% ~ 80%

TTX-FALL Output Fall Time TBD - TBD ps 20% ~ 80%

RTX Differential Resistance TBD TBD TBD ohm

CTX AC Coupling Capacitor TBD TBD TBD nF

LTX Transmit Length in PCB - - TBD inch

Table 31. SGMII Transmitter Electrical Characteristics

Symbol Parameter Min Typ Max Units Notes

VTX-DIFFp-p Output Differential Voltage TBD TBD mV |Vod| range: 150mV-400mV

TXTJ Total jitter - - TBD UI Total jitter is defined at 10-12

BER

TTX-RISE Output Rise Time TBD - TBD ps 20% ~ 80%

TTX-FALL Output Fall Time TBD - TBD ps 20% ~ 80%

RTX Differential Resistance TBD TBD TBD ohm

CTX AC Coupling Capacitor TBD TBD TBD nF

LTX Transmit Length in PCB - - TBD inch

Table 32. 1000BASE-X/SGMII Receiver Electrical Characteristics

Symbol Parameter Min Typ Max Units

VRX-DIFFp-p Input Differential Voltage TBD - TBD mV

RRX Differential Resistance TBD TBD TBD ohm

RTL9601B



10.6. ONU SerDes Electrical Characteristics

Table 33. ONU SerDes Transmitter Electrical Characteristics

Parameter Condition Min Typ Max Units Note

TX Baud Rate GPON TBD TBD TBD Mbps

EPON TBD TBD TBD Mbps

Output Differential Voltage CML TBD - TBD mV

LVPECL TBD - TBD mV

Rise/Fall Time GPON/EPON TBD TBD ps

Differential Resistance GPON/EPON TBD TBD TBD ohms

Total jitter GPON - - TBD UI Total jitter is defined at

10-12

BER

Total jitter EPON - - TBD UI Total jitter is defined at

10-12

BER

Jitter Transfer GPON - - TBD -

Jitter Transfer EPON - - TBD -

CTX - TBD TBD TBD nF AC Coupling Capacitor

LTX - - - TBD inch Transmit Length in PCB

Table 34. ONU SerDes Receiver Electrical Characteristics

Parameter Condition Min Typ Max Units

RX Baud Rate GPON TBD TBD TBD Mbps

EPON TBD TBD TBD Mbps

Input Differential Swing - TBD - TBD mV

Differential Resistance GPON/EPON TBD TBD TBD ohm

RTL9601B



11. Thermal Characteristics

TBD

RTL9601B



12. Mechanical Dimensions

Plastic Quad Flat No-Lead Package 88 Leads 10x10mm2 Outline

Symbol Dimension in mm Dimension in inch

Min Nom Max Min Nom Max

A 0.80 0.85 0.90 0.031 0.033 0.035

A1 0.00 0.02 0.05 0.000 0.001 0.002

A2 --- 0.65 0.70 --- 0.026 0.028

A3 0.20 REF 0.008 REF

b 0.15 0.20 0.25 0.006 0.008 0.010

D/E 10.00BSC 0.394BSC

D1/E1 9.75BSC 0.384BSC

D2/E2 6.65 6.90 7.15 0.262 0.272 0.282

e 0.40BSC 0.016BSC

L 0.30 0.40 0.50 0.012 0.016 0.020

Notes:

1. CONTROLLING DIMENSION: MILLIMETER(mm).

2. REFERENCE DOCUMENTL: JEDEC MO-220.

RTL9601B



13. Ordering Information

Table 35. Ordering Information

Part Number Package Status

RTL9601B-CG QFN88 E-PAD ‘Green’ Package -

Note: See 5.2, page 9 for package identification information.

Realtek Semiconductor Corp.

Headquarters

No. 2, Innovation Road II

Hsinchu Science Park, Hsinchu, 300, Taiwan, R.O.C.

Tel: +886-3-5780211 Fax: +886-3-5776047

www.realtek.com

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