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Assignment-3 INTEGRATED CIRCUITS - CONCEPTS AND DESIGN ELEC-672

Section 2

In this section the most basic gate, a CMOS inverter is designed and simulated. The Inverter is made up of pmos

and nmos, which are connected as shown in the schematic below. The pmos transistor specifications are: width

is equal to twice the number characters in surname (PATIL), which is WP =-5*2=10µ, length is Lp =3µ. The

nmos transistor specifications are: width is WN =-6µ, length is LN =3µ.

A schematic of the CMOS inverter is designed in Cadence with the specification mentioned above.

Figure 2: Schematic of Inverter

A varying voltage pulse is supplied to the inverter using a vpulse V0, The rise time and fall time are set to 1ns,

while the delay is set to 0ns. At every clock cycle the output varies with the input. The input toggles from ‘0’

level to ‘1’ level, correspondingly the output is inverted.

The inverter is simulated using the Spectres simulator. A d.c simulation and Transient response is conducted on

the inverter.

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The plot of d.c analysis is as shown in figure 1.1. The operation of the inverter can be explained in 5 regions

using the load line analysis.

Region I: VIN < VT

In this region nmos is turned off, while the pmos is ON. The corresponding output voltage VO is held at VDD

Region II: VT < VIN < VDD/2

In this region, n -MOS is in saturation mode while p -MOS is unsaturated. The output voltage is more than

VDD/2.

Region III: VIN = VDD/2

In region III both the transistors are in saturation and the d.c curve slope is -∞. The output voltage drop sharply

as can been seen in the plot.

Region IV: VDD/2 < VIN < VDD-VT

nmos is in unsaturation mode while pmos is saturated. The output voltage is less than VDD/2.

Region V: VDD-VT < VIN < VDD

nmos is unsaturated and pmos is turned off. The output voltage is held at VO = 0

Figure .1.1: CMOS Inverter and its DC Analysis



D.C simulation was conducted on the inverter using the Spectres simulator. The simulation waveform is as

shown below.

Figure: 1.2: DC response for inverter

Transient response for cmos inverter is simulated using Spectres simulator. The transient response plot is as

shown below.

Figure: 1.3: Transient response of inverter.


Over shoot

Under shoot


The simulation and testing of the inverter is followed by laying out the layout of inverter. The inverter is laid out

on n-substrate. The layout for inverter is shown in figure 1.4.

Figure 1.4: Layout of CMOS inverter

The layout is laid out with the width of pmos WP =-5*2=10µ and length is Lp =3µ. The width of nmos is WN =-

6µ and length is LN =3µ.after the layout was laid out on cadence a DRC was conducted, the errors that occurred

due to mismatch in design rules are shown in figure 1.5.

Figure 1.5: DRC error report



The DRC errors that occurred in the layout design are:

DRC3447 & DRC44: The poly layer extension over the active area edge was 0.8 µ while a minimum

poly length of 1.5µ specified in the design rule. Extending the poly layer over the active area edge to

1.5 µ resolves this error.

DRC81: The metal layer extending between the drain of pmos and nmos has a thickness of 2.9µ, while

the design rule states the minimum thickness should be 3µ. Extending the metal layer thickness over 3

µ resolves this error.

The DRC for inverter is shown in figure 1.6 below.

Figure 1.6: DRC error fixed


DRC3447 & DRC44

DRC81


Once the errors were fixed, the next step is to extract the layout. The extracted layout is compared with the

schematic and an LVS is performed. The verified LVS report is shown in the figure below.

Figure: 1.7: Completed LVS verification

The LVS verifies that the inverter layout obeys the design rules set. It also verifies that the netlist of schematic

and layout match.

Figure: 1.8: Layout with label


Latch up protection


The above figure 1.8 shows the layout with the different labels. The ground, VDD, the drain and source of both

the nmos and pmos are labelled, also the gate terminal is labelled. The latch up protection is also labelled. The

two tap connections shown in the figure help in reducing Latch up.

Latch up:

what is latch up, why does it occur in IC’s these are answered in the following section. A by-product of the

CMOS structure is a pair of parasitic bipolar transistors. The collector of each BJT is connected to the base of

the other transistor in a positive feedback structure. A phenomenon called latchup can occur when (1) both

BJT's conduct, creating a low resistance path between Vdd and GND and (2) the product of the gains of the two

transistors in the feedback loop, b1 x b2, is greater than one. The result of latchup is at the minimum a circuit

malfunction, and in the worst case, the destruction of the device.

Figure: 1.9: cross section of parasitic transistors in cmos along with the equivalent circuit for parasitic npn and pnp transistor.

Latchup may begin when Vout drops below GND due to a noise spike or an improper circuit hookup (Vout is

the base of the lateral NPN Q2). If sufficient current flows through Rsub to turn on Q2 (I Rsub > 0.7 V), this

will draw current through Rwell. If the voltage drop across Rwell is high enough, Q1 will also turn on, and a

self-sustaining low resistance path between the power rails is formed. If the gains are such that b1 x b2 > 1,

latchup may occur. Once latchup has begun, the only way to stop it is to reduce the current below a critical

level, usually by removing power from the circuit.

The conflicting components can be located as far as possible from each other. This reduces the current gain of

the parasitic transistors, and the triggering sensitivity of the thyristors is reduced. However, these precautions

achieve only limited success because, for reasons of space and cost, the distance between the conflicting

components can be increased only to a certain limit. On the other hand, the continuous process of reduction in

the geometries of semiconductor circuits works in the opposite direction. Therefore, other remedies that combat

latch-up are necessary, including surrounding the critical parts of the circuit with guard rings

These guard rings form additional collectors for the parasitic transistors. Such collectors are connected either to

the positive or negative supply-voltage connection of the integrated circuit. These additional collectors are

placed considerably closer to the base-emitter region of the transistor in question than the corresponding

connections of the complementary transistor. As a result, the charge carriers injected into one of the two



transistors is diverted largely via these auxiliary collectors to the positive or negative supply-voltage connection.

These precautions do not completely eliminate the questionable thyristor. However, the thyristor’s sensitivity is

reduced to such an extent that, under normal operating conditions, there should be little risk of triggering the

thyristor.

The above inverter will have an effect on the performance due to the latchup, which causes the parasitic npn and

pnp transistors to be formed. To reduce the effect of latch up:

Move n-well and n+ source/drain farther apart

Reduce the well and substrate resistances, producing lower voltage drops

Higher substrate doping level reduces Rsub, reduce Rwell by making low resistance contact to GND

Guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic

resistances.

Make sure power supplies are off before plugging a board. A "hot plug in" of an unpowered circuit board or

module may cause signal pins to see surge voltages greater than 0.7 V higher than Vdd, which rises more slowly

to its peak value. When the chip comes up to full power, sections of it could be latched.



Section 3

An inverter loaded with5 identical inverters is to be designed and analysed. The transient response is simulated

using Spectres and investigated. The inverters to be designed here have the same width and length for transistors

which was used in section2.

An inverter is loaded with 5 identical inverters as shown in the figure below the device under test (DUT) drives

the 5 inverters. For a load of 5 the corresponding fall time is calculated using the MATLAB code of

assignment1. The rise time and fall time of the input signal tothe DUT is set to 1/10 of the fall time calculated

using the MATLAB code.

For width WP =10µ, length LP =3µ and WN =-6µ, length is LN =3µ. The fall time as calculated using the

MATLAB code is TF = 2.9205ns. The TF and TR for the vpulse is

TF = TR = 1/10*2.9205ns = 292.05ps

The schematic of the DUT is as shown below in the figure

Figure 2.1: Schematic of Inverter with a fan out of 5



The above schematic is simulated to obtain the transient response. The rise time and fall time of the output can

be analysed in the transient response plot. The transient response of the inverter is as shown below.

Figure 2.2: Transient Response of the Device under test with WP = 10µ

Rise time of a transistor is time voltage takes to rise from 10% VDD to 90% VDD. While fall time is defined as the

time the voltage takes to fall from 90% VDD to 10% VDD. The rise time and fall time can be analysed using the

transient response plot. For the above DUT the rise time and fall time are as calculated below.

Rise Time

Fall Time

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Period = 40ns and Pulse Width = 20ns

TF = TR = 292.05ps

90% VDD = 4.5V 25.24ns

10% VDD = 0.5V 20.94ns

Rise time (TR) 4.3ns


TF = TR = 292.05ps

90% VDD = 4.5V 15.25ns

10% VDD = 0.5V 10.92ns



TF = TR = 292.05ps

90% VDD = 4.5V 40.45ns

10% VDD = 0.5V 42.85ns

Fall time (TF) 2.4ns


TF = TR = 292.05ps

90% VDD = 4.5V 20.45ns

10% VDD = 0.5V 22.8ns



The fall time calculated using the MATLAB code is 2.9205ns while the fall time calculated using the transient

response are 2.4ns and 2.35ns. There is a slight difference between the two values; the cadence tool considers

more parameters than the ones we specified in the MATLAB code. Hence we have a slight variation in the fall

time calculated using the two methods.

The investigation is extended by setting the width of the pmos to be same as nmos. The inverter is simulated and

the rise time and fall time is analysed as in the previous exercise. The fall time calculated using the MATLAB

for the change of width is as shown below.

For width WP = WN = 6µ & length LP = LN = 3µ. The fall time as calculated using the MATLAB code is TF =

2.2315ns. The TF and TR for the vpulse is

TF = TR = 1/10*2.2315ns = 223.15ps

The rise time and fall time of the output can be analysed in the transient response plot. The transient response of

the inverter is as shown below.

Figure 2.3: Transient Response of the Device under test with WP = 6µ

For the above DUT the rise time and fall time are as calculated below.

Rise Time

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TF = TR = 223.15ps

90% VDD = 4.5V 26.61ns

10% VDD = 0.5V 21.01ns



TF = TR = 223.15ps

90% VDD = 4.5V 16.61ns

10% VDD = 0.5V 11.02ns



Fall Time

The minimum geometry inverter is to design the inverter with the minimum specification with equal rise time

and fall. To get equal rise time and fall time, the width of pmos should be more than that of the nmos.

Theoretically the width of pmos should be ≈2.7 times that of the nmos. Since, the mobility of electrons is much

faster than that of the holes also the number of holes is much less compared to the electrons.

Here in our university we use 1.5µ technology, hence a minimum geometry of 1.5µ should be designed.

Considering this the width of pmos is

WP = 2.7*WN = 2.7*1.5µ

≈ 4µ

A load capacitance of 39.577fF is considered in the minimum geometry design. This capacitance value is

obtained from the MATLAB code with a fan out of 5. The schematic is shown below.

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TF = TR = 223.15ps

90% VDD = 4.5V 40.34ns

10% VDD = 0.5V 42.1ns



TF = TR = 223.15ps

90% VDD = 4.5V 20.33ns

10% VDD = 0.5V 22.07ns



Figure: 2.4: Schematic of Minimum Geometry Inverter

The schematic is simulated using SpectreS; the transient response of the minimum geometry inverter is as

shown below.

Figure: 2.5: transient response of the minimum geometry inverter

Rise Time Fall Time

The table shows the rise time and fall time calculated with the minimum geometry design. The fall time of nmos

is slightly less than the rise time of pmos. In the theoretical calculation we might not consider all the parameters

necessary to get equal rise time and fall time, but cadence considers many other parameters while simulating the

schematic, hence the slight difference in rise time and fall time.

The minimum geometry inverter is laid out as layout. The layout is as shown in the figure below.

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TF = TR = 106.85ps

90% VDD = 4.5V 11.66ns

10% VDD = 0.5V 10.32ns



TF = TR = 106.85ps

90% VDD = 4.5V 20.22ns

10% VDD = 0.5V 21.37ns

Fall Time (TF) 1.15ns


Figure: 2.6~: Layout of minimum geometry inverter

The layout is designed with minimum geometry; the width of pmos is 4µ, while the width of nmos is 1.5 µ. The

length of the channel for both nmos and pmos is 1.5 µ. Once the layout is laid out, a DRC check is done to

check is any of the design rules have not been followed. The figure below shows the DRC report

Figure: 2.7: DRC report

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The DRC verification was passed successfully with only the bad routing error. The layout was extracted

successfully and LVS performed. The LVS passed with the netlist matching. The LVS report is shown below.

Figure: 2.8: LVS report

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Section 4

Section 4 is an analysis on the power dissipation of a loaded CMOS inverter. The matched value of WP is used

in the design. The power meter circuit is employed and the power dissipation over 5 or more cycles is plotted.

An analysis on the power dissipation is made in this section. Three main factors contribute to the power

consumption P: the load capacitance C, the supply voltage VDD and the clock frequency f.

CMOS gates are very power-efficient because they dissipate nearly zero power while idle. Standard CMOS

circuit draw current from the power supply only during the switching event. The complementary behaviour of

the CMOS results in a low power characteristic of the nmos and pmos transistors, and is one reason that the

popularity of CMOS. Power in CMOS can be divided into static power and dynamic power dissipation. Figure

3.1 shows the basic inverter circuit consisting of two MOSFETs. The power supply current IDD is the important

factor when calculating power dissipation since.

P = IDDVDD

gives the value in units of watts.

Figure: 3.1: CMOS Inverter with power supply current

Consider the DC characteristic first; Figure 3.2 provides the important plots. When V IN is at a stable logic 0 or

logic 1 voltage level, either the nFET or the pFET is in cutoff. In this case, there is no direct current flow path

through the transistors between the power supply and ground. In a realistic circuit, however, a small amount of

quiescent leakage current IDD flows across the reverse biased the drain-bulk regions. The quiescent DC power

dissipation which is also called as short circuit power is then given by

PDQ = IDDQVDD

When the input voltage is changed from 0 and 1 logic voltages, both FETs conduct. The maximum power

supply current Imax occurs when VIN = VI shown in the plot; this is verified by noting that both the nFET and the

pFET are saturated at this point.

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Figure: 3.2: DC plot with current

The dynamic power is due to the charging and discharging of the output capacitance Cout. The power due to

short circuit is negligible compared to the dynamic power dissipation. A) When the input voltage is at a value of

VIN = 0V, the nFET is in cutoff while pFET is conducting. Thus output capacitance Cout charges to a voltage of

Vout = VDD. B) When the input voltage is increased to a high voltage i.e. VIN = VDD, the situation is reversed as in

Figure 3.3: Mn is active and Mp is in cutoff. This allows the capacitor Cout to the drain the current ‘I’ to ground

through the nmos. The amount of transient power dissipated obviously depends upon the rate at which the input

switches, i.e., the signal frequency f. The dynamic power is given by

PDYN = Cout VDD f

Figure: 3.3: Dynamic power dissipation

To calculate the power dissipated by the circuit we employ a power meter circuit as shown below. This circuit is

included along with the design and the dynamic power and average power can be calculated.

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Figure: 3.2: Power meter Circuit

The current delivered by the power supply can be found out using the circuit shown above. The zero value

voltage source is placed in the lead where the current is required to be measured. The meter circuit takes this

current multiplies it with a factor K, and uses this scaled current to charge the capacitor, C. the voltage across

the capacitor is the PAV.

For the analysis of power, the Short circuit power dissipation and the Dynamic power dissipation is

considered. The Short circuit power dissipation is due to the direct path formed between VDD and Gnd when

both nmos and pmos are on simultaneously, this result in the short circuit current ISC. The Dynamic power

dissipation is due to charging and discharging of the output capacitor Cout, the dynamic current IDYN is associated

with it.

The schematic to check the power dissipation in CMOS inverter is as shown below in figure 3.3, 3.4, 3.5

Figure: 3.3: power meter circuit used to analyse the power dissipation

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Figure: 3.4: Inverter device under test

Figure: 3.5: schematic of the inverter with load

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Figure: 3.3: power meter circuit

Figure: 3.4: Schematic


The above schematic was simulated and the input and output voltage, p-mos and n-mos drain current, the power

dissipation of the device under test is as shown below.

In the plot of drain current of n-mos and p-mos, the short circuit current can be seen at the transition of the input

voltage. As discussed in the beginning the short circuit current is due to the path formed between the VDD and

Gnd when both the transistors are ON. A short circuit current, ISC flows from VDD to Gnd.

Figure: 3.6: Transient response

In the above schematic the voltage drop across nmos and pmos is shown , which is used to calculate the

dynamic power and short circuit power. The drain current for nmos and pmos is shown in the plot; we can see in

the plot the short circuit current ISC and the dynamic current IDYN.

The total power dissipated is a sum of dynamic power due to the IDYN and short circuit power due to ISC

When the input voltage is at logic ‘0’, pmos conducts while nmos is in cutoff. The output capacitor charges to

VDD. During the transition from logic ‘1’ to logic’0’ , both the transistors turn on and there is a path for current

to drain out this is the short circuit current as shown in figure 3.7. So we have

IDP = ISC + IDYN.

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Nmos

Pmos

IDN

IDP

Output

Input

IDYN

ISC


When the input voltage is at logic ‘1’, nmos is conducting, while pmos is turned off. The charge in the

capacitors drains out through nmos. During the transition from logic ‘0’ to logic’1’ , both the transistors turn on

and there is a path for current to drain out this is the short circuit current as shown in figure 3.7. So we have

IDN = ISC + IDYN.

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IDYNISC

IDP ISC

IDPIDYN


Section 5

In the previous section we discussed cmos inverter, its dc analysis, timing analysis and power dissipation

analysis. In this section we analyse and investigate a two input cmos NAND which is also a basic logic gate.

ANALYSIS OF NAND GATE

In CMOS design, the NAND gate consists of two nMOS in series connected to two pMOS in parallel. The

schematic diagram of the NAND cell is reported below. NAND is a basic logic gate used to design complex

circuits. The nMOS in series tie the output to the ground for one single combination A=1, B=1. The CMOS

NAND operation can be explained in three regions: The DC transfer characteristics depend on the input

combinations. Figure 4.1 illustrates the VTC for a CMOS NAND gate.

Figure: 4.1: Voltage Transfer Curve of NAND gate.

When VIN,A and VIN,B are held at 0V. The output of the NAND gate is held at VDD. The equivalent circuit for this

input combination is as shown in figure 4.2 below. The two pmos connected to VDD are ON while the nmos are

turned off. There are two paths for the current to charge the output to VDD. Hence the output voltage is held at

VDD.

Figure: 4.2:

Circuit for VIN,A and VIN,B held at 0V

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When VIN,A is held at 0V & VIN,B is held at 1V, or VIN,A is held at 1V & VIN,B is held at 0V. For the above

combination at least one of the pmos is on, hence there is a path for current to flow through, while there is no

path for current to flow through the nmos though one of them is on. Since there is a path for current to flow

from VDD to ground through output, the voltage at the output is charged to VDD. The equivalent circuits for the

two input combinations are as shown in figure 4.3 below.

Figure: 4.3: Circuit for VIN,A and VIN,B at 1V & 0V: VIN,A and VIN,B at 0V & 1V

There are three input combinations that result in the output voltage changing from a high state to a low state.

The possibilities are:

VIN, A and VIN, B are simultaneously switched over from 0V to VDD.

VIN,A is VDD and VIN,B is switched from 0V towards VDD.

VIN,B is VDD and VIN,A is switched from 0V towards VDD.

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Figure: 4.4: Equivalent circuit to realize for VIN,A and VIN,B at 1V & 1V

The pull-up path consists of a parallel combination of two pmos transistors. If either of the input is at logic `0',

the output node assumes the value VDD. If we look at the VTC in the figure 4.1, there are differences in the

curves and these are due to the electrical structuring of the gate circuit. The pull-down sub-circuit is made of a

series combination of two nmos transistors. These are responsible for conducting logic '0' to the output node

when both of the gates are at VDD, and to realize this let us consider a node X between the two series nmos. The

node X is a problem as its voltage is dependent on the nmosA.

To establish conduction through the chain, both nmosA and nmosB must have a voltage VGS > VTn, provided

there is no body bias. But here we can see that.

VSB, A = VDS, B; VSB, B = 0;

This indicates the presence of body bias on nmosA

Let us calculate the value of the gate threshold voltage VI for the case of simultaneous switching by analyzing

the circuit shown in Figure 4.2. Calling this voltage value VI is appropriate since the circuit is infact acting as an

inverter when the inputs are tied together. The input and output voltages have been placed at

VIN, A = VIN, B = VI = VOUT

With this assumption; the source-gate voltage on both pmos is given by

VSGp = VDD - VI = VSDp.

Which shows that both the pmos are saturated. The nFETs are more complicated to turn on. We will ignore

body bias for simplicity, so that VTN, A ≈ VTN, B. First, we need to determine the state of conduction (saturated or

non-saturated) of each nFET.

VGSA = VI – VDSB.

VGSB = VI.

Using KVL to sum up the drain source voltages to read at the output

VDSA + VDSB = VI.

Consider first the terminal voltages on nmosA. Solving for VDSB from the output equation and substituting into

the gate-source expression gives

VGSA = VI – VDSB.

= VI – (VI - VDSA).

= VDSA.

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Since the saturation voltage is VSAT, A = (VGSA - VTn) we see that VDSA > VSAT is automatically satisfied. Thus, we

may conclude that nmosA is conducting in the saturation mode.

The other nFET nmosB has a gate-source voltage of VGSA = VI which is larger than that on nmosA. This makes

the saturation voltage VSAT, B = (VI - VTn) greater than VSAT, A. Now then, since nmosA and nmosB are in series,

they must have the same current: IDA = IDB Hence, nmosB is conducting in the non-saturation region.

Also the series-connected nFETs in the NAND gate combine to increase the resistance from the output to

ground. In particular, MnB is easier to turn on than MnA due to body-bias effects and the difference between

the applied voltage and VGSA.

SCHEMATIC

The schematic of NAND is as shown in the figure 4.5; the drain of pmos is connected to VDD while the other end

is connected to output and the nmos are in series, connected to ground (gnd). The specification of the nmos and

pmos are: width of pmos is equal to twice the number characters in surname (PATIL), which is WP =-5*2=10µ,

while the length is Lp =3µ, width of nmos is WN =-6µ, and the length is LN =3µ.

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Figure: 4.5: schematic of a two input NAND

SpectreS Simulation

The schematic is saved and the circuit is simulated using SpectreS, the simulation helps in analysing the

input/output plot and also verifies the working of the design gate. The transient plot of the CMOS gate is as

shown in the figure below.

Figure: 4.6: Transient response of CMOS NAND

The transient response verifies that the designed schematic is correct. We can the overshoot and undershoot in

the output which are due to the miller capacitances.

NAND Layout

The analysis and simulation of the NAND gate is followed by the laying out the NAND layout. The layout cell

view is shown below in the figure 4.9.

The Layout features are:

– Single poly-silicon lines (for inputs) are run vertically across both N and P active regions

– Single active area are used for building both nMOS devices and both pMOS devices

– Output wire runs horizontal for easy connection to neighbouring circuit

A DRC was conducted after the layout was laid out. The figure below shows the DRC report along with the

errors

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Figure: 4.7: DRC report

The DRC errors that occurred in the layout design are:

WBRM153:

The only error in the DRC report is ‘WBRM153’ which is for bad routing. However, this is not a potential

design violation, for the device to fail. Cadence sees this kind of routing as an open circuit which is the reason

we have this error.

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WBRM153


Figure: 4.8: Layout with errors

The layout after one of the error was rectified is as shown below , this layout passes the DRC error with only

one error for bad routing, which is not a design violation, the layout is designed as explained above in the

beginning of the section. The layout is as shown below in the figure 4.9.

Figure: 4.9: Layout of CMOS NAND

The corrected layout was extracted; a LVS was performed on the schematic and the Layout. The LVS passed

and the netlist match. The LVS report is as shown below.#

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Figure: 4.10: LVS report

The LVS verifies that the inverter layout obeys the design rules set. It also verifies that the netlist of schematic

and layout match.

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Documents

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inverter layout

layout of cmos inverter

schematic of inverter

layout design

inverter transient response

transient response of

design elec