ibm letter dated 11 march 2010 to turbohercules sas

2455 South Road, Poughkeepsie, NY 12601

March 11, 2010

Mr. Roger Bowler President TurboHercules SAS Tour Arane, 33eme etage 5, Place de la Pyramide La Defense 9 92088 PARIS LA DEFENSE FRANCE

Re: TurboHercules

Dear Mr. Bowler:

We have received and considered your letter of November 18, 2009. The comments you provide do not lead IBM to reconsider IBM's position as set out in my letter of November 4, 2009. Your suggestion that TurboHercules was unaware that IBM has intellectual property rights in this area is surprising. IBM has spent many years and many billions of dollars developing its z-architecture and technology, and is widely known to have many intellectual property rights in this area. IBM's litigation against PSI for, among other things, patent infringement and trade secret misappropriation is a matter of public record, and well known in the industry. According to your own statements, your product emulates significant portions of IBM's proprietary instruction set architecture and IBM has many patents that would, therefore, be infringed. For illustration, I enclose with this letter a non-exhaustive list ofIBM u.S. patents that protect innovative elements ofIBM's mainframe architecture and that IBM believes will be infringed by an emulator covering those elements. For your information, the enclosed list also includes a non-exhaustive list of relevant IBM u .s . published patent applications. Apart from concerns about unauthorized use of proprietary IBM information by one or more TurboHercules contributors, IBM therefore has substantial concerns about infringement of patented IBM technology. In these circumstances, I trust you will understand that IBM cannot agree to your request to reconsider its position.

Sincerely,

Mark S. Anzani VP and Chief Technology Officer, IBM System z

Non-Exhaustive List ofmM U.S. Patents and mM U.S. Published Patent Applications

NO. TITLE PATENT US FEATURE TYPE

OR APPLlCA TIONNO.

1. 7,624,237 INSTRUCTION SET COMPARE, SWAP AND STORE FACILITY WITH NO ARCHITECTURE EXTERNAL SERIALIZATION

7,617,410 2. PARALLEL SYSPLEX SIMULTANEOUSLY UPDATING LOGICAL TIME OF ARCHITECTURE DAY (TO D) CLOCKS FOR MULTIPLE CPUS IN

RESPONSE TO DETECTING A CARRY AT A PREDETERM INED BIT POSlTlON OF A PHYSICAL CLOCK

3. 7,600,053 CHANNEL SUBSYSTEM EMULATION OF EXTENDED INPUT/OUTPUT ARCHITECTURE MEASUREMENT BLOCK FACILITIES

4. 7,594,094 INSTRUCTION SET MOVE DATA FACILITY WITH OPTIONAL ARCHITECTURE SPECIFICATIONS

5. 7,587,531 C HANNEL SUBSYSTEM MULTIPLE LOGICAL INPUT/OUTPUT SUBSYSTEM ARCHITECTURE FACILITY

FACILITATING USE OF STORAGE ACCESS KEYS ARCHITECTURE

6. 7,581,074 MEMORY TO ACCESS STORAGE MANAGING INPUT/OUTPUT INTERRUPTIONS IN

ARCHITECTURE 7. 7,543,095 VIRTUALIZATION

NON- DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS PARSING-ENHANCEMENT FACILITY

ARCHITECTURE 8. 7,516,304 INSTRUCTION SET

MULTIFUNCTION HEXADECIMAL INSTRUCTION ARCHITECTURE

9. 7,500,084 INSTRUCTION SET FORM MANAGING INPUT/OUTPUT INTERRUPTIONS IN

ARCHITECTURE 10. 7,454,548 VIRTUALIZATION

NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS, AND METHODS THEREFOR

11. 7,395,448 PARALLEL SYSPLEX DIRECTLY OBTAINING BY APPLICATION ARCHITECTURE PROGRAMS INFORMATION USABLE IN

DETERMINING CLOCK ACCURACY 12. 7,380,041 VIRTUALIZATION MANAGING INPUT/OUTPUT INTERRUPTIONS IN

ARCHITECTURE NON-DEDICATED INTERRUPTION HARDWARE ENV IRONMENTS

13. 7,373,435 CHANNEL SUBSYSTEM EXTENDED INPUT/OUTPUT MEASUREMENT ARCHITECTURE BLOCK

14. 7,356,725 INSTRUCTION SET METHOD AND APPARATUS FOR ADJUSTING A ARCHITECTURE TIM E OF DAY CLOCK WITHOUT ADJUSTING THE

STEPPING RATE OF AN OSCILLATOR 15. 7,356,710 INSTRUCTION SET SECURITY MESSAGE AUTHENTICATION

ARCHITECTURE CONTROL INSTRUCTION M UL TlPLE LOGICAL INPUT/OUTPUT SUBSYSTEM

ARCHITECTURE 16. 7,290,070 CHANNEL SUBSYSTEM

FACILITY 7,284,100 INV ALIDATfNG STORAGE, CLEARING BUFFER

ARCHITECTURE 17. INSTRUCTION SET

ENTRIES, AND AN INSTRUCTION THEREFOR 7,281,1 15 METHOD, SYSTEM AND PROGRAM PRODUCT FOR

ARCHITECTURE 18. MEMORY

CLEARING SELECTED STORAGE TRANSLATION BUFFER ENTRIES

19. 7,257,718 INSTRUCTION SET CIPHER MESSAGE ASSIST INSTRUCTIONS ARCHITECTURE

20. 7,254,698 INSTRUCTION SET MULTIFUNCTION HEXADECIMAL INSTRUCTIONS ARCHITECTURE

2l. METHOD, SYSTEM AND PROGRAM PRODUCT FOR ARCHITECTURE

7,197,601 MEMORY INVALIDATING A RANGE OF SELECTED STORAGE

I TRANSLATION TABLE ENTRIES 22. VIRTUALIZATION METHOD AND APPARATUS FOR MANAGING THE 7,197,585

2

NO. US . FEATURE TYPE TITLE pAtENT i.

OR APPLICA ' TIONNO.

ARCHITECTURE EXECUTION OF A BROADCAST INSTRUCTION ON A GUEST PROCESSOR

23. 7,174,550 CHANNEL SUBSYSTEM I SHARING COMMUNICATIONS ADAPTERS ACROSS ARCHITECTURE A PLURALITY OF INPUT/OUTPUT SUBSYSTEM

IMAGES 24. 7,174,274 CHANNEL SUBSYSTEM IGATHERING [f0 MEASUREMENT DATA DURING

ARCHITECTURE i AN 110 OPERATION PROCESS 25. 7,159.122 INSTRUCTION SET IMESSAGE DIGEST INSTRUCTIONS

ARCHITECTURE 26. 7,146,523 PARALLEL SYSPLEX MONITORING PROCESSING MODES OF COUPLING

ARCHITECTURE FACILITY STRUCTURES 27. 7,130,949 VIRTUALIZATION . MANAGING INPUT/OUTPUT INTERRUPTIONS IN

ARCHITECTURE I NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS

28. I 7.127,599 CHANNEL SUBSYSTEM MANAGING CONFIGURATIONS OF INPUT/OUTPUT ARCHITECTURE SYSTEM IMAGES OF AN INPUT/OUTPUT

I SUBSYSTEM, WHEREIN A CONFIGURATION IS i

MODIFIED WITHOUT RESTARTING THE IINPUT/OUTPUT SUBSYSTEM TO EFFECT A IMODIFICATION 29. 7,058,837 PARALLEL SYSPLEX METHOD AND SYSTEM FOR PROVIDING A

ARCHITECTURE MESSAGE-TIME-ORDERING FACILITY 30. 7,013,305 I PARALLEL SYSPLEX MANAGING THE STATE OF COUPLING FACILITY

I ARCHITECTURE STRUCTURES, DETECTING BY ONE OR MORE

I I SYSTEMS COUPLED TO THE COUPLING FACILITY,

I I THE SUSPENDED STATE OF THE DUPLEXED I COMMAND, DETECTING BEING INDEPENDENT OF

MESSAGE EXCHANGE 31 7,003,700 PARALLEL SYSPLEX HALTING EXECUTION OF DUPLEXED COMMANDS

ARCHITECTURE 32. 7,000,036 CHANNEL SUBSYSTEM EXTENDED INPUT/OUTPUT MEASUREMENT

ARCHITECTURE FACILITIES 33. 6,996,638 CHANNEL SUBSYSTEM METHOD, SYSTEM AND PROGRAM PRODUCTS

ARCHITECTURE FOR ENHANCING INPUT/OUTPUT PROCESSING FOR OPERATING SYSTEM IMAGES OF A COMPUTING ENVIRONMENT

34. 6,971,002 I PARTITIONING METHOD, SYSTEM, AND PRODUCT FOR BOOTING A PARTITION USING ONE OF MULTIPLE,

I I DIFFERENT FIRMWARE IMAGES WITHOUT REBOOTING OTHER PARTITIONS

35. 6,963,940 CHANNEL SUBSYSTEM I MEASURING UTILIZATION OF INDIVIDUAL ARCHITECTURE COMPONENTS OF CHANNELS

36. 6,963,882 PARALLEL SYSPLEX METHOD AND APP ARATUS FOR PROCESSING A ARCHITECTURE LIST STRUCTURE

37. 6,944,787 PARALLEL SYSPLEX SYSTEM-MANAGED DUPLEXING OF COUPLING ARCHITECTURE FACILITY STRUCTURES

38. 6,862,595 PARALLEL SYSPLEX METHOD AND APPARATUS FOR IMPLEMENTING ARCHITECTURE A SHARED MESSAGE QUEUE USING A LIST

I STRUCTURE I 39. 6,859,866 PARALLEL SYSPLEX SYNCHRONIZING PROCESSING OF COMMANDS

ARCHITECTURE INVOKED AGAINST DUPLEXED COUPLING FACILITY STRUCTURES

40. 6,813,726 1 PARALLEL SYSPLEX RESTARTING A COUPLING FACILITY COMMANDI ARCHITECTURE USING A TOKEN FROM ANOTHER COUPLING

FACILITY COMMAND 41. 6,775 ,789 INSTRUCTION SET METHOD, SYSTEM AND PROGRAM PRODUCTS

3

NO. US FEATURE TYPE TITLE PATENT OR APPLICA TIONNO.

ARCH[TECTU RE FOR GENERATING SEQUENCE VALUES THAT ARE UN [Q UE ACROSS OPERATING SYSTEM IMAGES

42. l 6,748,460 CHANNEL SUBSYSTEM INIT[ATIVE PASSING IN AN lIO OPERATION ARCHITECTURE WI THOUT THE OVERHEAD OF AN INTERRUPT

43. ! 6,7 14,997 VIRTUALIZAT[ON . METHOD AND MEANS FOR ENHANCED I ARCHITECTURE [NTERPRETIVE INSTRUCTION EXECUTION FOR A I

I NEW INTEGRATED COMMUN ICATIONS ADAPTER USING A QUEUED DIRECT INPUT-OUTPUT DEVICE

44. 6,687,853 CHANNEL SUBSYSTEM CHECKPOINTING FOR RECOVERY OF CHANNELS ARCHITECTURE IN A DATA PROCESSING SYSTEM

45. 6,681 ,238 VIRTUALIZATION METHOD AND SYSTEM FOR PROVIDING A ARCHITECTURE HARDWARE MACHINE FUNCTION [N A

PROTECTED VIRTUAL MACHINE 46. 6,654,8 12 PARTIT[ONING COMMUN [CATION BETWEEN MULTIPLE I PARTITIONS EMPLOYING HOST-NETWORK

INTERFACE 47. 6,615,373 PARALLEL SYSPLEX METHOD, SYSTEM AND PROGRAM PRODUCTS

ARCHITECTURE FOR RESOLVING POTENTIAL DEADLOCKS 48. 6,609,214 PARALLEL SYSPLEX METHOD, SYSTEM AND PROGRAM PRODUCTS

ARCHITECTURE FOR COPYING COU PLING FACILITY STRUCTURES 49. 6,598,069 PARTITIONING METHOD AND APPARATUS FOR ASSIGNING

RESOURCES TO LOGICAL PARTIT[ON CLUSTERS 50. 6,594,667 PARALLEL SYSPLEX METHOD, SYSTEM AND PROGRAM PRODUCTS

ARCHITECTURE FOR MODIFYING COUPLING FACILITY STRUCTURES

51. 6,584,554 PARALLEL SYSPLEX DIRECTED ALLOCATION OF COUPLING FACILITY ARCH ITECTURE STRUCTURES

52. I 6,567,841 PARTITIONING METHOD AND APPARATUS FOR CREATING AND I IDENTIFYING LOGICAL PARTITION CLUSTERS

53. 6,539,495 PARALLEL SYSPLEX METHOD, SYSTEM AND PROGRAM PRODUCTS ARCHITECTURE FOR PROVIDING USER-MANAGED DUPLEXING OF

COUPLING FACILITY CACHE STRUCTURES 54. I 6,438,654 PARALLEL SYSPLEX CASTOUTPROC ESSING FOR DUPLEXED CACHE

ARCHITECTURE STRUCTURES 55. 6,345,329 CHANNEL SUBSYSTEM METHOD AND APPARATUS FOR EXCHANGING

ARCHITECTURE DATA USING A QUEUED D[RECT INP UT-OUTPUT DEVICE

\ 56. I 6,339,802 CHANNEL SUBSYSTEM COMPUTER PROGRAM DEVICE AND AN ARCH ITECTURE APPARATUS FOR PROCESSING OF DATA

I REQUESTS USING A QUEUED DIRECT INPUTOUTPUT DEVICE

57. 1 6,336, [84 INSTRUCTION SET METHOD AND APPARATUS FOR PERFORMING A ARCH ITECTURE TRAP OPERATION IN AN INFORMATION

HANDLING SYSTEM 58. 6,332,171 CHANNEL SUBSYSTEM SELF-CONTAINED QUEUES WITH ASSOCIATED

ARCH ITECTURE CONTROL IN FORMATION FOR RECEIPT AND TRANSFER OF INCOMING AN D OUTGOING DATA US ING A QUEUED DIRECT INPUT-OUTPUT DEVICE

59. 6,237,000 PARALLEL SYSPLEX METHOD AND APPARATUS FOR PREVIEWING THE ARCHITECTURE RESULTS OF A DATA STRUCTURE ALLOCATION

60. 6,209,106 PARALLEL SYSPLEX METHOD AND APPARATUS FOR SYNCHRONIZING ARCHITECTURE SELECTED LOGICAL PARTITIONS OF A

PARTITJONED INFORMATION HANDLING SYSTEM TO AN EXTERNAL TIME REFERENCE

4

NO. US FEATURE TYPE TITLE

IPATENT OR APPLICA

I

.TIONNO. 61. 6,189,007 PARALLEL SYSPLEX METHOD AND APPARATUS FOR CONDUCTING A

ARCHITECTURE I HIGH PERFORMANCE LOCKING FACILITY IN A LOOSELY Co.UPLED ENVIRo.NMENT

62. 6,085,313 INSTRUCTIo.N SET COMPUTER PROCESSOR SYSTEM FOR EXECUTING I ARCHITECTURE RXE FORMAT FLOATING POINT INSTRUCTIONS I

63. 6,009,261 EMULATlo.N PREPROCESSING o.F STo.RED TARGET Ro.UTINES Fo.R EMULATING INCOMPATIBLE INSTRUCTIONS o.N A TARGET PRo.CESSo.R

64. 5,987,495 INSTRUCTIo.N SET METHOD AND APPARATUS FOR FULLY ARCHITECTURE RESTORING A PROGRAM Co.NTEXT Fo.LLOWING

AN INTERRUPT 65. 5,953,520 EMULATIo.N ADDRESS TRANSLATIo.N BUFFER FOR DATA

PRo.CESSING SYSTEM EMULATIo.N Mo.DE 66. 5,923 ,890 PARALLEL SYSPLEX METHOD AND APP ARA TUS Fo.R o.PTIMIZING THE 1

ARCHITECTURE HANDLING o.F SYNCHRo.NOUS REQUESTS TO A I I

Co.UPLING FACILITY IN A SYSPLEX I Co.NFIGURATION

67. 5,893,157 INSTRUCTIo.N SET I BLo.CKING SYMBOL Co.NTRo.L IN A COMPUTER

I ARCHITECTURE SYSTEM TO SERIALIZE ACCESSING A DATA I RESo.URCE BY SIMULTANEo.US PROCESSo.R

REQUESTS 68. 5,887,135 PARALLEL SYSPLEX I SYSTEM AND METHo.D FOR MANAGEMENT OF

I I ARCHITECTURE o.BJECT TRANSITIONS IN AN EXTERNAL

ISTORAGE FACILITY ACCESSED BY o.NE o.R Mo.RE I PROCESSORS I

69. 5,875,484 PARALLEL SYSPLEX 1 METHOD AND SYSTEM FOR DETERMINING AND IARCHITECTURE OVERRIDING INFo.RMATION UNA V AILABILITY TIME AT A COUPLING FACILITY i

70. 5,875,336 EMULATIo.N METHOD AND SYSTEM Fo.R TRANSLATING A

INON-NATIVE BYTECo.DE TO. A SET OF Co.DES NATIVE TO A PRo.CESSo.R WITHIN A Co.MPUTER SYSTEM

71. 5,860,115 PARALLEL SYSPLEX REQUESTING A DUMP o.F INFo.RMATlo.N STo.RED ARCHITECTURE WITHIN A Co.UPLING FACILITY, IN WHICH THE

DUMP INCLUDES SERVICEABILITY INFORMATIo.N FRo.M AN o.PERATING SYSTEM THAT LOST

I Co.MMUNICATION WITH THE Co.UPLlNG FACILITY

72. 5,825,678 INSTRUCTIo.N SET METHOD AND APPARATUS FOR DETERMINING I

ARCHITECTURE FLo.ATING Po.INT DATA CLASS I 73. 5,822,562 PARALLEL SYSPLEX METHOD AND APPARATUS Fo.R EXPANSlo.N, I

ARCHITECTURE I CONTRACTlo.N, AND REAPPo.RTIONMENT o.F ISTRUCTURED EXTERNAL STORAGE STRUCTURES

74. 5,76 1,739 PARALLEL SYSPLEX METHODS AND SYSTEMS Fo.R CREATING A ARCHITECTURE STo.RAGE DUMP WITHIN A COUPLING FACILITY

o.F A MULTISYSTEM ENVIRo.MENT 75. 5,745,676 INSTRUCTIo.N SET AUTHORITY REDUCTlo.N AND RESTo.RATIo.N

I ARCHITECTURE I METHOD PRo.VIDING SYSTEM INTEGRITY Fo.R I SUBSPACE GRo.UPS AND SINGLE ADDRESS

I

i SPACES DURING PROGRAM LINKAGE 76. I 5,742,830 PARALLEL SYSPLEX I METHo.D AND APPARATUS Fo.R PERFo.RMING

ARCHITECTURE I Co.NDlTIONAL o.PERATIo.NS o.N EXTERNALLY ! SHARED DATA

77. 5,706,432 PARALLEL SYSPLEX MECHANISM FOR RECEIVING MESSAGES AT A IARCHITECTURE Co.UPLING FACILITY 78. 5,704,055 o.THER ARCHITECTURE DYNAMIC RECo.NFIGURATION o.F MAIN I

5

N6. US FEATURE TYPE TITLE

IPATENT ,

OR I

I APPLICA ITIONNO.

STORAGE AND EXPANDED STORAGE BY MEANS I

OF A SERVICE CALL LOGICAL PROCESSOR 79. 5,696,709 INSTRUCTION SET PROGRAM CONTROLLED ROUNDING MODES

ARCHITECTURE 80. 5,687,106 OTHER ARCHITECTURE , IMPLEMENTATION OF BINARY FLOATING POINT

USING HEXADECIMAL FLOATING POfNT UNIT 8l. . 5,636,373 PARALLEL SYSPLEX SYSTEM FOR SYNCHRONIZING LOGICAL CLOCK

ARCHITECTURE IN LOGICAL PARTITION OF HOST PROCESSOR I WITH EXTERNAL TIME SOURCE BY COMBINING I

CLOCK ADJUSTMENT VALUE WITH SPECIFIC V ALUE OF PARTITION

82. 5,630,050 PARALLEL SYSPLEX METHOD AND SYSTEM FOR CAPTURING AND

I IARCHITECTURE CONTROLLING ACCESS TO INFORMATION IN A I COUPLING FACILITY I 83. 5,613,086 INSTRUCTION SET METHOD AND SYSTEM FOR LOCKING A PAGE OF I ARCHITECTURE REAL STORAGE USING A VIRTUAL ADDRESS

84. 5,581,737 PARALLEL SYSPLEX METHOD AND APPARATUS FOR EXPANSION, ARCHITECTURE CONTRACTION, AND REAPPORTIONMENT OF

STRUCTURED EXTERNAL STORAGE STRUCTURES i 85. 5,574,945 PARALLEL SYSPLEX MULTI CHANNEL INTER-PROCESSOR COUPLING I

I ARCHITECTURE FACILITY PROCESSING RECEIVED COMMANDS

ISTORED IN MEMORY ABSENT STATUS ERROR OF CHANNELS

86. 5,574,938 PARALLEL SYSPLEX ALLOWED OPERATIONAL-LINK TRANSCEIVER I, ARCHITECTURE TABLE VERIFIES THE OPERATIONAL STATUS OF I

TRANSCEIVERS IN A MULTIPLE CONDUCTOR

IDATA TRANSMISSION LINK 87. 5,561,809 PARALLEL SYSPLEX IN A MULTIPROCESSING SYSTEM HAVING A

IARCHITECTURE COUPLING FACILITY, COMMUNICATING MESSAGES BETWEEN THE PROCESSORS AND THE

I COUPLING FACILITY IN EITHER A SYNCHRONOUS II OPERATION OR AN ASYNCHRONOUS OPERATION 88. 5,544,345 PARALLEL SYSPLEX COHERENCE CONTROLS FOR STORE-MULTIPLE

ARCHITECTURE SHARED DATA COORDINATED BY CACHE DIRECTORY ENTRIES IN A SHARED ELECTRONIC STORAGE

I 89. 5,493,668 PARALLEL SYSPLEX MULTIPLE PROCESSOR SYSTEM HAVING

IARCHITECTURE SOFTW ARE FOR SELECTING SHARED CACHE ENTRIES OF AN ASSOCIATED CASTOUT CLASS FOR TRANSFER TO A DASD WITH ONE I/O

I OPERATION 90. 5,493,661 INSTRUCTION SET ! METHOD AND SYSTEM FOR PROVIDING A

I ARCHITECTURE I PROGRAM CALL TO A DISP ATCHABLE UNIT'S BASE SPACE

91. 5,463 ,736 PARALLEL SYSPLEX ! COUPLING FACILITY FOR RECEIVING

II ARCHITECTURE COMMANDS FROM PLURALITY OF HOSTS FOR ACTIV ATING SELECTED CONNECTION PATHS TO I I/O DEVICES AND MAINTAINING STATUS THEREOF

I 92. 5,452,455 CHANNEL SUBSYSTEM ASYNCHRONOUS COMMAND SUPPORT FOR ARCHITECTURE SHARED CHANNELS FOR A COMPUTER COMPLEX

HAVING MULTIPLE OPERATING SYSTEMS 93. 5,450,590 PARALLEL SYSPLEX AUTHORIZATION METHOD FOR CONDITIONAL

IARCHITECTURE COMMAND EXECUTION 94. 5,442,350 OTHER ARCHITECTURE METHOD AND MEANS PROVIDING STADC

I, DICTIONAR Y STRUCTURES FOR COMPRESSING

6

-------------------------------------------------------------------- ----~

1 NO. US FEATURE TYPE TITLE IPATENT .y

IOR APPLICA H ONNO.

I I CHARACTER DATA AND EXPANDING ! COMPRESSED DATA

I 95. 5,416,921 ! PARALLEL SYSPLEX APPARATUS AND ACCOMPANYING METHOD FOR

I I ARCHITECTURE USE IN A SYSPLEX ENVIRONMENT FOR

II PERFORMING ESCALATED ISOLATION OF A SYSPLEX COMPONENT IN THE EVENT OF A

I

FAILURE 96. 5,414,851 PARTITIONING . METHOD AND MEANS FOR SHARING I/O

RESOURCES BY A PLURALITY OF OPERATING SYSTEMS

97. 5,410,695 PARALLEL SYSPLEX APPARATUS AND METHOD FOR LIST ARCHITECTURE MANAGEMENT IN A COUPLED DATA PROCESSING

SYSTEM 98. 5,394,554 PARALLEL SYSPLEX INTERDICTING I/O AND MESSAGING OPERATIONS

ARCHITECTURE FROM SENDING CENTRAL PROCESSING COMPLEX

ITO OTHER CENTRAL PROCESSING COMPLEXES

I AND TO I/O DEVICE IN MULTI-SYSTEM COMPLEX 99. 5,394,542 PARALLEL SYSPLEX CLEARING DATA OBJECTS USED TO MAINTAIN

IARCHITECTURE STATE INFORMATION FOR SHARED DATA AT A

I LOCAL COMPLEX WHEN AT LEAST ONE MESSAGE I PATH TO THE LOCAL COMPLEX CANNOT BE I RECOVERED !

100. 5,392,397 PARALLEL SYSPLEX COMMAND EXECUTION SYSTEM FOR USING

I ARCHITECTURE FIRST AND SECOND COMMANDS TO RESERVE

I AND STORE SECOND COMMAND RELATED

I STATUS INFORMATION lN MEMORY PORTION RESPECTIVELY

10 J. 5,381,535 VIRTUALIZATION DATA PROCESSrNG CONTROL OF SECOND-LEVEL ARCHITECTURE QUEST VIRTUAL MACHINES WITHOUT HOST

INTERVENTION 102. 5,361,356 INSTRUCTION SET I STORAGE ISOLATION WITH SUBSPACE-GROUP

ARCHITECTURE FACILITY ]03. 5,339,405 PARALLEL SYSPLEX COMMAND QUIESCE FUNCTION

ARCHITECTURE 104. 5,331,673 PARALLEL SYSPLEX INTEGRITY OF DATA OBJECTS USED TO

ARCHITECTURE MAINTAIN STATE INFORMATION FOR SHARED I

DATA AT A LOCAL COMPLEX I !

105. 5,317,739 PARALLEL SYSPLEX METHOD AND APPARATUS FOR COUPLING DATA I

ARCHITECTURE PROCESSING SYSTEMS !

106. 5,220,669 OTHER ARCHITECTURE LINKAGE MECHANISM FOR PROGRAM ISOLATION 107. App. INSTRUCTION SET SECURITY MESSAGE AUTHENTICATION

]2/0295 14 ARCHITECTURE INSTRUCTION 108. App. CHANNEL SUBSYSTEM DETERMINING EXTENDED CAPABILITY OF A

I 12/030912 ARCHITECTURE CHANNEL PATH 109. App. CHANNEL SUBSYSTEM I Bl-DIRECTIONAL DATA TRANSFER WITHIN A I

12/030954 ARCHITECTURE . SINGLE 110 OPERATION 110. lAPP' CHANNEL SUBSYSTEM I PROVIDING INDIRECT DATA ADDRESSING IN AN

12/031038 ARCHITECTURE I INPUT/OUTPUT PROCESSING SYSTEM WHERE THE

I INDIRECT DATA ADDRESS LIST IS NON I CONTIGUOUS i

11 l. lApp. CHANNEL SUBSYSTEM I PROVIDING INDIRECT DATA ADDRESSING FOR A II 12/03120] ARCHITECTURE CONTROL BLOCK AT A CHANNEL SUBSYSTEM OF I I AN I/O PROCESSING SYSTEM

112. App. VIRTUALIZATION OPTIMIZATIONS OF A PERFORM FRAME

I 12/036725 ARCHITECTURE MANAGEMENT FUNCTION ISSUED BY PAGEABLE

GUESTS

7

NO. US PATENT OR APPLICA nON NO.

FEATURE TYPE TITLE

113. App. 12/037177

VIRTUALIZATION ARCHITECTURE

SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A SHARED MEMORY TRANSLATION FACILITY

114. App. 12/037268


DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER

115. App. 12/052675


MANAGING USE OF STORAGE BY MULTIPLE PAGEABLE GUESTS OF A COMPUTING ENVIRONMENT

116. i

App. 12/052683


USE OF TEST PROTECTION INSTRUCTION IN I COMPUTING ENVIRONMENTS THAT SUPPORT

P AGEABLE GUESTS 117. App.

111182570 VIRTUALIZATION ARCHITECTURE

FACILITATING PROCESSING WITHIN COMPUTING ENVIRONMENTS SUPPORTING PAGEABLE GUESTS

118. App. 111223641

INSTRUCTION SET ARCHITECTURE

FUSED MULTIPLY ADD SPLIT FOR MULTIPLE PRECISION ARITHMETIC

119. App. 12/363825


MULTIFUNCTION HEXADECIMAL INSTRUCTION FORM SYSTEM AND PROGRAM PRODUCT

120. App. 12/394579


CIPHER MESSAGE ASSIST INSTRUCTION

121. App. 12/417943

INSTRUCTION SET I ARCHITECTURE

PARSING-ENHANCEMENT FACILITY

122. App. 11/437220


EXTRACT CPU TIM E FACILITY

123. App. 12/488670

[NSTRUCTION SET I ARCHITECTURE

STORE CLOCK AND STORE CLOCK FAST INSTRUCTION EXECUTION

124. App. 11/469573

CHANNEL SUBSYSTEM ARCHITECTURE

GATHERING I/O MEASUREMENT DATA DURING AN I/O OPERATION PROCESS

I

I 125. I

App. 111469916


METHOD OF EMPLOYING INSTRUCTIONS TO CONVERT UTF CHARACTERS WITH AN

. ENHANCED EXTENDED TRANSLATION FACILITY 126. App.

111469919 INSTRUCTION SET ARCHITECTURE

METHOD OF TRANSLATING N TO N INSTRUCTIONS EMPLOYING AN EN HANCED EXTENDED TRANSLATION FACILITY

127. App. 12/540261


PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYCHRONIZING TODCLOCKS

128. App. 12/555974

INSTRUCTION SET I

ARCHITECTURE COMPARE, SWAP AND STORE FACILITY WITH NO EXTERNAL SERIALIZATION

129. App. 11/532172


METHOD AND SYSTEM OF RECORDING TIME OF DAY CLOCK

130. App. 11/532177


ENHANCED STORE FACILITY LIST SYSTEM AND OPERATION

131. App. 111551292

I INSTRUCTION SET ARCHITECTURE

MESSAGE DIGEST INSTRUCTION

132. App. 111680894


ROUND FOR REROUND MODE IN A DECIMAL FLOATING POINT INSTRUCTION

133. App. 11/692382


OPTIONAL FUNCTION MULTI-FUNCTION INSTRUCTION

I

134. App. 111733224

MEMORY ARCHITECTURE

CLEARING SELECTED STORAGE TRANSLATION BUFFER ENTRIES BASED ON TABLE ORIG!N ADDRESS

135. App. 111740165


DETECTION OF POTENTIAL NEED TO USE A LARGER DATA FORMAT IN PERFORMING FLOATING POINT OPERATIONS

136. App. INSTRUCTION SET MANAGEMENT OF EXCEPTIONS AND HARDWARE

I

I

I I I 1

I

!

I I

I i

8

NO. US FEATURE TYPE TITLE PATENT OR APPLICA TIONNO. 111740185 ARCHITECTURE INTERRUPTIONS BY AN EXCEPTION SIMULATOR

137. App. INSTRUCTION SET INSERT/EXTRACT BIASED EXPONENT OF 111740683 ARCHITECTURE DECIMAL FLOATING POINT DATA

138. lAPP. INSTRUCTION SET SHIFT SIGNIFICAND OF DECIMAL FLOATING 111740701 ARCHITECTURE POINT DATA

139. App. INSTRUCTION SET COM POSITION/ 111740711 ARCHITECTURE DECOMPOSITION OF DEClMAL FLOATING POINT

DATA 140. App. INSTRUCTION SET CONVERT SIGNIFICAND OF DECIMAL FLOATING

111740721 ARCHITECTURE POINT DATA TO/FROM PACKED DECIMAL I FORMAT

14l. App. INSTRUCTION SET EXTRACT BIASED EXPONENT OF DECIMAL 111770861 ARCHITECTURE FLOATING POINT DATA

142. App. INSTRUCTION SET CONVERT SIGNIFICAND OF DECIMAL FLOATING 11178 1574 ARCHITECTURE POINT DATA TO PACKED DECIMAL FORMAT

143. App. fNSTRUCTION SET CONVERT SIGNIFICAND OF DECIMAL FLOATING 11 178 1650 ARCHITECTURE POlNTDATA FROM PACKED DECIMAL FORMAT

144. App. INSTRUCTION SET COMPOSITION OF DECIMAL FLOATfNG POINT I11 /840323 ARCHITECTURE DATA, AND METHODS THEREFORE

145. App. INSTRUCTION SET DECOMPOSITION OF DECIMAL FLOATING POINT 111840345 ARCHITECTURE DATA

146. App. INSTRUCTION SET DECOMPOSITION OF DECIMAL FLOATING POINT 111840359 ARCHITECTURE DATA, AND METHODS THEREFORE

147. App. INSTRUCTION SET PERFORM FLOATING POINT OPERATION 111868605 ARCHITECTURE ! INSTRUCTION

148. App. VIRTUALIZATION FACILITATING MANAGEMENT OF STORAGE OF A 10/854990 ARCHITECTURE PAGEABLE MODE VIRTUAL ENVIRONMENT

ABSENT INTERVENTION OF A HOST OF THE ENVIRONMENT

149. App. VIRTUALIZATION INTERPRETING I/O OPERATION REQUESTS FROM 10/855200 ARCHITECTURE PAGEABLE GUESTS WITHOUT HOST

INTERVENTION 150. App. INSTRUCTION SET PRE-FETCH DATA AND PRE-FETCH DATA

11 /954526 ARCHITECTURE RELATIVE 151. App. CHANNEL SUBSYSTEM EXTENDED INPUT/OUTPUT MEASUREMENT

11/965866 ARCHITECTURE WORD FACILITY, AND EM ULATION OF THAT FACILITY

152. App. INSTRUCTION SET SYSTEM AND METHOD FOR TOO-CLOCK 11 /968733 ARCHITECTURE STEERING

153. App. fNSTRUCTION SET COMPARE AND BRANCH FACILITY AND 11 /972666 ARCHITECTURE INSTRUCTION THEREFORE

154. App. INSTRUCTION SET EXTRACT CACHE A TTRIB UTE F ACI LITY AN 0 11/972675 ARCHITECTURE INSTRUCTION THEREFORE ,

155. App. INSTRUCTION SET ROTATE THEN OPERATE ON SELECTED BITS 11 /972679 ARCHITECTURE FACILITY AND fNSTRUCTIONS THEREFORE

156. App. MEMORY DYNAMIC ADDRESS TRANSLATION WITH ACCESS 111972682 ARCHITECTURE CONTROL

157. App. MEMORY DYNAMIC ADDRESS TRANSLATION WITH FETCH 11 /972688 ARCHITECTURE PROTECTION

I58. App. fNSTRUCTION SET ROTATE THEN INSERT SELECTED BITS FACILITY I 11 /972689 ARCHITECTURE AND INSTRUCTIONS THEREFORE

159. App. MEMORY DYNAM IC ADDRESS TRANSLATION WITH 11 /972694 ARCHITECTURE CHANGE RECORDING OVERRIDE

160. App. MEMORY DYNAMIC ADDRESS TRANSLATION WITH 11 /972697 ARCHITECTURE FORMAT CONTROL

161. App. MEMORY DYNAMIC ADDRESS TRANSLATION WITH LOAD

9

NO. US > FEATURE TYPE TITLE pATENT OR APPLICA TIONNO, 11/972700 ARCHITECTURE PAGE TABLE ENTRY ADDRESS

162. App. MEMORY DYNAMIC ADDRESS TRANSLATION WITH LOAD I

111972705 ARCHITECTURE REAL ADDRESS I I

163. lApp. MEMORY DYNAMIC ADDRESS TRANSLATION WITH I11/972706 ARCHITECTURE FORMAT CONTROL I 164. App. MEMORY I DYNAMIC ADDRESS TRANSLATION WITH FRAME

1119727 13 ARCHITECTURE MANAGEMENT 165. App. INSTRUCTION SET EXECUTE RELATIVE LONG FACILITY AND

I11/972714 ARCHITECTURE INSTRUCTIONS THEREFORE

I 166. App. MEMORY DYNAMIC ADDRESS TRANSLATION WITH DAT I I

111972715 ARCHITECTURE PROTECTION 167. App. MEMORY DYNAMIC ADDRESS TRANSLATION WITH FRAME

11/972718 ARCHITECTURE MANAGEMENT 168. App. MEMORY DYNAMIC ADDRESS TRANSLATION WITH FRAME

11/972725 ARCHITECTURE MANAGEMENT I I 169. App. INSTRUCTION SET LOAD RELATIVE AND STORE RELATIVE FACILITY I

111972740 ARCHITECTU RE AND INSTRUCTIONS THEREFORE I 170. lAPP. INSTRUCTION SET PERFORMING A CONFIGURATION VIRTUAL

] 11972766 ARCHITECTURE TOPOLOGY CHANGE AND INSTRUCTION THEREFORE

171. App. INSTRUCTION SET COMPARE RELATIVE LONG FACILITY AND I11/972780 I ARCHITECTURE INSTRUCTIONS THEREFORE

172. App. INSTRUCTION SET MOVE FACILITY AND INSTRUCTIONS THEREFORE 111972791 ARCHITECTURE

173. App. INSTRUCTION SET COMPUTER CONFIGURATION VIRTUAL 11 /972802 ARCHITECTU RE TOPOLOGY DISCOV ERY AND INSTRUCTION

THEREFORE

10

ibm letter dated 11 march 2010 to turbohercules sas

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