i2c unit 23 로봇 sw 교육원 조용수. 학습 목표 i2c i2c protocol 구조 n051 i2c 동작 i2c...
TRANSCRIPT
I2C UNIT
23
로봇 SW 교육원조용수
2학습 목표
• I2C• I2C Protocol 구조• N051 I2C 동작 • I2C Register
3I2C Bus
• Inter Integrated Circuit Bus• TWI : Two Wire Interface • Phillips 에서 제안한 규격으로 2 선만을 이용하여
시리얼 전송하는 프로토콜– SCL : I2C Clock– SDA : I2C Data
• I2C 는 1:N 통신이 가능하며 , 각각 디바이스는 Address 를 가지고 있다 .
I2C Protocol 구조 • Normally, a standard communication consists of 4
stages:– START or Repeated START signal generation– Slave address transfer– Data transfer– STOP signal generation
SCL
SDA
SorSr
MSB
ACK
PorSr
P
SrLSB MSB LSB
1 2 7 8 9 1 2 3 - 7 8 9
A6 A5 A4 - A1 A0 R/W D7 D6 D5 - D1 D0 NACKACK
Data Transfer
5
When successful slave addressing has been achieved, the data transfer can proceed on byte-by-byte basis in the direction specified by the R/W bit.The data length is based on actual applica-tion.
SCL
SDA
SorSr
MSB
ACK
PorSr
P
SrLSB MSB LSB
1 2 7 8 9 1 2 3 - 7 8 9
A6 A5 A4 - A1 A0 R/W D7 D6 D5 - D1 D0 NACKACK
Data transfer stage
(example 1 byte data)
Acknowledge
1 2 8 9SCL FROMMASTER
DATA OUTPUT BYTRANSMITTER
DATA OUTPUT BYRECEIVER S
STARTcondition
clock pulse foracknowledgement
not acknowledge
acknowledge
6
Acknowl-edge
Position
NACK: High level
ACK: Low level
Each transferred byte is followed by an ACK or a NACK at 9th clock.
7I2C Read / Write Protocol 구조
• I2C Writ
• I2C Read
8N051 I2C Bus
• Compatible with Philips I2C standard.• Support Master/Slave mode• Support 7 bit addressing mode• Built-in a 14-bit time-out counter to avoid the I2C
bus hang-up.• Multiple address recognition ( Four slave address
with mask option)
9I2C Status
10I2C Register
11I2C Register
12I2C Register
13I2C Register
14I2C Register
15I2C Register
16I2C Register
17I2C Register
18I2C Register
19I2C Register
20I2C Register
21I2C Register