i simulation and characterization of silicon nanowire … · berikutan itu, (i-v) ciri-ciri bagi...
TRANSCRIPT
i
SIMULATION AND CHARACTERIZATION OF SILICON NANOWIRE TRI-GATE
TRANSISTOR WITH HIGH-k INSULATOR
NONA BT RIDWAN
UNIVERSITI TEKNOLOGI MALAYSIA
i
ii
―I hereby declare that I have read this thesis and in my opinion this thesis is
sufficient in terms of scope and quality for the award of the degree of Bachelor of
Engineering Electrical (Electronics).‖
Signature : ……………………………..
Supervisor : Prof. Dr. Razali Ismail
Date : 21th
June 2013
iii
SIMULATION AND CHARACTERIZATION OF SILICON NANOWIRE TRI-GATE
TRANSISTOR WITH HIGH-k INSULATOR
NONA BT RIDWAN
A thesis submitted in fulfilment of the
requirements for the award of degree
Bachelor of Engineering Electrical (Electronics)
Faculty of Electrical Engineering
Universiti Teknologi Malaysia
JUNE 2013
iv
I declare that this thesis entitled ―Simulation and Characterization of Silicon Nanowire
Tri-gate Transistor with High-k Insulator‖ is the result of my own research except as
cited in the references. The thesis has not been accepted for any degree and is not
concurrently submitted in candidature of any other degree.
Signature : ………………………………
Name : Nona bt Ridwan
Date : 21th
June 2013
ii
v
Dedicated to my beloved family,
siblings and all my friends for their
love and sacrifice.
iii
vi
ACKNOWLEDGEMENT
First and foremost, I thank God for everything that has made this dissertation
possible.
I would like to sincerely thank my supervisor, Prof. Dr. Razali Bin Ismail for his
enormous support and encouragement. Without his vision, technical guidance, patience,
and willingness to let me pursue this work, this thesis would not have been possible.
I wish to express my deepest gratitude to my mentor, Fatimah binti Abdul Hamid
for all help and support. Without her guidance and knowledge, I may not manage to
complete this thesis on time. Also, special thanks to my friends, Maisara binti Yasak and
others for their friendship, help and support.
I would like to thank Yayasan Tuanku Abdul Rahman Sarawak, for financial
support of my study.
Finally, I am grateful to my mother, father, and sisters for their encouragement,
support and love.
iv
vii
ABSTRACT
Multigate such as double gate, tri-gate, surrounding gate and FinFET has been
studied rigorously as a potential structure to replace metal-oxide-semiconductor field-
effect transistor (MOSFET). This paper reports the performance between silicon
nanowire tri-gate (SNWT), a semi-cylindrical channel shaped with tri-gate structure and
square shaped tri-gate. However, highlighted part on the report is performance of SNWT
with high-k insulator layer is compared with SNWT with oxide layer. The SNWTT is
modeled based on ideal silicon nanowire structure model; Gate-All-Around (GAA).
First, by using Sentaurus TCAD tool, three-dimensional (3D) geometrical structure is
developed with channel length of 65nm as the validation. Then, the algorithm from
validated model is edited according to required specifications such as channel length,
radius, and dielectric layer deposition. As the length of channel goes beyond 65nm for
tri-gate structure, the electrostatic potential surfaced at corner of channel (corner effect)
is increasing. The performance of the circuit is affected due to channel shape of
transistor. Hence, the corner effect can be reduced by replacing square shaped channel to
semi-cylindrical shape (SNWT). Following that, (I-V) characteristics for tri-gate
transistor, SNWTT, SNWTT with high-k (HfO2) layer and SNWTT with oxide layer are
extracted from simulated model and explored. I-V curves for all performance are
plotted using MATLAB for comparison purpose in terms of leakage current, drive
current, DIBL and on-off ratio. In optimization of device performance, parameters such
as channel length, temperature, radius, and doping concentration are varied and studied.
It was found that modeled SNWTT has minimum leakage current, maximum drive
current and lower DIBL compared to reported silicon nanowire tri-gate MOSFET.
v
viii
ABSTRAK
Multigate seperti dua planar, tiga planar, planar penuh dan FinFET telah dikaji
secara berterusan sebagai struktur yang berpotensi untuk menggantikan (MOSFET).
Kajian ini melaporkan prestasi antara silikon nanowire tiga planar (SNWT), saluran
berbentuk separa silinder dengan struktur tiga planar dan tiga planar berbentuk empat
segi. Walau bagaimanapun, bahagian utama pada laporan itu adalah prestasi SNWT
dengan lapisan penebat tinggi k dibandingkan dengan SNWT dengan lapisan oksida.
SNWTT ini dimodelkan berdasarkan ideal silikon nanowire model struktur; Gate-All-
Around (GAA). Pertama, dengan menggunakan Sentaurus TCAD alat, tiga dimensi (3D)
struktur geometri dibangunkan dengan panjang saluran 65nm sebagai permulaan.
Kemudian, algoritma daripada model disahkan dan diolah mengikut spesifikasi yang
diperlukan. Apabila panjang saluran dikurangkan dari 65nm untuk struktur tiga planar,
potensi elektrostatik muncul di sudut saluran (kesan sudut) semakin meningkat. Prestasi
litar terjejas kerana bentuk saluran transistor. Oleh itu, kesan sudut boleh dikurangkan
dengan menggantikan saluran berbentuk segi empat dengan bentuk semi-silinder
(SNWT). Berikutan itu, (I-V) ciri-ciri bagi transistor tiga planar, SNWTT, SNWTT
dengan high- k (HfO2) lapisan dan SNWTT dengan lapisan oksida yang diekstrak
daripada model simulasi dan diterokai. I-V graf untuk semua prestasi diplot
menggunakan MATLAB untuk tujuan perbandingan dari segi arus kebocoran, memandu
semasa, DIBL dan nisbah di-off. Dalam mengoptimumkan prestasi peranti, parameter
seperti panjang saluran, suhu, radius, kelikatan doping yang berbeza dikaji. Hasilnya,
SNWTT model mempunyai kebocoran minimum,pemacu electik maksimum dan semasa
DIBL lebih rendah berbanding silicon nanowire tiga planar MOSFET yang dilaporkan.
vi
ix
TABLE OF CONTENTS
CHAPTER TITLE PAGE
DECLARATION ii
DEDICATION iii
ACKNOWLEDGEMENT iv
ABSTRACT iv
ABSTRAK vi
TABLE OF CONTENTS vii
LIST OF TABLES x
LIST OF FIGURES xi
LIST OF ABBREVIATIONS xiii
LIST OF SYMBOLS xiv
LIST OF APPENDICES xv
1 INTRODUCTION
1.1 Research Background 1
1.2 Problem Statements 5
1.3 Research Objectives 6
1.4 Research Scopes 7
1.5 Thesis Outline 7
vii
x
2 LITERATURE REVIEW
2.1 Introduction 9
2.2 MOSFET Scaling 10
2.3 MOSFET Scaling Issues 10
2.3.1 Higher Subthreshold Conduction 11
2.3.2 Increased Gate Oxide Leakage 11
2.3.3 Increased Junction Leakage 12
2.3.4 Short Channel Effect 13
2.3.5 Channel Length Modulation 13
2.4 Alternatives and Potential Solutions to Overcome
Scaling Issues
15
2.5 Silicon Nanowire 16
2.5.1 Silicon Nanowire Structure 16
2.5.2 Silicon Nanowire Electrical Properties 18
2.5.3 Fabrication Process of Silicon Nanowire 19
2.5.4 Relationship between Current and Voltage
of Silicon Nanowire Transistor
20
2.6 Tri-gate MOSFETs 22
2.6.1 Tri-gate Structure 22
2.6.2 Corner Effect in Tri-gate Structure 24
2.7 High-k Dielectric 26
2.8 Summary 27
3 RESEARCH METHODOLOGY
3.1 Introduction 29
3.2 Research Activities 29
3.3 Modeling Approach 30
3.3.1 MATLAB 31
3.3.2 Sentaurus TCAD 32
3.4 The SNWTT Modeling 33
3.4.1 Fermi Dirac Distributions 33
viii
xi
3.4.2 Analytical Model for Silicon Nanowire
Transistor
34
3.4.3 SNWTT Modeling Overview 36
3.5 A Development of Silicon Nanowire Tri-gate 40
3.6 Summary 43
4 CHARACTERIZATION OF SILICON NANOWIRE
TRI-GATE
4.1 Introduction 44
4.2 Silicon Nanowire Tri-gate Structure 45
4.3 Flowchart of Device Fabrication for Silicon
Nanowire Tri-gate Transistor
47
4.4 Result and Discussion 48
4.4.1 Tri-gate versus Silicon Nanowire Tri-gate 48
4.4.2 SNWTT with Two Different Insulator
Layers
50
4.4.3 Channel Radius Variation 52
4.4.4 Temperature effect on SNWTT performance 55
4.4.5 Doping concentration effect 56
4.5 Summary 58
5 CONCLUSION AND RECOMMENDATIONS
5.1 Conclusion 59
5.2 Suggestions for Future Work 61
REFERENCES 63-70
APPENDICES 71-78
ix
xii
LIST OF TABLES
TABLE NO. TITLE PAGE
2.1 Comparison of nanowire MOSFET device 18
4.1 The geometry values of silicon nanowire tri-gate transistor
Model 46
x
xiii
LIST OF FIGURES
FIGURE NO. TITLE PAGE
1.1 The numbers of transistors in Intel processor increased
exponentially throughout the years from 1960 to 2010
according to Moore‘s Law
2
1.2 International Technology Roadmap for Semiconductor
(ITRS,2011)
4
1.3 Technology trends on MOSFET (Jakub Kedzierski, 2011) 5
2.1 Structure of (a) Silicon dioxide gate dielectric (b) Potential
high-k dielectric
12
2.2 An effective channel length modulation at saturation
mode.
13
2.3 A comparison between ideal curve MOSFET and
MOSFET with channel length modulation effect.
14
2.4 Schematic representation of different architecture
Silicon Nanowire MOSFET (K. Henari et. al, 2005).
16
2.5 Summary Progression of device structure from single-
gated planar to fully GAA NW MOSFETs (Navab Singh
et al, 2008)
17
2.6 Drain current versus gate voltage for Silicon Nanowire 21
xi
xiv
2.7 Illustration of (a) TEM cross section of N-MOS Tri-gate
structure (b) 3-Dimensional of Tri-gate structure (Doyle et
al., 2003).
23
2.8 Corner effect reduction methods using Pi-Gate device as
reference (Ritzenthaler et al., 2006).
25
2.9 The architecture of (a) 3-D of Tri-gate (b) Cross section of
3-D tri-gate include the corner region
26
3.1 Schematic diagram for silicon nanowire transistor 34
3.2 Methodology for Silicon Nanowire Tri-gate Transistor
modeling.
39
3.3 Flow chart for device simulation of silicon nanowire tri-
gate transistor, SNWTT
42
4.1 Schematic diagram for Silicon Nanowire Tri-gate in (a) 2-
dimensional (2-D) (b) 3-dimensional (3-D)
45
4.2.1 Structure of a) Tri-gate transistor b) Silicon Nanowire Tri-
gate transistor
48
4.2.2 I-V curve Silicon Nanowire Tri-gate designed and
reference Tri-gate (Gate length, Lg = 26nm; Vds = Vgs =
1V)
49
4.3.1 (a) Silicon Nanowire Tri-gate Transistor with oxide layer
structure,
(b) Silicon Nanowire Tri-gate Transistor with high-k
(HfO2) layer structure
50
4.3.2 I-V curve for undoped high-k (HfO2) layer and undoped
oxide layer
51
4.4.1 (a) SNWTT structure with 9nm radius, (b) SNWTT
structure with 11nm radius
52
4.4.2 I-V curve for SNWTT with various channel radiuses 53
4.4.3 Graph of threshold voltage, Vth against radius of channel
of SNWTT
54
4.4.4 DIBL against radius of channel of SNWTT 55
xii
xv
4.5 I-V curve incorporating with SNWTTs for different
temperature
55
4.6 I-V curve for doped high-k metal (HfO2) with different
doping concentration, Na
57
xiii
xvi
LIST OF ABBREVIATIONS
MOSFET -Metal-Oxide-Semiconductor Field-Effect Transistor
FinFET -Fin Field-Effect-Transistor
GAA -Gate-All-Around
SNWT -Silicon Nanowire Tri-gate
SNWTT -Silicon Nanowire Tri-gate Transistor
DIBL -Drain Induced Barrier Lowering
BJT -Bipolar Junction Transistor
FET -Field Effect Transistor
IC -Integrated Circuit
SCE -Short Channel Effect
ITRS -International Technology Roadmap for Semiconductor
TCAD -Technology Computer Aided Design
GIDL -Gate Induced Drain Leakage
EBM -Electron Beam Lithography
VLS -Vapor Liquid Solid
CVD -Chemical Vapor Deposition
SS -Subthreshold Swing
xiv
LIST OF SYMBOLS
Ioff -Off-state current/ Leakage current
Ion -On-state current/ Drive current
HfO2 -Hafnium dioxide
SiO2 -Silicon Oxide
Leff -Effective channel length
𝐶𝐺 , -Gate capacitance
𝑉𝐺𝑇 -Gate voltage
𝜐𝑠𝑎𝑡 -Velocity saturation
𝐼𝐷𝑠𝑎𝑡 -Drain current in saturation
𝑅𝑖𝑛𝑠 -Radius of insulator
𝑅𝑤𝑖𝑟𝑒 -Radius of channel
𝑉𝑐 -Critical Voltage
𝜇0 -Electron permittivity
𝜇𝑙𝑓 -Mobility of electron that is correlated to the mean free
path
A -Capacitor area
K -Dielectric constant of the material
ε0 -Permittivity of free space
T -Thickness of the capacitor oxide insulator
𝑓(𝐸) -Fermi-Dirac Distribution
E -Quantum state of energy
xv
xviii
EF -Fermi energy
kB -Boltzmann‘s constant
T -Temperature
𝜇𝐿𝐹 -Mobility of electrons under low electric field
𝜀𝑜𝑥 -Permittivity of an insulator
𝛼 -Body factor
xvi
xix
LIST OF APPENDICES
APPENDIX TITLE PAGE
A Fabrication Process by Structure 69
B Sentaurus TCAD software 73
xvii
1
CHAPTER 1
INTRODUCTION
1.1 Research Background
The first discovery of the transistor was reported, in 1925 by Julius Edgar
Lilienfeld. Twenty five years later, Bell Laboratories junction transistor created by
Bell Telephone was named as bipolar junction transistor (BJT) while Lilienfeld‘s
design named as field effect transistor (FET). After that, in year 1959, Dawon
Kahng and Martin M. (John) Atalla invented metal-oxide-semiconductor field-
effect-transistor (MOSFET). These findings have become a pioneer in the
development of the transistor world. Since the day, the electronic industry has
started to growth aggressively with rapid changes in every year. In order to expand
the usage of transistors for many areas, the integrated circuit, (IC) was designed,
which is consisting of a number of transistors. From here, a lot of devices have
been produced for many applications such as for automotive, telecommunication
and security and alarm as well as for medical treatment. Besides, a lot of
sophisticated gadgets have been introduced such as notebook, iPad, smart phones
and many more. Previously, it was obvious people only buy the electronic gadget
2
as a hobby or interest. But nowadays, it seems everything has changed and the
gadget is become a necessity in their routine life. In addition, the functionality of
the device is adorable and up to date.
Since today‘s generation concern with the latest invention of electronic
devices, the manufacturer has faced a great responsibility and challenges to make
their product more sophisticated, small and light in size, convenient, reliable,
higher processing speed, and lower power consumption with affordable prices
compare to previous one for the next following years . Normally, the
manufacturers will compete to market their product. To insure to stay ahead, they
will offer to the consumer a multifunctional devices features with reasonable
prices. A multifunctional device normally requires a very complex circuit in the
integrated circuit to enable the device system operate with high speed device and
low power consumption. Both of these two criteria would be the main concern for
the next product for all of electronic suppliers.
Figure 1.1: The numbers of transistors in Intel processor increased exponentially
throughout the years from 1960 to 2010 according to Moore‘s Law
3
The remarkable evolution of semiconductor from a single transistor to a
million of transistor packaging into a single chip was introduced by Moore‘s Law.
Moore‘s Law stated that the number of transistor in the IC is predicted to be
double for every two years which has begun since 1959 as shown in Figure 1.1. To
meet this requirement, scaling down the transistor is a must to ensure more
transistors can be incorporated into a single IC. Besides, more functionality can be
added and lead to a better device performance.
However, scaling down of MOSFET to nanometer scale results in major
challenges including simultaneously maintaining satisfactory drive current, Ion ,
reducing leakage current, Ioff, controlling short channel effect (SCEs), drain
induced barrier lowering (DIBL), carrier or electron surface scattering and velocity
saturation may severely affect and degrade the performance of this device.
According to the International Technology Roadmap for Semiconductor (ITRS,
2011), it pointed out some potential solutions and approaches to overcome
transistor scaling limitation such as initiation of new materials: carbon nanotube,
high-k dielectric, strain silicon and metal gate; new devices structures: vertical
MOSFET, multigates such as double gate, tri-gate, surrounding gate-all-around
(GAA) and FinFET.
4
Figure 1.2: International Technology Roadmap for Semiconductor (ITRS, 2011)
Multigates MOSFET such tri-gate has gain outstanding attention by the
researcher as evident growing numbers of publication in recent year. TCAD tools
seem help the researcher to analyze the multigates device behavior in a short time.
Moreover, it also can reduce time to the market for the device as a result it can
fulfill the demand by the industry and consumer. This research work will focus on
the simulation and characterization of silicon nanowire with high-k insulator
behavior based on the three dimensional, (3D) geometry effect of the channel, by
using TCAD tool.
5
1.2 Problem Statements
The downsizing of channel length in a planar MOSFET leads to several
disadvantages. Therefore, the conventional devices' modeling is no longer accurate
when the channel lengths reach the nanometer scale due to the numerous unknown
parameters. As a result, silicon nanowire tri-gate transistor with high-k (HfO2)
insulator is the potentially one of the alternatives to overcome all the scaling issues
specifically on leakage current, Ioff. It can be seen in Figure 1.2 that the latest trend
is FinFET (double gate) MOSFET with channel length 22nm, with silicon
nanowire tri-gate transistor structure channel length can be further shrinks to
20nm.
Figure 1.3: Technology trends on MOSFET (Jakub Kedzierski, 2011).
Hence, the proposed model of silicon nanowire tri-gate transistor with high-k
insulator is following the trends. Silicon nanowire ideal structure, gate-all-around
(GAA) is the benchmark of proposed model. Since GAA has numerous
advantages: excellent gate control; high Ion/Ioff ratio; suppressed leakage current
and high drive current.
6
Here are the questions that are bound to be answered throughout the research:
a. How to maintain high drive current, Ion?
b. What is the relationship of corner effect in silicon nanowire tri-gate with
transistor structure?
c. How to minimize the leakage current?
1.3 Research Objectives
The research focus on analytical analysis by structure and not by process of
silicon nanowire transistor model using 3D Sentaurus TCAD tool and MATLAB
software is utilized to evaluate the performance of the model. On the whole the
objectives of this research are:
(i) To model silicon nanowire tri-gate transistors with oxide (SiO2) layer and
high-k (HfO2) insulator layer.
(ii) To simulate the device performances based on the model designed for
both silicon nanowire tri-gate transistor with oxide (SiO2) layer and high-
k (HfO2) insulator layer.
(iii) To characterize the electrical properties of silicon nanowire tri-gate
transistor with oxide (SiO2) layer and high-k (HfO2) insulator layer.
(iv) To analyze and compare device performance between tri-gate transistor
with oxide (SiO2) and high-k (HfO2) insulator layer.
7
1.4 Research Scopes
This research scopes cover the analytical modeling of 3D silicon nanowire
tri-gate transistor, simulation of two difference models (silicon nanowire with
oxide (SiO2) layer and silicon nanowire tri-gate with high-k (HfO2) insulator layer)
and comparison of the result from both models. The scopes of the research briefly
explain as follows:
(i) Implement the structure of silicon nanowire tri-gate transistor with oxide
(Si02) layer and high-k (HfO2) insulator layer using 3D simulator tool(
Sentaurus TCAD software)
(ii) TCAD simulation for silicon nanowire tri-gate transistor by including
the corner effect on the channel. The channel length used as the starting
point is 65nm (validation).
(iii) MATLAB graph plotting for I-V curves extraction for each design.
Analyzing the performance based on specified electrical properties.
(iv) Comparing the device performances of silicon nanowire tri-gate transistor
with oxide (SiO2) layer and silicon nanowire tri-gate with high-k (HfO2)
layer.
1.5 Thesis outline
The outline of thesis begins with introduction and general background
reviews and reasons to conduct this research as can be found in Chapter 1.
The literature review and theory of silicon nanowire tri-gate transistor are
performed in Chapter 2.
8
It establishes new insights on one-dimensional physics, which provides a
foundation to the rest of the proposal. Methodology part will take place in Chapter
3 in which the research activities will be described in details. The findings and
discussion of the research will be demonstrated in the following section, Chapter 4.
Finally, the findings of the current achievements will be summarized in conclusion
section.
CHAPTER 2
LITERATURE REVIEW
2.1 Introduction
The basic principle of transistor was first patented by Julius Edgar
Lilienfeld in 1925. Twenty five years later, when Bell Telephone attempted to
patent the junction transistor, they found Lilienfeld already holding a patent which
was worded in a way that would include all types of transistors. Bell Labs was able
to work out an agreement where Bell Labs transistor patent was given the name
bipolar junction transistor, (BJT), and Lilienfeld's design took the name field effect
transistor. Then, in year 1959, Dawon Kahng and Martin M. (John) Atalla at Bell
Labs invented the metal–oxide–semiconductor field-effect transistor (MOSFET) as
an offshoot to the patented FET design which has become a pioneer in transistor
world.
10
2.2 MOSFET scaling
The MOSFET has continually been scaled down in size; typical MOSFET
channel lengths were once several micrometers, but modern integrated circuits are
incorporating MOSFETs with channel lengths of nanometers. Robert Dennard's
work on scaling theory was pivotal in recognizing that this ongoing reduction was
possible. Hence, Intel began production of a process featuring a transistor with 32
nm channel length in late 2009. The semiconductor industry maintains a
"roadmap", the ITRS,[20] which sets the pace for MOSFET development. The
main purposes of scaling down transistor are to pack more transistors per chip,
reducing fabrication cost, and elevate overall devices performance. However, the
reduction of MOSFET size has cause complication on semiconductor device
fabrication process (discuss further in section 2.1.3).
2.3 MOSFET scaling issues
Producing MOSFETs with channel lengths beyond micrometer
(nanometer) is a challenge, and will lead to several issues.
11
2.3.1 Higher subthreshold conduction
As MOSFET geometries shrink, the voltage that can be applied to the gate
must be reduced to maintain reliability. To maintain performance, the threshold
voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced,
the transistor cannot be switched from complete turn-off to complete turn-on with
the limited voltage swing available; the circuit design is a compromise between
strong drive current, Ion and low leakage current, Ioff. Subthreshold leakage can
contribute to increment of total power consumption. [22]
2.3.2 Increased gate oxide leakage
The gate oxide, which serves as insulator between the gate and channel,
should be made as thin as possible to increase the channel conductivity and
performance when the transistor is on and to reduce subthreshold leakage when the
transistor is off. However, with current gate oxides with a thickness of around 1.2
nm as shown in Figure 2.1(a) the quantum mechanical phenomenon of electron
tunneling occurs between the gate and channel, leading to increased power
consumption.
Silicon dioxide has traditionally been used as the gate insulator. Silicon
dioxide however has a modest dielectric constant. Increasing the dielectric constant
of the gate dielectric allows a thicker layer while maintaining a high capacitance
where capacitance is proportional to dielectric constant and inversely proportional
to dielectric thickness. Higher dielectric thickness can reduces the quantum
tunneling current through the dielectric between the gate and the channel.
12
Insulators that have a larger dielectric constant than silicon dioxide is high-k
dielectrics, such as group hafnium dioxide, HfO2 and zirconium silicates are being
used to reduce the gate leakage from the 45 nanometer technology node onwards.
Figure 2.1: (a) Silicon dioxide gate dielectric structure,
(b) Potential high-k dielectric structure
2.3.3 Increased junction leakage
To make devices smaller, junction design has become more complex,
leading to higher doping levels, shallower junctions, "halo" doping and so
forth,[23][26] all to decrease drain-induced barrier lowering To keep these
complex junctions in place, the annealing steps formerly used to remove damage
and electrically active defects must be curtailed[24] increasing junction leakage.
Heavier doping is also associated with thinner depletion layers and more
recombination centers that result in increased leakage current, even without lattice
damage.
13
2.3.4 Short Channel Effect
A short channel effect is a key or indicator of limitation of device scaling.
The aims of scaling are to reduce the size of transistor in order to integrate more
transistors into a single chip to achieve low power dissipation per function,
increased speed and function density of transistors (Dennard, 1997)[6]. The degree
of worsening short channel effect can be seen obviously from these effects such as
channel length modulation, drain induced barrier lowering (DIBL), threshold
voltage roll-off, velocity saturation, punch-through, impact ionization, hot carriers,
source drain series resistance, gate induced drain leakage (GIDL), band to band
tunneling, poly-Si depletion and quantum effects. However, only several effects
will be discussed extensively which related with the models development and
simulation work.
2.3.5 Channel Length Modulation
Fig 2.2: An effective channel length modulation at saturation mode.
14
Originally, the channel length, L is assumed as a constant in ideal case of
the current-voltage model. However, this consideration is not valid when MOSFET
is biased in the saturation region. Under this condition, the depletion region (∆L) at
the drain terminal extends laterally into the channel, thus, the effective channel
length getting smaller. The depletion region width is bias dependent; it also makes
the effective channel length (Leff) modulated by the drain to source voltage. This
phenomenon is called as channel length modulation as shown in Fig 1. The
importance to this effect is clearly visible when the actual channel length is
reduced by a factor of Leff =L-∆L. This lead to a shorter channel length and
increased the drain current. Ignorance of this situation can cause an existence of
uncertainty because Leff is a very crucial parameter for characterization and
optimization, SPICE model extraction and manufacturing control (Chung et
al.,1999)[7]. In standard MOSFET, the general views can be seen from channel
length modulation is shown in Figure 2.3.
Fig 2.3: A comparison between ideal curve MOSFET and MOSFET with
channel length modulation effect.
0 5 10 15 20 25 300
0.5
1
1.5
2
2.5
3x 10
-3
Drain Voltage,VDS
(V)
Drain
Cu
rren
t, I
D(A
)
Simulated data with Channel Length Modulation Effect
Ideal Curve MOSFET
15
2.4 Alternatives and Potential Solutions to Overcome Scaling Issues
In order to overcome scaling issues encountered, there are potential
solution such as the introduction of new materials and new structures. All these
potential alternatives are being applied by researcher were shown in technology
trends of MOSFET. Since 2001, when bulk MOSFET was fabricated with the
technology node of 130 nm by Intel as Under this technology, the device was
produced using gate length and oxide thickness of 60 nm and 1.5 nm respectively
(Thompson et al[10]., 2001). An attempt to reduce the oxide thickness from 1.5
nm to 1 nm (30%) was failed when gate leakage current increased up to 100 A
[11](Lo et al., 1997). From these result, gate oxide thickness cannot be scale down
as the next technology node.
Then, strained silicon a new material of transistor was reported within a
year 2003 as the 90nm technology node (Thompson et al., 2004; Ghani et al[12].,
2003). In this technology, an oxide thickness and gate length were defined as 1.2
nm and 45 nm .The effect an incorporation of strain into silicon could alter the
mobility as well as improve device performance. Uniaxial longitudinal stress is
very convincing in enhancing the performance. In the following two years, a
65nm technology node was presented where the gate length is reducing to 35 nm.
The achievement in this node is better compared than the former node with
installation of enhanced strain layer [13](Bai et al., 2004). A high k-metal and
metal gate were introduced in the 45 nm technology node using the oxide
thickness of 1 nm (Mistry et al., 2007)[14]. A second generation of a high-k
metal gate was reported with 32 nm technology node (Jan et al., 2009; Jan, et al.,
2009; Packan, et al., 2009)[15-17]. In order to enable downscaling for the next
node, an implementation of high-k is an inevitable. A great performance from
this technology node was a rectification of Idsat, Idlin as well as highest drive
currents from the past node ( Mistry et al., 2007 ; Packan, et al., 2009; Auth, et
al., 2008 ) .
16
The latest technology node was completely different from previous
device and node, where the device was created based on a new structure,
FinFET; one of the high achievements among the existence technology node
with excellent performance. Besides, the gate length also reported as the
smallest. The outcome of every technology node explained earlier only could be
achieved through the research work. Thus, a continuous improvement needs to
perform so that the device for the next technology node can be prepared better
and enhanced from the existence node.
2.5 Silicon Nanowire
2.5.1 Silicon Nanowire Structure
Silicon nanowire FETs are more appealing than the conventional Double
Gate (DG) FETs because of its higher on-current conduction due to their quantum
nature and its adoptability for high density integration including that of 3D.
Figure 2.4: Schematic representation of different architecture silicon nanowire
MOSFET (K. Henari et. al, 2005).
17
Silicon nanowire transistors offer better gate control and more flexibility
in device design (Lundstorm and Jing Guo, 2006) when comparing with planar
double-gate (DG) MOSFETs. Figure 2.5 shows the evolution of multiple-gate
transistors schematically in the order of increasing gate electrostatic control.
Apparently, the tri-gate structure is the better resistant to short-channel effects than
FinFET device structures for given silicon body thickness. The reduction in
channel 11 width and thickness can further increase the effectiveness of the gate
control and become major candidate for extreme CMOS scaling process
complexities.
Figure 2.5: Progression of device structure from single-gated planar to
fully GAA NW MOSFETs (Navab Singh et al, 2008)
There have been several experiments that demonstrated the advantages of
tri-gate gaining short-channel control as thin-body double-sided FinFET, excellent
drain-induced barrier lowering (DIBL) suppression, better on current and leakage
current. Tables 1 indicate the DIBL suppression effect for a given architecture of
nanowire. Furthermore, the cylindrical geometry gives inverse logarithmic
dependence of the gate capacitance on the channel diameter; the gate length in
these devices can be scaled with wire diameter without reducing the gate dielectric
thickness (Navab Singh et. al, 2008).
18
Table 2.1: Comparison of nanowire MOSFETs
2.5.2 Silicon Nanowire Electrical Properties
Many theoretical works have been reported to investigate the behavior of
electron transport silicon nanowire. The electronic properties of silicon nanowire
could be altered using the following methods such as introducing the dopant,
varying the diameter, surface reconstruction as well as passivating the surface.
[65](Muller et al., 1986) observed that the additional dopants into lattice structure
could enhance the carriers transport. These dopants either donor or acceptor
actually act as catalyst to increase the stability of atomic bonding by making them
more stable. The band gap of silicon nanowire is found to be reduced with the
increment of diameter as well as surface reconstruction (Vo et al., 2006)[66].
Surface reconstruction is referring to the shape of silicon nanowire cross section
during the growth process. Silicon nanowire with orientation <110> is believed
can behave as metallic or semi-metallic depending on its surface reconstruction
[67](Rurali, 2010).
19
Surface passivation in SNWs occurred due to the growth of insulator
layer by thermal oxidation and the existence of hydrogen atom during growth
process ( Zhong et al., 2003)[68]. Such technique was proven can improve the
mobility of SNW as reported by (Cui et al., 2003)[69].
2.5.3 Fabrication process of Silicon Nanowire
Silicon nanowire transistor have recently gained a great attention, due to
their wide potential to implement as nanoscale electronics device [70]( Cui &
Lieber, 2001)[71]. This statement also agreed by (Singh et al., 2006)[72] when
their findings in such device exhibit a good device performance in terms of drive
current, ideal subthreshold slope (SS), low DIBL, and high ION/IOFF.
Normally, silicon nanowire transistor is synthesized using ―top-down‖ or
―bottom up‖ approaches. For ―top-down‖ approach, silicon nanowire growth using
electron beam lithography (EBM) meanwhile for ―bottom up‖ approach, vapor
liquid solid (VLS) and chemical vapor deposition (CVD) underlying under this
method. Each method will be discussed at length in the next section.
20
2.5.4 Relationship between current and voltage of silicon nanowire
transistor
The best way to explain the silicon nanowire is a new structure device
based which has an outstanding electrical characteristics such as high mobility,
high on drive current and the most important key is downscaling process could be
proceed much further with desired size and performance [ 1-6 ]. Eventually, such
device is still using the silicon as common material in fabrication process. The
ultimate goal in modeling is to develop drain current model in order to see either
the device could be implemented as a device through the critical analysis on its
performance. The drain current model for SNW contains two different regions
which are saturation region and linear region. The drain current in saturation is
given as ( Ahmadi et al., 2009)
𝐼𝐷𝑠𝑎𝑡 = 𝐶𝐺 𝑉𝐺𝑇 − 𝑉𝐷𝑠𝑎𝑡 𝑣𝑠𝑎𝑡 (2.1)
where 𝐶𝐺 ,𝑉𝐺𝑇 , 𝜐𝑠𝑎𝑡 respectively are the gate capacitance, gate voltage and
saturation velocity. Gate capacitance for cylindrical is calculated as followed:
𝐶𝐺 = 2𝜋ɛ𝑖𝑛𝑠
ln 𝑅𝑖𝑛𝑠
𝑅𝑤𝑖𝑟𝑒 (2.2)
The variables such 𝑅𝑖𝑛𝑠 , 𝑅𝑤𝑖𝑟𝑒 are represent as radius of insulator and channel
correspondingly. The drain voltage at saturation regime is denoted as (Ahmadi et
al., 2009)
𝑉𝐷𝑠𝑎𝑡 = 𝑉𝑐 1 +2𝑉𝐺𝑇
𝑉𝑐− 1 (2.3)
where 𝑉𝑐 is the critical voltage and defined as 𝑉𝑐 = (𝜐𝑠𝑎𝑡 / 𝜇0)𝐿 .
21
A drain current model in linear region is formulated as
𝐼𝐷 =𝐶𝐺𝜇𝑙𝑓
2𝐿 2 𝑉𝐺𝑆 − 𝑉𝑇 𝑉𝐷 − 𝑉𝐷
2
1 +𝑉𝐷
𝑉𝐶
(2.4)
where 𝜇𝑙𝑓 is the mobility of electron that is correlated to the mean free path. Thus,
a final view on the current-voltage curve is demonstrated in Figure 2.6.
Linear region
Saturation region
Figure 2.6: Drain current versus gate voltage for Silicon Nanowire
(Ahmadi et al., 2009)
22
2.6 Tri-gate MOSFETs
2.6.1 Tri-gate structure
Tri-gate structure is more promising in comparison to the double gate
structure, not only due to its favorable electrical behavior, yet has a simple and
low cost of fabrication method ( Wong et al., 1997; Doyle et al., 2003)[25, 36].
Moreover, the manufacturing process of the device is compatible with CMOS
technology. The first tri-gate process was invented by (Doyle et al., 2003) as
shown in Figure 2.7. The inventors even have patented their findings as intellectual
properties (Chau et al., 2009)[37]. Their works have inspired many researchers
with rapid number of publications for further development in such device (Breed
et al., 2003; Chau et al., 2005; Thean, et al., 2006; Haensch et al., 2006; Bernstein
et al., 2006; Moselund et al., 2006; Lee et al., 2007; Garcia et al.,2007; Ernst et al.,
2007; Jin et al., 2007) . [35, 38-46] In this experiment, the device was fabricated
for the gate length of 60 nm, meanwhile silicon fin width and height respectively
55 nm and 36 nm. Firstly, the formation of body fin was prepared using the same
method as poly-silicon gate. Aggressive poly-silicon lithography and etching
techniques were used in order to have the fin width similar to gate length. Next, a
conventional boron implant was implemented to achieve desire threshold voltage.
The oxide layer was formed on the top of body fin with thickness of 1.5 nm. To
reduce parasitic resistance, raised source and drain were introduced. The formation
of contact surface for source, drain and gate were silicided using metal such nikel.
In overall, an important findings from this process is a fully depleted device could
be achieved with excellent electrical performance of Subthreshold Swing(SS) ,
Drain Induced Barrier Lowering(DIBL) , the on state current ( ION ) and the off
state current ( IOFF.).
23
Figure 2.7: Illustration of (a) TEM cross section of N-MOS Tri-gate structure
(b) 3-Dimensional of Tri-gate structure (Doyle et al., 2003).
Another fabrication process was proposed by (Landgraf et al., 2006) [47]
with body doping and influence of crystal orientation as the subject of the analysis.
SOI substrate was prepared by staking the 50 nm silicon above the buried oxide
layer with thickness of 100 nm. Next, the body fin was doped with boron, with
doping concentration of 2 × 1015 cm−3. Then, the silicon body was patterned with
the hardmask layer using e-beam lithography and plasma etching ( Kretz et al.,
2003)[48]. To round the corner, a sacrificial oxide was used to vary the silicon fin
surface. Before hand, the hardmask was removed in order to grow the insulator
(SiO2) on the top layer of silicon fin. The process of gate formation includes such
phosphorus deposition and patterned using e-beam mask. The spacer was
deposited and etched anistropically with material of SI3N4 and thickness of 20 nm.
To form raised source and drain, 60 nm of epitaxially silicon was grown. The
corresponding region was doped with arsenic using annealing method and
temperature of 1000C.Finally, metallization was used to form contact for source,
drain and gate.
(a) (b)
24
In overall, the fabrication process as described earlier do not emphasized
much about the consequence of corner effect toward performance analysis.
However, corner effect is of the important issue need to look into a consideration
because the effect has major connection with the I-V characteristic of the device
[25](Doyle et al., 2003). In the next section, several methods that have been used
to reduce such effect will be discussed extensively.
2.6.2 Corner Effect in Tri-gate Structure
Published works have highlighted the advantageous of tri-gate as future
device (Poiroux et al., 2005; Kavalieros et al., 2006 ; Doyle et al., 2003; Sun et al.,
2008 )[49-52], instead of their benefits, multi-gates can give different values in
threshold voltage (Ritzenthaleret al., 2006) [53]. This variation can affect the
electrical characteristic of the device. Based on Figure 2.8, originally the device
(Pi-Gate) has two maximum points which are represent two different sets of
threshold voltage. This phenomenon called as corner effect. Nevertheless, when
the device is subjected to different corner effect reduction methods, the threshold
left as a single value.
25
Figure 2.8: Corner effect reduction methods using Pi-Gate device as a reference
(Ritzenthaler et al., 2006).
Several alternatives were proposed to reduce corner effect. According to
(Fossum et al., 2003)[54], they suggest that the fin body should be left undoped in
order to minimize the corner effect. The two-dimensional (2D) numerical
simulation was used to perform the analysis. Figure 2.9(a) shows the three
dimensional (3D) of tri-gate meanwhile Figure 2.9(b) describes the cross section of
tri-gate with the corner region included through this analysis. Eventually, this
technique only applicable for the device beyond 50 nm and low threshold voltage
application due to the changes of impurities position (Dollfus et al.,2004) [55].
26
Figure 2.9: The architecture of (a) 3-D of Tri-gate (b) Cross section of 3-D tri-
gate include the corner region
2.7 High-k dielectric
Silicon dioxide has been used as a gate oxide material for decades. As
transistors have decreased in size, the thickness of the silicon dioxide gate
dielectric has steadily decreased to increase the gate capacitance and thereby drive
current, raising device performance. As the thickness scales below 2 nm, leakage
currents due to tunneling increase drastically, leading to high power consumption
and reduced device reliability. Replacing the silicon dioxide gate dielectric with a
high-κ material allows increased gate capacitance without the associated leakage
effects.
(a) (b)
27
The gate oxide in a MOSFET can be modeled as a parallel plate capacitor.
Ignoring quantum mechanical and depletion effects from the Si substrate and gate,
the capacitance C of this parallel plate capacitor is given by
𝐶 =𝑘𝜀0𝐴
𝑡 (2.5)
Conventional silicon dioxide gate dielectric structure compared to a potential high-
k dielectric structure. Where A is the capacitor area, κ is the relative dielectri
constant of the material, ε0 is the permittivity of free space and t is the thickness of
the capacitor oxide insulator. Since leakage limitation constrains further reduction
of t, an alternative method to increase gate capacitance is altering κ by replacing
silicon dioxide with a high-κ material. In such a scenario, a thicker gate oxide layer
might be used which can reduce the leakage current flowing through the structure
as well as improving the gate dielectric reliability.
2.7 Summary
Multigate such as double gate, tri-gate, surround gate, and FinFET have
been studied rigorously as potential successor of MOSFET. Besides that, high-k
material such as hafnium dioxide has been introduced to replace oxide layer.
Following that, the designed model; silicon nanowire transistor with high-k
insulator is relevant to recent technology trends with channel length variation
down to 22nm.
28
In addition, design approaches of model are different from published
work where implementation using three-dimensional (3D) Sentaurus TCAD tool,
advanced version of SILVACO and the design process is by structure and not by
process. Contributions of this design model as compared to published work are
on structure, device optimization based on parameter variation and analysis.
CHAPTER 3
RESEARCH METHODOLOGY
3.1 Introduction
This chapter focused on the method use to virtually fabricate of silicon
nanowire tri-gate transistor with high-k (HfO2) insulator using Sentaurus‘s TCAD
tools. The overall process flow for SNWTT are shown and discussed in details.
3.2 Research Activities
The aim of this research is to model and analyze a silicon nanowire tri-
gate transistor with high-k insulator.
30
This includes the studies and development of low leakage current and
high driving current, effective mobility, thermal effect, doping concentration and
finally the I-V characteristics of a three-dimensional (3D) silicon nanowire tri-gate
transistor model. The main challenge is to validate the model with the
experimental data as 3D modeling with Sentaurus TCAD tool is considered as a
new-emerging approach of silicon nanowire tri-gate transistor with high-k
insulator and research is still rapidly taking place so far. Therefore, data extracted
from Sentaurus TCAD tool will used for I-V curve plotting via MATLAB. The
plotted I-V curves will be compared with reference model as well as comparison
with silicon nanowire tri-gate transistor with tri-gate transistor. Basically, the
research activities consist of three components which are:
1. Literature review, which includes the studies of published material
and resources.
2. Modeling silicon nanowire tri-gate with high-k insulator and
silicon nanowire tri-gate with oxide layer.
3. Modeling the development of low leakage current and high driving
current, effective mobility and finally the I-V characteristics
4. Numerical simulation and comparison with model or experimental
data via MATLAB.
5. Optimization of the model until satisfying result is achieved.
3.3 Modeling approach
In implementing a silicon nanowire tri-gate transistor structure, full
process flow using a commercial three-dimensional (3D) technology CAD
(TCAD) tool is used.
31
The simulation is based on and refers to the modeled tri-gate FET
devices. Using our real process flow, various process simulation parameters from
activation models are first calibrated to the experimental data. Device simulations
are then performed with varying doping, channel width, channel height and length,
and box thickness.
Sentaurus-Process and Sentaurus-Device simulators from Synopsys [23]
have been used in this work because of its 3D process and device capability and
the compatibility to the mainstream 2D TCAD framework TSUPREM4/ MEDICI
(also from Synopsys) which has been well calibrated to all advanced CMOS logic
technologies. The critical process steps for tri-gate FET on standard SOI are gate
oxide growth, gate formation, and source-drain implant before final annealing .All
necessary thermal steps have been excluded in the process simulation.
3.3.1 MATLAB
A MATLAB (version 2008) tool is widely used by different background
peoples such as student, engineer and even professional in order to simulate the
numerical models. The simulator enables the users to perform computationally
tasks faster than traditional programming languages such as C, C++ and Fortran.
By simulating the model, numerous types of graph can be generated. In addition,
from those graphs, a critical analysis can be attained. The research framework in
Chapter 4 will be conducted using this simulator.
32
3.3.2 SENTAURUS TCAD
Sentaurus is classified as one of the Technology computer aided design
(TCAD) which accommodate a user friendly and convenient tools for
semiconductor devices. The tools comprises of Process Simulation, Structure
Editing and Device and Interconnect. Both of the Process Simulation and the
Structure Editing are provided to develop the actual wafer fabrication process
virtually. Meanwhile, Device and Interconnect tool, it can be used to characterize
and extract the electrical properties.
TCAD tools are crucial for semiconductor industry which usually faced
with time and cost constraints. Requirement of high speed device with advanced
technology may be the reason for the semiconductor always exposed to the
technology innovation. The advantages of TCAD tool are reduced time and cost
consuming for technology development. Besides, it also compatible with fast
prototyping, development and optimization of semiconductor technology
(Synopsy,2012) ("Modules of Sentaurus TCAD Industry-Standard Process and
Device Simulators at "). The tools also occupied with the physics modeling
capabilities. Not only is that, the tools flexible to execute for multidimensional
devices such as two dimensional (2-D) and three dimensional (3-D) devices. Thus,
Sentaurus TCAD will be used to carry the researches aims.
33
3.4 The SNWTT Modeling
3.4.1 Fermi-Dirac Distributions
The function of 𝑓(E) is called as Fermi-Dirac Distribution which
provides the probability that a quantum state at energy E will occupied by the
electron expressed as (Lau, et al., 2008) [82]
𝑓 𝐸 =1
𝐸 − 𝐸𝐹
𝑒𝑘𝐵𝑇+1
(3.1)
where 𝑓 E , EF , kB , T respectively represent as the occupation probability of a state
of energy E , Fermi energy, boltzmann‘s constant and temperature. This
distribution explains the probability of electron to occupy the empty state at certain
energy, E, and temperature, T. Fermi-Dirac Distribution can be approximated in
two different conditions either degenerate or non degenerate state. For degenerate,
when the energy of electron is equal to energy of electron at Fermi level (E = EF) ,
the probability of electrons is calculated as ½. However, in Maxell-Boltzman (non-
degenerate) approximation, another form of Fermi direct can be clarify as
𝑓 𝐸 =1
𝐸 − 𝐸𝐹
𝑒𝑘𝐵𝑇
= 𝑒−𝐸−𝐸𝐹𝑘𝐵𝑇 (3.2)
where ‗1‘ in the denominator in equation (2.6) can be neglected since the Fermi
energy is below the conduction band (Neamen, 2003)[83]. In this case, the
probability of electrons is estimated as 1 when E = EF.
34
3.4.2 Analytical Model for Silicon Nanowire Transistor
Figure 3.1: Schematic diagram for silicon nanowire transistor
In the beginning of modelling, a development of silicon nanowire
transistor started from fully cylindrical nanowire transistor where the structure is
assumed have the same behaviour as gate all around for comparison the data. It is
done since there is no fabrication yet reported for the proposed structure. In order
to create a model that reflect to silicon nanowire transistor structure, new
capacitance model for its structure was designed; an approximation method was
implemented based on capacitance model for gate all around silicon nanowire .
One dimensional drain current has been implemented which is a function of drain
voltage, 𝑉DS and gate voltage, 𝑉GS in linear and saturation region by (Ahmadi et
al., 2009)[104]. For the linear region 𝑉𝐷𝑠 < 𝑉𝐷𝑆 (𝑠𝑎𝑡 ) drain current condition before
considering the CLM model is given by
35
𝐼𝐷 =𝜇𝐿𝐹𝐶𝐺
2𝐿
2 𝑉𝐺𝑆 − 𝑉𝑇 (𝑉𝐷𝑆 − 𝑉𝐷𝑆2)
1 +𝑣𝐷𝑆
(𝑉𝑠𝑎𝑡
𝜇𝐿𝐹 )
(3.3)
where 𝜇𝐿𝐹 is the mobility of electrons under low electric field (equation 4.7),
𝑉𝑠𝑎𝑡 is the drift velocity in saturation region for degenerate regime (Vijay,1985;
Ahmadi et al., 2009), L is the channel length of device and CG is the gate
capacitance per unit length. For device that operates at the saturation region
𝑉𝐷𝑠 ≥ 𝑉𝐷𝑆 (𝑠𝑎𝑡 ), the drain current before implementing CLM model can be
simplified and expressed as
𝐼𝐷𝑠𝑎𝑡 = 𝐶𝐺 𝑉𝐺𝑇 − 𝑉𝐷𝑆 𝑠𝑎𝑡 𝑣𝑠𝑎𝑡 (3.4)
Gate capacitance per unit length for fully cylindrical structure is presented as
(Lundstrom and Guo, 2006)[105]
𝐶𝐺 = 2𝜋𝜀𝑜𝑥
log(𝑡𝑖𝑛𝑠 + 2𝑡𝑠𝑖
𝑡𝑠𝑖) (3.5)
where 𝜀𝑜𝑥 is the permittivity of an insulator . The thickness value for both
insulator (tins) and silicon (twire) are 10nm and 5nm respectively. Gate
capacitance for Silicon Nanowired FinFET is developed based on approximation
of gate capacitance of gate all round. Given that gate capacitance for respective
structure is given as
𝐶𝐺′ = 𝑛𝐶𝐺 (3.6)
Where n is the ratio of gate capacitance between 70 percent of omega shape and
fully cylindrical that was approximated as 0.86 (L. Yiming et al.,2005)[106] .
36
The equations for drain to source current for both saturation and linear region after
consideration of channel length modulation effect are simplified as ( Hamid, et al.,
2013)
𝐼𝐷′ = 𝛼𝐼𝐷 (3.7)
𝐼𝐷𝑠′ = 𝛼𝐼𝐷𝑠 (3.8)
3.4.3 SNWTT modeling Overview
Generally, the device model is essential method before any device is
implemented in electronic circuit or system. This model is used to study and
predict the device‘s behavior based on carrier transports of electrons, current-
voltage and capacitance voltage characteristics. From here, the electrical
characteristics could be extracted and determine the operation range of the devices.
Normally, these data can be found in datasheet of any semiconductor vendors such
as Intel.
According to Arora, there are two types of device model which are physical device
models and equivalent circuit models (Arora, 2007). Physical device models
normally developed based on transport equations, device geometry, technological
parameters, temperature effects, doping profile and material characteristic (Arora,
2007; Montoro and Schneider, 2007). Even though the model is rarely and not
favorable to used, but, it is useful to investigate the electrical behavior, optical
device and thermal properties.
37
A compact model which also known as equivalent model circuit is consist
of a collection of mathematical equations whose variables are used as an input to
a SPICE-like circuit simulators [7]. The mathematical equation which works
similar as physical mechanism is estimated to be able to extract the electrical
characteristics of a device for different physical dimension, temperature and
process variation [41-46]. This model is more favorable compared to physical
device because the model is normally can be transferred directly to the circuit
application.
The model of this research framework involved with the physical
modeling device. Even though this model takes time to develop; the data obtained
through the model can be used as preliminary views to the device characteristics.
Figure 3.1 shows the research flow of Silicon Nanowire Tri-gate Transistor
modeling. The research activities begin with the literature reviews of Silicon
Nanowire Tri-gate Transistor with high-k insulator which required reviewing the
works that related to the published materials. The literature understanding includes
the carrier statistic, velocity, mobility and I-V curve. The former research work
that associated with research scope also been summarized in Chapter 2 in order to
identify the research gap.
Next, the modeling of I-V of SiNWTT were performed which
incorporated with various parameter; doping concentration, temperature, channel
length and radius of channels. The command scripts for these models then
extracted using Sentaurus Process and it can be edited according to necessity.
After a complete command is written and executed on this file, the output file in
form of graph is generated. In order to make a comparison for varied parameter all
the data from graph generated in TCAD are copied to MATLAB editor so that all
can be plotted n the same graph.
38
From here, the current-voltage proposed SNWTT model then compared with the
published model. If there is no divergence or error, an extensive analysis could be
carried out.
The next stage is the analysis of results obtained from the models after a
comparison with published model. In this work, significant findings from those
variations will be discussed in details in Chapter 4
39
Figure 3.2: Methodology for Silicon Nanowire Tri-gate Transistor modeling
No
Yes
Start
Literature
review
Silicon Nanowire Tri-
gate transistor with oxide
layer implementation
using Sentaurus TCAD.
Silicon Nanowire Tri-
gate transistor with High-
k insulator
implementation using
Sentaurus TCAD. I-V characteristics
(MATLAB)
Result analysis
Analyzing and
comparing the device
performance based
on the graph of
parameters
extraction.
Acceptable Design
improvement
performance
optimization. Finish
40
3.5 A development of Silicon Nanowire Tri-gate
TCAD is listed as physical modeling device tools which simulating the
device based on certain underlying physic concept such as carrier statistic, mobility
and impact ionization of electrons. Numerous of physical model tools that
available nowadays such as PISCES, Atlas, and Synopsys are designated based on
finite element method (Duane, 2002)[98]. Sentaurus TCAD is one of the
applications provided by the Synopsys company. The tools can be used to cut cost
and speed up the research and process development when developing a new
semiconductor device. As the technologies become more advanced and complex,
the semiconductor manufacturers relies increasingly more on TCAD tool. TCAD is
more preferable to implement on the latest technology due to less time and cost
consuming on the production.
The simulation work for silicon nanowire tri-gate transistor was
performed mainly using the Sentaurus TCAD tools. This simulator consists of
three types of device application which are fabrication, structure and device
simulator. Fabrication and structure can be used to design the new structure either
in 2-D or 3-D. However, the recent trends show the structure for semiconductor
device gets complex. For this case, the structure simulator can be used to prepare
for such device. In order to extract the device characterization, finite element
method which known as mesh need to define early. Mesh definition is important to
ensure the accuracy of result yield for analysis the device performance.
In device simulator, the most important thing is to nominate the
appropriate the physical device model. A right model nomination will help to
increase the accuracy of result. Thus, a different model will produced a different
result for device characterization.
41
There are five categories of physical models in device simulator offered
by the Synopsys: carrier statistics, mobility, impact ionization, recombination, and
tunneling model.
From the previous literatures that have been discussed in Chapter 2, the
simulation of fabrication method of Tri-gate and Silicon Nanowire Tri-gate with
high-k insulator were gathered. The fabrication method used needs to ensure
compatible with the CMOS technology. Besides, knowledge and tools required for
device fabrication in TCAD can be found from the manual guideline provided by
the Synopsys. Before hand, Tri-gate and Silicon Nanowire Tri-gate were compared
to see the significant improvement in electrical characteristics. In this research,
the main work is to fabricate the Silicon Nanowire Tri-gate Transistor. The
fabricated of Silicon Nanowire Tri-gate then compared with published data which
has the similar structure such Tri-gate Nanowire using device simulation. From
this method, if the data obtained for fabricated device having the same trend as
published material, then the data analysis will be proceed. Data analysis will be
focusing on the enhancement of electrical properties for the proposed structure
through parameter variations.
The flow chart as shown in Figure 3.2 below summarizes all the
processes done in device simulation using the Sentaurus TCAD program from
beginning up to parameter extraction.
42
Figure 3.3: Flow chart for device simulation of silicon nanowire tri-gate
transistor, SNWTT
Device simulation start by loading the structure file created to Sentaurus
Workbench. There are several steps in device simulation in order to obtain the
SNWTT characteristics for further analysis. The output (IDS versus VDS curve) and
transfer characteristics (IDS versus VGS curve) for DP-MOSFET will be obtained
respectively. In addition, parameters extraction for VT, Ion/Ioff ratio, IOFF, IDsat,
DIBL and others will also be carried out.
Load Structure File
Created to Sentaurus
Workbench
Define Gate
Work Function
Set Material
Model
Choose Contact and
Interface
Characteristics
Select Biasing
Method
Set Different Drain Biases for Certain
Range of Gate Biases to Get the Plot
of Family Curve of IDS versus VGS
Using Log, Solve and Load
Statements
Obtain an Initial Solution
Created from ATHENA
Set Different Drain Biases for Certain
Range of Gate Biases to Get the Plot
of Family Curve of IDS versus VDS
Using Log, Solve and Load
Statements
Parameters extraction
Created from ATHENA
43
3.6 Summary
In this chapter, modeling approach, method, and tools used are being
discussed. The implementation of silicon nanowire tri-gate transistor using
Sentaurus is described in details including the fabrication process. Besides that,
tools used in the research such as Sentaurus TCAD and MATLAB are explained in
details. Flowchart for the whole research work also shown.
CHAPTER 4
CHARACTERIZATION OF SILICON NANOWIRE TRI-GATE
4.1 Introduction
As outlined in the literature reviews, multigate structure such as silicon
nanowire tri-gate offer a lot of advantageous due its good electrical properties
such as better electrostatic controlled and high drive on-current. Enhancement
and improvement of previous multigate structure is studied extensively through
this chapter. However, the main concern for the improvements is discussed in
term of its on-state current (Ion) where silicon nanowire tri-gate is better than
standard tri-gate. Silicon nanowire tri-gate where the channel is a way to control
leakage current and other parameters (SS, DIBL, Ion , Vth ) based numerous
parameter variation.
45
4.2 Silicon Nanowire Tri-gate Structure
A silicon nanowire tri-gate device is designed and simulated using a three
dimensional (3-D) tool known as SENTAURUS TCAD. Figure 4.1 demonstrates
the simulated device with all physical dimensions shown clearly. The device is
made up of silicon material based for both the channel and the substrate region.
Meanwhile for the insulator (silicon oxide) and the buried oxide regions, they are
created using silicon oxide. The gate device is formed using the poly-silicon
material. For channel region, the semi-cylindrical structure is used as a channel
with the radius of 9.5 nm. The width of channel is defined as two times of radius
that is set as 19 nm. The device also has the oxide thickness (tox1 = tox2) of 3 nm. A
lightly doped is chosen at the channel and the gate regions. On the other hand, a
heavily doped is applied at the source and drain region. For the substrate and
buried oxide, they are left as undoped region. All the physical geometries used in
the device are summarized in table 4.1.
Figure 4.1: Schematic diagram for Silicon Nanowire Tri-gate in (a) 2-
dimensional (2-D) (b) 3-dimensional (3-D)
Substrate
BOX
Silicon
Oxide
Gate
A=(pi/2)x(9.5nm)2
tsub
tBOX
tox1
tox2
tgate
(a) (b)
46
Table 4.1: Parameter values that have been used to build silicon nanowire
tri-gate transistor model.
Physical geometry Value
Gate length, Lg(nm) 65
Width of channel (diameter=2*
radius)(nm)
19
Height of channel (radius) 9.5
Channel doping, Nd ( cm-3
) 1e12
Gate doping, Ng ( cm-3
) 1e15
Source/drain doping ,NS/D ( cm-3
) 5e18
Oxide thickness,tox (nm) 3
47
4.3 Flow Chart of Device Fabrication for Silicon Nanowire Tri-gate
Transistor
2. Boron doped (100) Silicon wafer
3. P-type body – Boron implantation (8x1012cm-2, 100keV)
4. Diffuse using dry oxygen (50s,1000oC) & nitrogen gas (90s,1200oC)
5. Removal of growth Oxide
6. Well implantation (B) – to adjust VT
7. Gate oxide, TOX=5nm (800oC)
10. LDD extensions (Arsenic, 8x1013 at/cm2)
9. Deposit Oxide cap layer
8. Deposit PolySi Gate
11. 20nm Nitride spacer formation
12. Etching process, 70nm in the S/D region were formed
13. Selective epitaxy was carried out to fulfill the depression in the S/D
14. Implant HDD junctions with Arsenic (50keV, 5x1015 at/cm2)
15. Anneal with RTA (1000oC, 20s)
1. Mesh Definition
16. Metal Deposition and Contact Openings
18. Mirror the Structure and Name the Electrodes
17. Parameters Extraction
48
4.4 Result and Discussion
4.4.1 Tri-gate versus Silicon Nanowire Tri-gate
Figure 4.2.2 shows the I-V curve Silicon Nanowire Tri-gate designed and
reference Tri-gate of channel length LG=26nm. The graph was simulated by using
normalization method, where the current was normalized by the total of width of
channel and height of the channel. Normally, a standard tri-gate is defined as
structure in Figure 4.2.1(a).
Silicon
Oxide
Gate
Substrate
BOX
Substrate
BOX
Silicon
Oxide
Gate
(a) (b)
A=19nm x12nm
A=(pi/2)x(9.5nm)2
Figure 4.2.1: Structure of a) Tri-gate transistor b) Silicon Nanowire Tri-gate
transistor
An early assumption was observed where silicon nanowire tri-gate has
better electrical properties compared to tri-gate in term of off-state current trend.
On state current degradation facing by this device is not considerably high
compared to off-state current, thus, off-state current achievement is much
preferable to discuss in this analysis. From simulated result, off state current for
structure in Figure 4.2.1 (b) is much lower compared to standard structure
respectively with IOFF =9 μA and IOFF = 11μA .A significant reduction on off state
49
current is suspected contributed by the nature of structure that replicate as gate all
around but in semi-cylindrical form that offers better electrostatic control (electric
field) over the channel by the gate. Using this structure, off-state current could be
reduced by up to 50%. Originally, the trapped charge at the edge of corner in
standard tri-gate could contribute to a high leakage current during off-state
condition (M. P. Kumar, et al) and also known as corner effect. Corner effect is
believed to happen when the electric field line is not uniform and caused the
trapped charge at the corner (A. Godoy, et al). This problem can be minimized by
introducing the proposed structure in Figure 4.1(b). The rounding structure make
the uniform electrons distribution on the channel easily can be controlled by the
gate during the switching off period, which indicates a good controlled over the
electric field since the electric field line is uniform in this structure. Thus, it make
the device has smaller leakage current compared to tri-gate. In addition, even
though the channel for both structure were applied with heavily doped, but this
condition is seem to give more benefit on proposed structure. It is because the area
involved in fabricating for suggested structure is smaller than standard tri-gate,
thus cost of production be able to reduce efficiently.
Figure 4.2.2: I-V curve Silicon Nanowire Tri-gate designed and reference Tri-
gate (Gate length, Lg = 26nm; Vds = Vgs = 1V)
50
4.4.2 SNWTT with two different insulator layers
(a) (b)
Figure 4.3.1: (a) Silicon Nanowire Tri-gate Transistor with oxide layer structure,
(b) Silicon Nanowire Tri-gate Transistor with high-k (HfO2) layer structure
High-κ dielectrics are used in semiconductor manufacturing processes where they
are usually used to replace a silicon dioxide gate dielectric or another dielectric
layer of a device. The implementation of high-κ gate dielectrics is one of several
strategies developed to allow further miniaturization of microelectronic
components.
HfO2
layer
SiO2
layer
51
Figure 4.3.2: I-V curve for undoped high-k (HfO2) layer and undoped oxide layer
As can be seen in Graph 2, the two curves are noticeably different. I-V curve of
undoped high-k layer shows significantly lower leakage current as compared to
undoped oxide. The difference occurs due to the thickness of capacitor layer of
insulator. Since, HfO2 layer is thicker than SiO2, thus, leakage current HfO2 is
smaller. According to (Moshe Eizenberg, 2012) ,when the transistor size shrink,
thickness of SiO2 is reduced and will contributing in significant increase of leakage
current. These finding is supported with the publish work where high-k dielectric
has low leakage current, low loss factor and substantially higher permittivity than
SiO2.
52
4.4.3 Channel radius variation
(a) (b)
Figure 4.4.1: (a) SNWTT structure with 9nm radius, (b) SNWTT structure with
11nm radius
According to I-V curve in Figure 4.4.2, the positive impact of decrement
of radius of channel can be notified when on state current of devices almost remain
constant, but the desire outcome with lower leakage current can be achieved that
trade off with small declination of carrier mobility. The width of channel is defined
as two times of radius. As the radius scale down, the height of channel also
decreased and makes the gate control over the channel become more dominant by
lowering their off state current(Ru Huang et al,2011 ).Volume inversion could be
the best explanation regarding the relationship between leakage current and radius
effect. A larger radius induced a larger volume inversion. However, as the radius
increased, the gate control over the channel also affected and indicated by
increment of leakage current. Channel with larger radius make the position of
volume inversion is far away from the gate and located at the middle of the
channel. But, the case is different for the channel with smaller radius where the
location of volume inversion is nearer to top gate surface. As the volume inversion
is located nearer to the top gate, a leakage current could be improved better by
having a smaller of radius of channel. A small leakage current is much preferred to
make the device applicable as low power devices since less power loss during
switching period.
53
Figure 4.4.2: I-V curve for SNWTT with various channel radiuses
The threshold voltage is decreasing as radius of channel increase as shown in
Figure 4.4.3. The reason threshold decrease can be understood as a consequence of
charge neutrality: the Yau charge-sharing model. The combined charge in
the depletion region, device and in the channel are balanced by three electrode
charges: the gate, the source and the drain. As drain voltage is increased,
the depletion region of the p-n junction between the drain and body increases in
size and extends under the gate, so the drain assumes a greater portion of the
burden of balancing depletion region charge, leaving a smaller burden for the gate.
As a result, the charge present on the gate retains charge balance by attracting
more carriers into the channel, an effect equivalent to lowering the threshold
voltage of the device.
54
Radius of channel,R (nm)
Th
resh
old
vo
lta
ge
,Vth
(V)
141312111098765 10 15
0.65
0.7
0.75
0.8LG=26nm
tox=1.5nm
Figure 4.4.3 Graph of threshold voltage, Vth against radius of channel of
SNWTT
According to Figure 4.4.4 it shows that drain induced barrier lowering (DIBL);
a short-channel effect or referred as reduction in threshold voltage of
the transistor at high drain voltages against radius of channel. It can be deduced
that DIBL is directly proportional to radius of channel because the source and
drain form p-n junctions with the body, and so have associated built-in depletion
layers associated with them that become significant partners in charge balance at
short channel lengths, even with no reverse bias applied to increase depletion
widths. Besides, long channel is electrostatically shielded from the drain by the
combination of the substrate and gate. While for short-channel devices the drain
is close enough to gate the channel, and so a high drain voltage and turn on the
transistor prematurely.
.
55
Radius of channel, R (nm)
DIB
L (
V/V
)
1413121198765 10 150.4
0.5
0.6
LG=26nm
tox=1.5nm
Figure 4.4.4 DIBL against radius of channel of SNWTT
4.4.4 Temperature effect on SNWTT performance
0 0.2 0.4 0.6 0.8 110
-6
10-4
10-2
T=500K
T=400K
T=350K
T=300K
LG=65nm Nd= 1x1017
cm-3
tox=3nm
Dra
in C
urre
nt, I
D (A
/um
)
Gate Voltage, VG (V)
Figure 4.5: I-V curve incorporating with SNWTTs for different temperature.
56
Figure 4.5 presents the sensitivity of temperature effect on device
performance. Initially, when the temperature increased to 400K, the on-state
current and off state current is not much affected. However, degradation on state
current was notable when the temperature increased to 500K. Decrement of on-
state current is believed associated with the dependent of mobility of electrons on
the heat at the channel with higher temperature. As the temperature increased over
400K, energy posses by the sea of electrons started to reduced with temperature
due to mobility limited by phonon emission. This emission make the electron
scattered and reduced their mobility (F. Wessely, et al, 2012). On state current is
contributed by the carrier concentration at the conduction band, where the energy
dependent on mobility of electrons. Mobility decrement make the behavior of
doped channel become less extrinsic and caused the percentage amount of carrier
concentration moving to the conduction band decreased and affected the on-current
performance (D. A.Neamen,2003).
Nevertheless, this trend still can be accepted as robustness device since
their off-state current remain same and on-state current slightly shifted downward.
These criteria also imply that the lifetime of devices could be keep further.
Furthermore, normally the device will expose to high temperature when they are
combined into more than one device to work as electronic system.
4.4.5 Doping concentration effects
An analysis of different uniform body doping: 1011
cm-3
, 1015
cm-3
and
1018
cm-3
of 22 nm channel length for SNWTT structure with high-k (HfO2)
insulator has been done successfully. The SNWTT structure has suppressed short
channel effect without the need to reduce the junction depth. A reduction of
leakage current was obtained without altering the drive current.
57
Besides, the threshold voltage is increase accordingly with increasing
body doping. Thus, the incorporation of SNWTT structure will enhance the
electrical performance and give a good control of the SCE for scaling the
MOSFET in nanometer regime for future development of nanoelectronics devices.
Figure 4.6: I-V curve for doped high-k metal (HfO2) with different
doping concentration, Na
Figure 4.6 shows the current-voltage (IDS – VGS) characteristics and
subthreshold curves for MOSFET device of channel length Lg = 22 nm with
uniform boron doping of 1011
cm-3
, 1015
cm-3
and 1018
cm-3
taken at VDS = 0.1 V.
In the off-state operation mode the transistor showed a drain leakage current IOFF
which is independent of the gate voltage, but increases with decreasing body
doping concentration as depicted in Figure 4.6. With low body doping, the carrier
mobility can be increased [45] meanwhile higher substrate doping density reduces
the mobility and the extension of the source and drain depletion layers into the
channel [9]. Low body doping concentration was used instead of high body
concentration because the carrier mobility can be increased and in the same time
the extension of depletion layers can be reduced. In addition, it is obvious that the
off-state leakage current reduced to 2 x 10-8
A/µm, 4 x 10-8
A/µm and 12 x 10-9
58
A/µm for body doping of 1011
cm-3
, 1015
cm-3
and 1018
cm-3
. A slight different on
drive current, ION is obtained for all body doping concentration.
4.5 Summary
In this chapter, SNWTT structure analysis and comparison to reference model
structure, some manipulation parameter such variation of doping level , variation of
channel radius , variation of temperature and variation of asymmetry mobility was
presented by numerical simulation. The analysis includes the IDS versus VGS
curves, transfer and output characteristics, threshold voltage roll-off, and off-state
leakage current and DIBL Key results are: (i) to optimize the fabrication process
using process simulation, 3D Sentaurus TCAD tool allow better IDS versus VGS
performance.
CHAPTER 5
CONCLUSION AND RECOMMENDATIONS
5.1 Conclusion
Silicon nanowire tri-gate transistor with high-k (HfO2) insulator device
has been designed, fabricated and investigated the characterization with
comparison with standard tri-gate structure. It has shows the advantages especially
to suppress corner effect, short channel effect such as allowing better VT control
depends on reduction of VT roll-off, reduction of IOFF and improve ION/IOFF ratio
Current-voltage characteristics for both IDS - VGS and IDS - VDS curve illustrated the
electrical behavior of designed silicon nanowire tri-gate structure. It was also
found that the proposed structure plays a role in determining the effective threshold
voltage, subthreshold swing, on and off current and drain induced barrier lowering.
As channel shaped of SNWTT is semi-cylindrical, it reduced corner effect that are
caused by accumulated electron at the corner of standard tri-gate structure (square
in shape) besides reducing the current leakage.
60
In order to optimize the performance of silicon nanowire tri-gate
transistor with high-k (HfO2) insulator, a few different approaches have been
investigated which were scaling of dielectric (applied HfO2 as dielectric instead of
SiO2), body doping concentration, different channel radius, and temperature effect
on performance. In the beginning, two different structure of transistor: tri-gate
structure and silicon nanowire tri-gate were constructed to shows proposed modal
has better performance. Then, silicon nanowire structure with two different
dielectric layers: oxide and high-k were modeled. Silicon nanowire tri-gate
transistor with high-k insulator has better performance especially in reduction of
IOFF and increased the ION/IOFF ratio. An analysis of three different uniform body
doping concentration: 1011
cm-3
,1015
cm-3
, 1018
cm-3
of SNWTT was shown the
increasing in magnitude of VT with increasing the body doping concentration. An
optimum body doping concentration of 1 x 1018
cm-3
was selected due to the
capability to improve the VT roll-off and reduce the DIBL effect. Lower value of
VT was obtained due to lower body or channel doping of 1018
cm-3
and high S/D
doping of 1020
cm-3
. Thus, the channel was created with the small value of VGS.
IOFF was decreased with an increasing body doping concentration meanwhile drain
current was increased with decreasing body doping concentration. While, analyze
of thermal effect on devices performance shows that when temperature is raised
above 400K, the device performance is reduced: increased in leakage current.
Therefore, the suitable temperature for the device to function optimally is at 300K
or below 400K.
A simulation study of Silicon Nanowire Tri-gate Transistor is presented
in this dissertation. This type of device has advantages Tri-gate transistor such as
less corner effect, reduction in leakage current through channel, and high drive
current. The current-voltage characteristics showed that for wider pillars the
threshold voltage, IOFF With the results obtained in simulating the transistor, DP-
MOSFET device showed a possibility to give a very good control of the SCE for
scaling the MOSFET in nanometer regime for future development of
nanoelectronics device.
61
Compare to other researchers, our contribution to do this research were:
(i) Using latest TCAD tool, Sentaurus to model silicon nanowire tri-gate
transistor in three-dimensional (3D)
(ii) The structure was develop based on ideal structure of silicon nanowire,
Gate-All-Around (GAA)
(iii) Introducing high-k (HfO2) as nanowire insulator
(iv) Optimization of silicon nanowire tri-gate structure; channel length =
22nm, doping concentration, radius of channel, and temperature
(v) Analysis on device performance based on parameter variation such
doping concentration, threshold voltage, on and off current, threshold
voltage roll-off, drain induced barrier lowering and ION/IOFF ratio.
For information, this research has been carried out on a simulation basis.
Technology computer-aided design (TCAD) is an important tool to simulate the
actual wafer fabrication process and device characterization. However, it is better
if there is facility to carry out the real fabrication process for better comparison
with the simulated results.
5.2 Suggestions for Future Work
In this dissertation, the feasibility of a silicon nanowire tri-gate transistor
with high-k insulator is demonstrated. Since the proposed device has a lot of
advantages, further utilize of the devices should be carried on.
62
Suggestions for future studies are as follows:
• The modeling data can be compared to either real fabricated structured or
simulation data. The parameters from this modeling can be used to
analyst in circuit performance. Thus, SNWTT structure can be used at
circuit level modeling.
• SNWTT fabrication process: Real fabrication MOSFET is an actual
structure to be investigated. However, it needs a facility such as clean
room lab which is expensive. The results from fabrication can be
compared with simulation. The simulation for SNWTT is almost done
and the process and device simulation data can be use to fabricate it.
• Novel device structures: It is important to continue to study the effects of
scaling down the channel length on the characteristics of the device in
order to optimize their performance. Therefore, many theoretical devices
structures and the use of new materials are proposed to extend future
scaling of MOSFET in future. Recently, vertical MOSFET become more
popular topic to be investigated. This is because of its performance and
many advantages over the conventional planar MOSFET. The channel
length can be reduced more easily using this structure. There are silicon-
based vertical MOSFETs and other alternative structure or using new
materials. Other new structures are nano-scroll, nano-ribbon and other
new materials such as grapheme.
63
REFERENCES
1. A.Neamen, D. (2003). Semiconductor Physics and Devices(Mc Graw
Hill,Singapore). p94
2. Agrawal, B., De, V., Pimbley, J., & Meindl, J. (1994). Short channel models and
scaling limits of SOI and bulk MOSFETs. Solid-State Circuits, IEEE Journal of,
29(2), 122-125.
3. Ahmadi, M. T., Johari, Z., Amin, N. A., Fallahpour, A. H., & Ismail, R. (2010).
Graphene nanoribbon conductance model in parabolic band structure. Journal of
Nanomaterials, 2010, 12.
4. Ahmadi, M. T., Ta, M. L. P., Ismail, R., & Arora, V. K. (2009). The high-field
drift velocity in degenerately-doped silicon nanowires. International Journal of
Nanotechnology 6, 7-8.
5. Arns, R. G. (1998). The other transistor: early history of the metal-oxide
semiconductor field-effect transistor. Engineering Science and Education
Journal, 7(5), 233-240.
6. Arora, V. K. (1985a). High-field distribution and mobility in semiconductors.
JAP. J. APPL. PHYS., 24(5), 537-545.
7. Arora, V. K. (1985b). Quantum well wires: electrical and optical properties.
Journal of Physics C: Solid State Physics, 18(15), 3011.
8. Arora, V. K. (2008). Ballistic quantum transport in nano devices and circuits.
Paper presented at the Nanoelectronics Conference, 2008. INEC 2008. 2nd IEEE
International.
9. Bai, P., Auth, C., Balakrishnan, S., Bost, M., Brain, R., Chikarmane, V., et al.
(2004, 13-15 Dec. 2004). A 65nm logic technology featuring 35nm gate lengths,
enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57
μm<sup>2</sup> SRAM cell. Paper presented at the Electron Devices
Meeting, 2004. IEDM Technical Digest. IEEE International.
10. Baie, X., Colinge, J., Bayot, V., & Grivei, E. (1995). Quantum-wire effects in
thin and narrow SOI MOSFETs. Paper presented at the SOI Conference, 1995.
Proceedings., 1995 IEEE International.
11. Balestra, F., Cristoloveanu, S., Benachir, M., Brini, J., & Elewa, T. (1987).
Double-gate silicon-on-insulator transistor with volume inversion: A new device
64
with greatly enhanced performance. Electron Device Letters, IEEE, 8(9), 410-
412.
12. Bernstein, K., Frank, D., Gattiker, A., Haensch, W., Ji, B., Nassif, S., et al.
(2006). High-performance CMOS variability in the 65-nm regime and beyond.
IBM Journal of Research and Development, 50(4.5), 433-449.
13. Bondyopadhyay, P. K. (1998). Moore's law governs the silicon revolution.
Proceedings of the IEEE, 86(1), 78-81.
14. Breed, A., & Roenker, K. (2003). Dual-gate (FinFET) and tri-gate MOSFETs:
simulation and design. Paper presented at the Semiconductor Device Research
Symposium, 2003 International.
15. Buddharaju, K., Singh, N., Rustagi, S., Teo, S. H., Wong, L., Tang, L., et al.
(2007). Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-
down approach. Paper presented at the Solid State Device Research Conference,
2007. ESSDERC 2007. 37th European.
16. Buddharaju, K. D., Singh, N., Rustagi, S. C., Teo, S. H. G., Wong, L. Y., Tang,
L. J., et al. (2007, 11-13 Sept. 2007). Gate-all-around Si-nanowire CMOS
inverter logic fabricated using top-down approach. Paper presented at the Solid
State Device Research Conference, 2007. ESSDERC 2007. 37th European.
17. Chau, R., Datta, S., Doczy, M., Doyle, B., Jin, B., Kavalieros, J., et al. (2005).
Benchmarking nanotechnology for high-performance and low-power logic
transistor applications. Nanotechnology, IEEE Transactions on, 4(2), 153-158.
18. Chau, R., Doyle, B., Kavalieros, J., Barlage, D., Murthy, A., Doczy, M., et al.
(2002). Advanced depleted-substrate transistors: single-gate, double-gate and tri-
gate. SOLID STATE DEVICES AND MATERIALS, 68-69.
19. Chau, R. S., Doyle, B. S., Kavalieros, J., Barlage, D., & Datta, S. (2009). Tri-
gate devices and methods of fabrication: Google Patents.
20. Chen, C.-Y., Liao, Y.-B., & Chiang, M.-H. (2008). Scaling study of nanowire
and multi-gate MOSFETs. Paper presented at the Solid-State and Integrated-
Circuit Technology, 2008. ICSICT 2008. 9th International Conference on.
21. Chung , S. H., Carns , T., Lee.S, K., DeBruler , L., & Berg , J. E. (1999).
Measuring the effective channel length of the deep submicron MOSFET and
channel broadening effect. Paper presented at the
University/Government/Industry Microelectronics Symposium, 1999.
Proceedings of the Thirteenth Biennial.
22. Colinge, J.-P. (2008). The SOI MOSFET: from Single Gate to Multigate
23. FinFETs and Other Multi-Gate Transistors. In J.-P. Colinge (Ed.), (pp. 1-48):
Springer US.
24. Colinge, J.-P., Quinn, A. J., Floyd, L., Redmond, G., Alderman, J. C., Xiong, W.,
et al. (2006). Low-temperature electron mobility in trigate SOI MOSFETs.
Electron Device Letters, IEEE, 27(2), 120-122.
65
25. Cui, Y., & Lieber, C. M. (2001). Functional nanoscale electronic devices
assembled using silicon nanowire building blocks. Science, 291(5505), 851-853.
26. Cui, Y., Zhong, Z., Wang, D., Wang, W. U., & Lieber, C. M. (2003). High
performance silicon nanowire field effect transistors. Nano Letters, 3(2), 149-
152.
27. Dennard, R. H. (1997). Scaling Challenges for DRAM and Microprocessors in
the 21st Century. . ULSI Science and Technology, 97(3), 519-532
28. Deshpande, N. P. (2008). Electron Device and Circuits: Principles and
Applications: McGraw-Hill Education (India) Pvt Limited.
29. Dollfus, P., Bournel, A., Galdin, S., Barraud, S., & Hesto, P. (2004). Effect of
discrete impurities on electron transport in ultrashort MOSFET using 3D MC
simulation. Electron Devices, IEEE Transactions on, 51(5), 749-756.
30. Doyle, B., Boyanov, B., Datta, S., Doczy, M., Hareland, S., Jin, B., et al. (2003).
Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout. Paper
presented at the VLSI Technology, 2003. Digest of Technical Papers. 2003
Symposium on.
31. Doyle, B. S., Datta, S., Doczy, M., Hareland, S., Jin, B., Kavalieros, J., et al.
(2003). High performance fully-depleted tri-gate CMOS transistors. Electron
Device Letters, IEEE, 24(4), 263-265.
32. Duane, M. (2002). The role of TCAD in compact modeling. Worksнop on
Compact Modeling, 5, 22-25.
33. Ernst, T., Ritzenthaler, R., Faynot, O., & Cristoloveanu, S. (2007). A model of
fringing fields in short-channel planar and triple-gate SOI MOSFETs. Electron
Devices, IEEE Transactions on, 54(6), 1366-1375.
34. Fernández-Serra, M.-V., Adessi, C., & Blase, X. (2006). Conductance, surface
traps, and passivation in doped silicon nanowires. Nano Letters, 6(12), 2674-
2678.
35. Fossum, J. G., Yang, J. W., & Trivedi, V. P. (2003). Suppression of corner
effects in triple-gate MOSFETs. Electron Device Letters, IEEE, 24(12), 745-747.
36. Garcia Ruiz, F. J., Godoy, A., Gamiz, F., Sampedro, C., & Donetti, L. (2007). A
Comprehensive Study of the Corner Effects in Pi-Gate MOSFETs Including
Quantum Effects. Electron Devices, IEEE Transactions on, 54(12), 3369-3377.
37. Ghani, T., Armstrong, M., Auth, C., Bost, M., Charvat, P., Glass, G., et al. (2003,
8-10 Dec. 2003). A 90nm high volume manufacturing logic technology featuring
novel 45nm gate length strained silicon CMOS transistors. Paper presented at the
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE
International.
38. Goetzbergera, A., Klausmanna, E., & Schulza, M. J. (1976). Interface states on
semiconductor/insulator surfaces. Interface states on semiconductor/insulator
surfaces, 6(1), 1-43.
66
39. Greene, B., Liang, Q., Amarnath, K., Wang, Y., Schaeffer, J., Cai, M., et al.
(2009, 16-18 June 2009). High performance 32nm SOI CMOS with high-k/metal
gate and 0.149µm<sup>2</sup> SRAM and ultra low-k back end with
eleven levels of copper. Paper presented at the VLSI Technology, 2009
Symposium on.
40. Haensch, W., Nowak, E., Dennard, R., Solomon, P., Bryant, A., Dokumaci, O.,
et al. (2006). Silicon CMOS devices beyond scaling. IBM Journal of Research
and Development, 50(4.5), 339-361.
41. Hamid, F. K. A., Anwar, S., Amin, N. A., Johari, Z., Sadeghi, H., Nurudin, M.
A., et al. (2013). The Effect of Effective Channel Length on a Silicon Nanowire
Fin Field Effect Transistor. American Scientific Publishers, Vol. 10(1-4)
42. Jan, C. H., Agostinelli, M., Buehler, M., Chen, Z. P., Choi, S. J., Curello, G., et
al. (2009, 7-9 Dec. 2009). A 32nm SoC platform technology with
2<sup>nd</sup> generation high-k/metal gate transistors optimized for ultra
low power, high performance, and high density product applications. Paper
presented at the Electron Devices Meeting (IEDM), 2009 IEEE International.
43. Jin, Y. W., Zeng, C., Ma, L., & Barlage, D. (2007). Analytical threshold voltage
model with TCAD simulation verification for design and evaluation of tri-gate
MOSFETs. Solid-State Electronics, 51(3), 347-353.
44. Kavalieros, J., Doyle, B., Datta, S., Dewey, G., Doczy, M., Jin, B., et al. (2006).
Tri-gate transistor architecture with high-k gate dielectrics, metal gates and
strain engineering. Paper presented at the VLSI Technology, 2006. Digest of
Technical Papers. 2006 Symposium on.
45. Kodambaka, S., Tersoff, J., Reuter, M., & Ross, F. (2006). Diameter-
independent kinetics in the vapor-liquid-solid growth of Si nanowires. Physical
review letters, 96(9), 096105.
46. Kretz, J., Dreeskornfeld, L., Hartwich, J., & Rosner, W. (2003). 20 nm electron
beam lithography and reactive ion etching for the fabrication of double gate
FinFET devices. Microelectronic Engineering, 67-8, 763-768.
47. Landgraf, E., Rösner, W., Städele, M., Dreeskornfeld, L., Hartwich, J., Hofmann,
F., et al. (2006). Influence of crystal orientation and body doping on trigate
transistor performance. Solid-State Electronics, 50(1), 38-43.
48. Lau, H. H., Hii, H., Lee, A., Ahmadi, M. T., Ismail, R., & Arora, V. K. (2008).
The high-field drift velocity in degenerately-doped silicon nanowires. Paper
presented at the Nanoelectronics Conference, 2008. INEC 2008. 2nd IEEE
International.
49. Lauhon, L. J., Gudiksen, M. S., Wang, D., & Lieber, C. M. (2002). Epitaxial
core–shell and core–multishell nanowire heterostructures. Nature, 420(6911),
57-61.
67
50. Lee, C.-W., Yun, S.-R.-N., Yu, C.-G., Park, J.-T., & Colinge, J.-P. (2007).
Device design guidelines for nano-scale MuGFETs. [doi:
10.1016/j.sse.2006.11.013]. Solid-State Electronics, 51(3), 505-510.
51. Li, Y. M., Chou, H. M., & Lee, J. W. (2005). Investigation of electrical
characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs.
Ieee Transactions on Nanotechnology, 4(5), 510-516.
52. Lo, S. H., Buchanan, D. A., Taur, Y., & Wang, W. (1997). Quantum-mechanical
modeling of electron tunneling current from the inversion layer of ultra-thin-
oxide nMOSFET's. Electron Device Letters, IEEE, 18(5), 209-211.
53. Lundstrom, M., & Guo, J. (2006). Nanoscale transistors: Device physics,
modeling and simulation (Vol. 233): Springer New York.
54. Mack, C. A. (2011). Fifty Years of Moore's Law. Semiconductor Manufacturing,
IEEE Transactions on, 24(2), 202-207.
55. Majkusiak, B., Janik, T., & Walczak, J. (1998). Semiconductor thickness effects
in the double-gate SOI MOSFET. Electron Devices, IEEE Transactions on,
45(5), 1127-1134.
56. Mistry, K., Allen, C., Auth, C., Beattie, B., Bergstrom, D., Bost, M., et al. (2007,
10-12 Dec. 2007). A 45nm Logic Technology with High-k+Metal Gate
Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning,
and 100% Pb-free Packaging. Paper presented at the Electron Devices Meeting,
2007. IEDM 2007. IEEE International.
57. Modules of Sentaurus TCAD Industry-Standard Process and Device Simulators
at (2012 ). Synopsys at
http://www.synopsys.com/Tools/TCAD/CapsuleModule/sentaurus_ds.pdf.
58. Moore's Law, Made Real by Intel Innovations", Intel, (2010, September, 23)
http://www.intel.com/technology/mooreslaw/.
59. Moselund, K. E., Bouvet, D., Tschuor, L., Pott, V., Dainesi, P., & Ionescu, A. M.
(2006). Local volume inversion and corner effects in triangular gate-all-around
MOSFETs. Paper presented at the Solid-State Device Research Conference,
2006. ESSDERC 2006. Proceeding of the 36th European.
60. Muller, R. S., & Kamins, T. I. (1986). Device Electronics for Integrated Circuits.
Wiley,Hoboken, NJ.
61. Ng, M.-F., Shen, L., Zhou, L., Yang, S.-W., & Tan, V. B. (2008). Geometry
Dependent I− V Characteristics of Silicon Nanowires. Nano Letters, 8(11), 3662-
3667.
62. Niquet, Y., Lherbier, A., Quang, N., Fernández-Serra, M., Blase, X., & Delerue,
C. (2006). Electronic structure of semiconductor nanowires. Physical Review B,
73(16), 165319.
63. Nitayama, A., Takato, H., Okabe, N., Sunouchi, K., Hieda, K., Horiguchi, F., et
al. (1991). Multi-pillar surrounding gate transistor (M-SGT) for compact and
high-speed circuits. Electron Devices, IEEE Transactions on, 38(3), 579-583.
68
64. Packan, P., Akbar, S., Armstrong, M., Bergstrom, D., Brazier, M., Deshpande,
H., et al. (2009, 7-9 Dec. 2009). High performance 32nm logic technology
featuring 2<sup>nd</sup> generation high-k + metal gate transistors. Paper
presented at the Electron Devices Meeting (IEDM), 2009 IEEE International.
65. Pennington, G., & Goldsman, N. (2005). Low-field semiclassical carrier
transport in semiconducting carbon nanotubes. Physical Review B, 71(20),
205318.
66. Poiroux, T., Vinet, M., Faynot, O., Widiez, J., Lolivier, J., Ernst, T., et al. (2005).
Multiple gate devices: advantages and challenges. Microelectronic Engineering,
80, 378-385.
67. Poljak, M., Jovanović, V., & Suligoj, T. (2010). Suppression of corner effects in
wide-channel triple-gate bulk FinFETs. [doi: 10.1016/j.mee.2009.07.013].
Microelectronic Engineering, 87(2), 192-199.
68. Pott, V., Moselund, K. E., Bouvet, D., De Michielis, L., & Ionescu, A. M.
(2008). Fabrication and characterization of gate-all-around silicon nanowires on
bulk silicon. Nanotechnology, IEEE Transactions on, 7(6), 733-744.
69. Ritzenthaler, R., Faynot, Jahan, C., Kuriyama, A., and, S. D., & S.Cristoloveanu,
S. (2006
70. ). Coupling effects in FinFETs and Triple-gate FETs. 7th European Workshop on
Ultimate Integration of Silicon, ULIS, pp. 25-28.
71. Rurali, R. (2010). Colloquium: Structural, electronic, and transport properties of
silicon nanowires. Reviews of Modern Physics, 82(1), 427.
72. Sato, S., Kakushima, K., Ahmet, P., Ohmori, K., Natori, K., Yamada, K., et al.
(2011). Effects of corner angle of trapezoidal and triangular channel cross-
sections on electrical performance of silicon nanowire field-effect transistors
with semi gate-around structure. Solid-State Electronics, 65–66(0), 2-8.
73. Sato, S., Yeonghun, L., Kakushima, K., Ahmet, P., Ohmori, K., Natori, K., et al.
(2010, 14-16 Sept. 2010). Gate semi-around Si nanowire FET fabricated by
conventional CMOS process with very high drivability. Paper presented at the
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the
European.
74. Schmidt, V., Wittemann, J. V., Senz, S., & Gösele, U. (2009). Silicon nanowires:
a review on aspects of their growth and their electrical properties. Advanced
Materials, 21(25‐26), 2681-2702.
75. Sekigawa, T. (1984). Calculated threshold-voltage characteristics of an XMOS
transistor having an additional bottom gate. Solid-State Electron, 27, 827.
76. Seoane, N., Martinez, A., Brown, A. R., Barker, J. R., & Asenov, A. (2009).
Current variability in Si nanowire MOSFETs due to random dopants in the
source/drain regions: A fully 3-D NEGF simulation study. Electron Devices,
IEEE Transactions on, 56(7), 1388-1395.
69
77. Simon, M. S., & Kwok, K. N. (2007). Physics of Semiconductor Devices.
78. Singh, A. K., Kumar, V., Note, R., & Kawazoe, Y. (2006). Effects of
morphology and doping on the electronic and structural properties of
hydrogenated silicon nanowires. Nano Letters, 6(5), 920-925.
79. Singh, N., Agarwal, A., Bera, L. K., Liow, T. Y., Yang, R., Rustagi, S. C., et al.
(2006). High-performance fully depleted silicon nanowire (diameter ≤ 5 nm)
gate-all-around CMOS devices. Electron Device Letters, IEEE, 27(5), 383-386.
80. Stadele, M., Luyken, R., Roosz, M., Specht, M., Rosner, W., Dreeskornfeld, L.,
et al. (2004). A comprehensive study of corner effects in tri-gate transistors.
Paper presented at the Solid-State Device Research conference, 2004. ESSDERC
2004. Proceeding of the 34th European.
81. Sun, X., Lu, Q., Moroz, V., Takeuchi, H., Gebara, G., Wetzel, J., et al. (2008).
Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap.
Electron Device Letters, IEEE, 29(5), 491-493.
82. Sze, S. M. (1981). Physics of Semiconductor Devices.2nd.New York:Wiley.
83. Taghi Ahmadi, M., Houg Lau, H., Ismail, R., & Arora, V. K. (2009). Current–
voltage characteristics of a silicon nanowire transistor. [doi:
10.1016/j.mejo.2008.06.060]. Microelectronics Journal, 40(3), 547-549.
84. Thean, A., Shi, Z., Mathew, L., Stephens, T., Desjardin, H., Parker, C., et al.
(2006). Performance and variability comparisons between multi-gate FETs and
planar SOI transistors. Paper presented at the Electron Devices Meeting, 2006.
IEDM'06. International.
85. Thompson, S., Alavi, M., Arghavani, R., Brand, A., Bigwood, R., Brandenburg,
J., et al. (2001, 2001). An enhanced 130 nm generation logic technology
featuring 60 nm transistors optimized for high performance and low power at 0.7
- 1.4 V. Paper presented at the Electron Devices Meeting, 2001. IEDM '01.
Technical Digest. International.
86. Thompson, S. E., Armstrong, M., Auth, C., Alavi, M., Buehler, M., Chau, R., et
al. (2004). A 90-nm logic technology featuring strained-silicon. Electron
Devices, IEEE Transactions on, 51(11), 1790-1797.
87. Vo, T., Williamson, A., & Galli, G. (2006). First principles simulations of the
structural and electronic properties of silicon nanowires. Physical Review B,
74(4), 045116.
88. Wagner, R., & Ellis, W. (1964). Vapor‐liquid‐solid mechanism of single crystal
growth. Applied Physics Letters, 4(5), 89-90.
89. Wang, J., Polizzi, E., & Lundstrom, M. (2003). A computational study of ballistic
silicon nanowire transistors. Paper presented at the Electron Devices Meeting,
2003. IEDM'03 Technical Digest. IEEE International.
90. Wang, J., Rahman, A., Ghosh, A., Klimeck, G., & Lundstrom, M. (2005). On the
validity of the parabolic effective-mass approximation for the IV calculation of
70
silicon nanowire transistors. Electron Devices, IEEE Transactions on, 52(7),
1589-1595.
91. Wong, H.-S., Chan, K. K., & Taur, Y. (1997). Self-aligned (top and bottom)
double-gate MOSFET with a 25 nm thick silicon channel. Paper presented at the
Electron Devices Meeting, 1997. IEDM'97. Technical Digest., International.
92. Wu, Y.-S., & Su, P. (2008). Sensitivity of gate-all-around nanowire MOSFETs
to process variations—A comparison with multigate MOSFETs. Electron
Devices, IEEE Transactions on, 55(11), 3042-3047.
93. Xia, Y., Yang, P., Sun, Y., Wu, Y., Mayers, B., Gates, B., et al. (2003).
One‐dimensional nanostructures: synthesis, characterization, and applications.
Advanced Materials, 15(5), 353-389.
94. Xiao, D., Wang, X., Yu, Y., Chen, J., Zhang, M., Xue, Z., et al. (2009). TCAD
study on gate-all-around cylindrical (GAAC) transistor for CMOS scaling to the
end of the roadmap. Microelectronics Journal, 40(12), 1766-1771.
95. Xiong, W., Park, J., & Colinge, J. (2003). Corner effect in multiple-gate SOI
MOSFETs. Paper presented at the SOI Conference, 2003. IEEE International.
96. Yan, R.-H., Ourmazd, A., & Lee, K. F. (1992). Scaling the Si MOSFET: From
bulk to SOI to bulk. Electron Devices, IEEE Transactions on, 39(7), 1704-1710.