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HP Advanced Design SystemRelease 1.0

What is HP Advanced

Design System?

HP Advanced Design System is anew electronic-design-automation(EDA) software system that helpsspeed communications productsto market. It provides the indus-try’s first integrated, end-to-endsignal path design solution todevelopers of products such ascellular and portable phones,pagers, wireless networks, andradar and satellite communica-tions systems. With this system, HP now provides a full range of communication system designcapabilities — from circuit andelectromagnetic simulation to digital signal processing (DSP)synthesis and physical design —seamlessly integrated in a singleenvironment.

Table of Contents HP Communication Systems Designer. . . . . . . . . . . . . 3

HP DSP Designer . . . . . . . . . . . . . 4

HP DSP Synthesis. . . . . . . . . . . . . 5

HP RFIC Designer . . . . . . . . . . . . . 6

HP Microwave Circuit Designer . . . . . . . . . . . . . . 7

HP RF Board Designer . . . . . . . . . 8

Design Environment . . . . . . . . . . . 9

Simulators . . . . . . . . . . . . . . . . . . 13

DSP Synthesis Products . . . . . . 25

Model Sets and Vendor Component Libraries . . . . . . . . . 31

Physical Design Products . . . . . 37

Framework Links. . . . . . . . . . . . . 41

Support, Training and Services . . . . . . . . . . . . . . . . 46

Index . . . . . . . . . . . . . . . . . . . . . . 47

Documentation and System Requirements . . . . . . . . 48

Features & Benefits• Allows simulation and

verification of DSP, RFIC, RF board, microwave, andelectromagnetic designs priorto costly prototyping.

• Permits co-simulation of RF and DSP solutions to improvedesign performance and speed product development time.

• Eases creation of optimal RTL for any DSP flow diagram.

• Provides faster new harmonicbalance, with reduced memoryneeds.

• Offers expanded links to HP measurement instrumentation.

• Includes libraries of over90,000 parts and links to third-party software.

Solutions from HP EEsof

The First Integrated Solution for Communication Signal Path Design

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HP Advanced Design System

The Time-to-Market

Challenge

The primary challenge facingtoday’s communication productdesigners is how to reduce the time it takes to get new productsinto the hands of consumers.Competition is intense. A fewmonths’ delay in bringing a newproduct to market can result in failure of the product offering.

HP Advanced Design System was developed to help bring yourcommunication designs to marketin the most expedient and cost-effective manner possible. Thisnew system is the culmination ofHP EEsof’s years of expertise indeveloping RF, microwave, and system design automation solutions.

Complete, Integrated

Solutions for End-to-

End Communication

Signal Path Design

HP Advanced Design System is a family of EDA modules thatoffers designers of communica-tions products a complete signalpath solution.

The family is composed of EDAmodules including circuit and system simulators, translators, layout solutions, models, libraries,etc. The modules have been selec-tively bundled into design suitesthat provide solutions to specificproblems.

HP Advanced Design

System Suites

HP offers a variety of suites, bundled to provide solutions tocommunications system, DSP,RFIC, microwave, RF board, layout, and related design prob-lems. The following suites areexplained in this document:

• HP Communication Systems Designer

• HP DSP Designer

• HP DSP Synthesis

• HP RFIC Designer

• HP Microwave CircuitDesigner

• HP RF Board Designer

This document defines the design suites, their components,their features and benefits, andtheir applications. The individualmodules that comprise the suitesare also described.

HP also offers specialized solu-tions for high-frequency structuresimulation and statistical modelingof ICs and nonlinear devices (see page 46).


SYSTEM ARCHITECTURE

CO-SIMULATION

INPUT REQUIREMENTS

AlgorithmSelection

Floating Point Design

Fixed PointDesign

SubsystemDesign

CircuitSimulation

CircuitOptimization

YieldOptimizationSynthesis

IC or ASIC/FPGAImplementation

IntegrateDSP & RF

Test

Manufacturing

Mentor/Cadence

DSP ANALOG/RF

HP EEsoforCadence/Mentor(for IC and PCB)

PhysicalDesign


Overview

Developed for communication system architects and subsystemdesigners, this suite lets youmodel, compare, and trade offarchitectures, standards, systempartitions, specifications, andother factors that affect a system’sperformance. The suite simplifiesthe generation of system-level andsubsystem-level specificationsthat are not over- or under-speci-fied. This can translate into signif-icant savings of component development time. A typical radiolink, for example, has at least anencoder, decoder, modulator,demodulator, upconverter, down-converter, power amplifier, low-noise amplifier, and IF section.The minimal benefit from notover-specifying these componentscould exceed one engineeringmonth. Further, the statisticalpackage (included in Premier)offers guidance on how to maxi-mize manufacturing yield andminimize cost. Finally, the abilityto download or upload analog anddigital signals to instrumentationleads to better analysis and under-standing of the hardware duringthe critical integration phase.

Suite Capabilities

There are three versions of this suite:

• HP Communication Systems

Designer is tailored for RF system engineers. It contains an RF simulator that accuratelypredicts performance of com-plete RF systems. It alsoincludes a set of block-level RF models for linear and non-linear parts. Some functionalityis restricted with this version ofthe suite.


Designer Pro offers RF systemmodeling and general signalprocessing, including DSP. Inaddition, it allows co-simulationbetween RF system models andDSP simulations. For example, this package allows you toimplement floating-point DSPalgorithms and, in the samesimulation, predict system per-formance measures like BER.

HP Communication SystemsDesigner

Features and Benefits• Provides accurate RF system models for faster development of system

specifications.• Contains bi-directional instrumentation links that provide a better way to

control the integration of hardware.• Offers propagation and matrix models that allow modeling of complete

wireless systems.• Contains hundreds of DSP and analog models for development of

algorithms to combat analog effects.• Co-simulates with MATLAB to leverage your intellectual property models.

Suite Configurations

HP Communication Systems Designer E8850A*Design EnvironmentData DisplayRF System SimulatorRF System Models

HP Communication Systems Designer Pro E8851A/ANDesign Environment E8900A/ANData Display E8901A/ANRF System Simulator E8853A/ANRF System Models E8854A/ANHP Ptolemy Simulator E8823A/ANStatistical Design E8824A/AN

HP Communication Systems Designer Premier E8852A/ANContains all of HP Communication Systems Designer Pro plus:HP Ptolemy Matrix Models E8826A/ANAntenna and Propagation Models E8856A/AN

* Some functionality is restricted:• File I/O only; instrument I/O not included• Available node-locked for PC platforms only• Not expandable with other modules, exceptwith the purchase of E88581A CommunicationSystems Designer to Unbundled

Note: Throughout this datasheet, all moduleshave a product number with a suffix. Moduleswith an ‘A’ suffix are available node-locked only.Modules with an ‘A/AN’ suffix are available either node-locked or network licensed.

HP Communication Systems Designer


Designer Premier extends thesuite’s simulation capability toinclude radio propagation mod-els for GSM, IS-95 CDMA, and IS-54 TDMA. And, with the addi-tion of the Matrix model set, you can create block processingmodels for data compressionmethods such as JPEG andMPEG. The matrix models alsoallow you to do bi-directional co-simulation with MATLAB.

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characteristics of wireless systems. Finally, this suite canbe combined with analog andRF design solutions for mixed-signal design and simulation.

Overview

Designers need DSP design solutions that speed a completeDSP design process and providethe ability to model analog distor-tions. The physical layer modelingcapability of the DSP Designerfamily enhances your ability toperform these tasks.

The design process starts with theconstruction of a block diagramthat describes the DSP algorithm.This diagram is assembled andwired together in a Windows®-likeenvironment. Each block in thedesign can be selected from thesystem’s extensive model libraryor you can create custom models.The suite also includes a DigitalFilter module (E8825A/AN) toinput filter specifications and gen-erate a schematic design. The HPPtolemy engine supports mixingof numeric signal processing withanalog/RF blocks.

The suite’s simulation solutionscan then be used to refine andoptimize a design. Visual resultssuch as eye diagrams and constel-lations are available. The suitealso includes data display anddata processing capabilities tocreate custom measurements.

Suite Capabilities

HP DSP Designer suite is available in two versions:

• HP DSP Designer providesfloating-point DSP systemdesign and simulation for thePC only. Designs can include amix of DSP and analog behav-ioral models. You can designbaseband processors, mixed-signal carrier recovery loops,AGC control loops, modulators,and other building blocks. Thesuite includes hundreds of DSP behavioral and analog/RFbehavioral models and a modeldevelopment kit. Some func-tionality is restricted with thissuite.

• HP DSP Designer Pro is available for the PC and Unixplatforms. Combining DSPSynthesis with DSP DesignerPro provides a complete flowfrom DSP system-level designthrough RTL output for imple-mentation in silicon. The Prosuite includes fixed-point analy-sis and matrix models (includ-ing bi-directional co-simulationwith MATLAB). You can alsoadd options to facilitate model-ing of channel propagation

HP DSP Designer

Features and Benefits• Provides HP Ptolemy hybrid dataflow and time-domain design and simulation

capability for mixed DSP, analog and RF systems.• Offers ability to co-simulate with analog (High-Frequency SPICE)

and RF (Circuit Envelope) simulators to speed the design process.• Has easy-to-use data export and import capability to measurement

instrumentation.• Works with DSP Synthesis to provide a path from the DSP algorithm

to implementation in silicon.• Comes with MATLAB co-simulation ability for model reuse.

Suite Configurations

HP DSP Designer E8820A*Design EnvironmentData DisplayHP Ptolemy Simulator

HP DSP Designer Pro E8821A/ANDesign Environment E8900A/ANData Display E8901A/ANHP Ptolemy Simulator E8823A/ANHP Ptolemy Fixed Point Analysis E8822A/ANHP Ptolemy Matrix Models E8826A/ANDigital Filter E8825A/AN

*Some functionality is restricted:• File I/O only; instrument I/O not included• Available node-locked for PC platforms only• Not expandable with other modules, exceptwith the purchase of E8837A DSP Designer toUnbundled

Note: Throughout this datasheet, all moduleshave a product number with a suffix. Moduleswith an ‘A’ suffix are available node-locked only.Modules with an ‘A/AN’ suffix are available eithernode-locked or network licensed.

Windows® is a U.S. registered trademark of Microsoft Corp.

HP DSP Designer

Suite ConfigurationsDSP Synthesis PC VHDL E8838A/ANSynthesis Engine E8836A/ANAdaptive Waveform

Comparator E8833A/ANVHDL Models & Code

Generation E8834A/ANVHDL Simulator*

DSP Synthesis PC Verilog E8830A/ANSynthesis Engine E8836A/ANAdaptive Waveform Comparator E8833A/ANVerilog Models & Code

Generation E8835A/ANVerilog Simulator*

DSP Synthesis PC Verilog & VHDL E8839A/ANSynthesis Engine E8836A/ANAdaptive Waveform Comparator E8833A/ANVHDL Models & Code Generation E8834A/ANVerilog Models & Code

Generation E8835A/ANVHDL Simulator*Verilog Simulator*

DSP Synthesis UNIX VHDL E8831A/ANSynthesis Engine E8836A/ANAdaptive Waveform Comparator E8833A/ANVHDL Models & Code Generation E8834A/ANVHDL Simulator*

DSP Synthesis UNIX Verilog E8832A/ANSynthesis Engine E8836A/ANAdaptive Waveform Comparator E8833A/ANVerilog Models & Code

Generation E8835A/ANVerilog Simulator*VHDL Simulator*

DSP Synthesis UNIX Verilog & VHDL E8840A/ANSynthesis Engine E8836A/ANAdaptive Waveform Comparator E8833A/ANVHDL Models & Code Generation E8834A/ANVerilog Models & Code

Generation E8835A/ANVHDL Simulator*Verilog Simulator*

*No part number (not sold separately)

Note: Throughout this datasheet, all modules havea product number with a suffix. Modules with an ‘A’suffix are available node-locked only. Modules withan ‘A/AN’ suffix are available either node-locked ornetwork licensed.

HP DSP Synthesis

Overview

The HP DSP Synthesis suiteallows you to implement high-level DSP designs into ASICs andFPGAs. With this suite you canoptimize designs for the siliconchips of your choice (ASIC orFPGA) and then generate Verilogor VHDL code that can be synthe-sized at the Register TransferLevel.

DSP Synthesis is integrated with DSP Designer, which eliminates hand coding. Thisbehavioral synthesis capability,combined with DSP Designer’ssimulation capabilities, permitsyou to reduce design iterationsand to implement design conceptsonto silicon in an efficient andaccurate manner.

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HP DSP Synthesis

Features and Benefits• Integrates with DSP Designer, which eliminates need to hand-code HDL.• Provides estimation capability to preview possible design choices.• Optimizes according to user-specified constraints to minimize area or

maximize performance.• Uses Adaptive Waveform Comparator to compare test vectors generated

from high-level schematic simulation and RTL HDL simulation.• Incorporates HDL simulator for verification of HDL code.• Provides schematic generation capability for design optimization.

DSP Synthesis takes a schematicdesign from DSP Designer andoptimizes the design for a particu-lar chip, according to your speci-fications. During the optimizationstage, area and performance areconsidered as variables. A newschematic can be generated forthe optimized design and broughtback to DSP Designer for simula-tion and further refinement, or anHDL file can be created and sub-mitted to a logic synthesis solu-tion. The suite also includes anHDL simulator for verification of the resulting HDL code.

Suite Capabilities

This suite is available for the combinations of platforms andHDL languages described under Suite Configurations (at right).

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Overview

Typical RFICs are composed ofdiverse building blocks such aslow-noise amplifiers, mixers,oscillators, phase-locked loops,power amps, and automatic level-control loops. These componentsrequire different simulation tech-nologies to obtain desired designaccuracies within realistic simula-tion times. HP RFIC Designersuites combine high-frequencysimulation and optimization tech-nologies with accurate models,tailored for RFIC designers. Thesuites combine five different sim-ulation technologies operating inthe time, frequency, and hybrid “frequency-time” domains. Theability to simulate and analyze anoverall system of RF and DSP cir-cuits in both the frequency andtime domains, from one schemat-ic, makes these suites invaluabledesign solutions. Solutions link tothird-party EDA solutions andlibraries.

Suite Capabilities

HP RFIC Designer is available intwo versions:

• HP RFIC Designer Pro bringstogether the most often-usedRFIC circuit simulation tech-nologies. With Circuit Envelope,Harmonic Balance, Linear, and the new HP EEsof High-Frequency SPICE simulatorsavailable from a single schemat-ic, you can simulate and opti-mize the performance specifica-tions of RFIC chip sets. In addi-tion, existing designs in netlistsfrom Berkeley SPICE, PSpice,and HSPICE can be broughtinto this suite for simulation.

• HP RFIC Designer Premier

adds user-defined modeling, statistical design, RF systemmodels and convolution simula-tion to the RFIC Designer Pro.An Analog Model DevelopmentKit (E8890A/AN) allows propri-etary foundry models to becompiled and used. MeasuredRFIC package parasitics can beconverted to equivalent low-pass networks using the SPICEmodel generator. The StatisticalDesign module (E8824A/AN)accounts for process variationsand optimizes for yield. The RF

System Models (E8854A/AN)facilitate accurate design partitioning and RF subsystemdesign. The Convolution Sim-ulator (E8885A/AN) extendshigh-frequency simulation toinclude arbitrary frequency-domain data such as S-parame-ters and arbitrary transfer functions.

Features and Benefits• Permits co-simulation of RF and DSP designs, and of combined system-

level behavioral blocks and circuit-level components, to validate overallsignal-path design.

• Provides multiple simulation capability, from one schematic, in frequency,time, and modulation (Circuit Envelope) domains to validate overall designagainst diverse digital wireless standards.

• Contains optimization technologies and statistical design techniques tomaximize design performance and improve yield.

• Provides links to third-party EDA solutions and libraries to ensure efficientdesign flows.

HP RFIC Designer Suite Configurations

HP RFIC Designer Pro E8888A/ANDesign Environment E8900A/ANData Display E8901A/ANLinear Simulator E8881A/ANHarmonic Balance Simulator E8882A/ANCircuit Envelope Simulator E8883A/ANHigh-Frequency SPICE E8884A/ANSPICE Netlist Translator E8880A/AN

HP RFIC Designer Premier E8889A/ANContains all of HP RFIC Designer Pro plus:Convolution Simulator E8885A/ANStatistical Design E8824A/ANRF System Models E8854A/ANAnalog Model Development Kit E8890A/ANSPICE Model Generator E8891A/ANNote: Throughout this datasheet, all moduleshave a product number with a suffix. Moduleswith an ‘A’ suffix are available node-locked only.Modules with an ‘A/AN’ suffix are availableeither node-locked or network licensed.

HP RFIC Designer

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Overview

HP developed this group of solutions for the accurate simula-tion and analysis of distributed elements and discontinuities typically found in MIC and MMICdesigns. It helps designers accountfor the affects of physical designon their circuits’ performance.

Library models for high-frequencytransistors and diodes are includ-ed (E8952A/AN and E8954A/AN),to define the circuit down to thecomponent level. Detailed circuit-level descriptions can be builtusing accurate microstrip, strip-line, suspended stripline, andcoplanar waveguide models. And a statistics capability (E8824A/AN)allows you to check the manufac-turability and anticipated yield ofyour design.

Suite Capabilities

HP Microwave Circuit Designersuite is available in two versions:

• HP Microwave Circuit

Designer Pro suite focuses on frequency-domain analysisfor linear and non-linear circuitsby using HP’s new HarmonicBalance Simulator (E8882A/AN).This simulator gives steady stateresults represented as a complexfrequency spectrum. Improve-

ments in this simulator allowmuch larger circuits to be simu-lated, faster, using less memorythan in previous versions of harmonic balance.

• HP Microwave Circuit

Designer Premier suite addsanalysis capability to the Prosuite. The addition of the Circuit Envelope Simulator(E8883A/AN) to the suiteenables you to extend harmonicbalance to include time-varyingeffects. This allows for the efficient analysis of analog and digital modulation of a carrier signal, certain phase-locked loops (PLL), automaticgain control (AGC), videoswitching, and other time-varying events. You can trace a complex signal through a circuit and examine it at everypoint to find out where, and to what extent, the signaldegrades. RF System Models(E8854A/AN) add behavioralmodeling capability to the cir-cuit-level modeling provided. If a model is not provided, theAnalog Model Development Kit(E8890A/AN) gives you a conve-nient way to add custom models.

The Premier suite also addsLayout (E8902A/AN), so thathybrid-circuits or MMIC designerscan do physical design. You canchoose to build your circuits ineither the schematic window orthe layout window. To manufac-ture the circuit or send it to themechanical designer, Layout’soptional translators help with thatpart of the job. Layout also servesas the entry point for our optionalelectromagnetic simulator HPMomentum (E8921A/AN).

HP Microwave Circuit Designer

HP Microwave Circuit

Designer Suite Configurations

Microwave Circuit Designer Pro E8911A/ANDesign Environment E8900A/ANData Display E8901A/ANLinear Simulator E8881A/ANHarmonic Balance Simulator E8882A/ANStatistical Design E8824A/ANMicrowave Transistor Library E8952A/ANHigh-Frequency Diode Library E8954A/AN

Microwave Circuit Designer Premier E8912A/ANContains all of Microwave Circuit Designer Pro plus:Circuit Envelope Simulator E8883A/ANRF System Models E8854A/ANAnalog Model Development Kit E8890A/ANLayout E8902A/ANNote: Throughout this datasheet, all moduleshave a product number with a suffix. Moduleswith an ‘A’ suffix are available node-locked only.Modules with an ‘A/AN’ suffix are availableeither node-locked or network licensed.

Features and Benefits• Provides accurate simulation and analysis of distributed elements and

discontinuities to analyze the effects of a circuit’s physical design. • Allows large circuits to be simulated faster, using less memory.• Includes a statistics capability to check manufacturability and anticipated

yield of designs.• Processes time-varying effects to allow signals to be traced to point of

degradation.• Provides physical layout capabilities and optional translators via the

Layout module.

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Overview

The RF Board Designer suitesaddress the challenges of board-level RF design. The suites rangein capabilities, from basic linearanalysis with RF Designer to com-plex modulation analysis andphysical design with RF BoardDesigner Premier.

Overall, RF Board Designer suitesallow you to create your boardfrom concept to manufacturing.System simulation allows analyz-ing RF system block diagrams forperformance tradeoffs. Test yourdesign with the multiple circuitsimulators (Linear, HarmonicBalance, Circuit Envelope), thencompare the results with mea-sured data. Optimize for best performance using Discrete ValueOptimization and vendor SMTparts. Create the physical designincluding SMT part footprints,then generate the artwork andbills-of-material to manufacturethe board. If the RF design mustbe combined with analog/digitalcircuitry, links to third party EDAsolutions like Mentor Graphics*can be used.

Suite Capabilities

HP RF Board Designer is avail-able in three versions:

• HP RF Designer is a low-cost suite that provides linearcircuit simulation on the PC.You can analyze S-, Z-, Y-, and H-parameters, noise figure, group delay, and more,plus optimize performance.Some functionality is restrictedcompared to the base modules,and expansion is limited to theLayout Basic module only.Designs created are compatiblewith RF Board DesignerPro/Premier.

• HP RF Board Designer Pro

improves on the RF Designercapabilities. It is fully expand-able and has no functionalityrestrictions in linear simulation.You can analyze nonlineareffects with Harmonic Balancesuch as mixer noise figure and large-signal S-parameters.By including common RF part models and vendor SMT parts,manufacturing yield analysisand optimization can be performed.

• HP RF Board Designer

Premier adds capabilities to the Pro suite. It provides thecapability to analyze how yourcircuit handles complex modula-tion schemes via eye diagramsand adjacent channel powerration, and the ability to createand simulate the multilayerboard layout.

HP RF Board Designer Suite Configurations

HP RF Designer E8940A*Design EnvironmentData DisplayLinear SimulatorOptional:Layout Basic E8944A**LayoutGerber Translator

HP RF Board Designer Pro E8942A/ANDesign Environment E8900A/ANData Display E8901A/ANLinear Simulator E8881A/ANHarmonic Balance Simulator E8882A/ANStatistical Design E8824A/ANRF Passive Circuit Models E8950A/ANRF Transistor Library E8953A/ANRF Passive SMT Library E8956A/AN

HP RF Board Designer Premier E8943A/ANContains all of RF Board Designer Pro plus:Circuit Envelope Simulator E8883A/ANLayout E8902A/ANMultilayer Interconnect

Models E8951A/ANRF System Models E8854A/AN

* Some functionality is restricted:• 9-port limitation on linear simulation• Two types of optimization (random, gradient) supported• File I/O only; instrument I/O not included• Available node-locked for PC platforms only• Not expandable with other modules, except with the purchase of E8941A RF Designer to Unbundled.

** Some functionality is restricted:• Gerber Translator only (DXF not included)• One-way schematic to layout design synchronization only• Does not support layout simulation• Available node-locked for PC platforms only• Not expandable with other modules, exceptwith the purchase of E8945A Layout Basic toUnbundled

Note: Throughout this datasheet, all moduleshave a product number with a suffix. Moduleswith an ‘A’ suffix are available node-locked only.Modules with an ‘A/AN’ suffix are available either node-locked or network licensed.

Features and Benefits• Allows circuit- and system-level models in a single schematic.• Permits frequency, time, and mixed time/frequency simulations. • Provides multiple optimization techniques, over 90,000 vendor parts,

and the ability to acquire measured data from instrumentation.• Incorporates a high-frequency layout solution with vendor part footprints,

EM simulation, DRC, and artwork generation in several output formats.• Offers links to third-party EDA solutions and libraries to ensure efficient

design flows.

Mentor Graphics* is a trademark of Mentor Graphics Corporation in the U.S. and other countries.

HP RF Board Designer

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The HP Advanced Design Systemis composed of approximately 50EDA modules that include designcapture and layout solutions, sim-ulators, model sets, libraries, andtranslators.

Included in this section aredescriptions of the DesignEnvironment and Data Displaymodules, as well as the DesignEnvironment’s instrument servercapabilities. These modules formthe basic platform and providethe user interface for almost allother HP Advanced DesignSystem modules and designsuites.

Design Environment

Design Environment

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Design Environment

Project organization for all filesassociated with a design, includ-ing data files, subnetworks, cus-tom artwork, and user settings, is automatically provided by theDesign Environment. All of thesefiles are ASCII text files availablein system default or user-speci-fied directories. Projects can provide current revisions of adesign, as well as older iterationsand alternate design approaches.Because all networks of a projectare maintained together, designsor portions of designs may be re-used without the need to copy them first.

The user interface was designedto have the look and feel of popu-lar PC office tools. Toolbars, component palettes, icons, andkeyboard shortcuts all provideeasy access to frequently usedfeatures. System and circuit elements can be selected frompalettes and placed with themouse; they are inserted alongwith their parameters onto thepage, ready for connection bywiring or transmission line.Component parameters can beedited on-screen, as can compo-nent types (for example, a resistor can be changed to acapacitor simply by typing in the

Features and Benefits• Includes schematic editor for

graphic manipulation and entryof RF and DSP designs.

• Allows designs and data files tobe structured in your preferredhierarchy.

• Comes with easy-to-learn, flexible user interface.

• Integrates RF/DSP/EM designtechnologies into one user inter-face, eliminating need for sepa-rate tools and file transfers.

• Offers extensive ability to customize the environment for ease of use.

Overview

The Design Environment is agraphical environment for the creation, simulation, and docu-mentation of RF and DSP designs.It provides the integration anddesign capture framework forplugging in our other modules,including simulators, layout, and libraries.

Design entry of RF and DSPdesigns is provided through aschematic page that offers bothpull-down menus and a commandtoolbar, either of which may becustomized. Components can beaccessed through logically-organized palettes, as well as textual library lists or a librarybrowser dialog. From theschematic, one or more simula-tions may be specified, controlled,and launched. Designs may beused as subnetworks to otherdesigns through the schematicpage; parameters can be passedto such subcircuits, which thenserve as custom models.

new name, eliminating the needfor deletion and rewiring). A fullon-line help facility that includesboth context-sensitive commandhelp and on-line documentation is provided.

The Design Environment provides the integration of all theHP Advanced Design Systemdesign technologies in one userinterface. Circuit simulations ofvarious components may beembedded into system simula-tions; planar electromagneticanalysis may also be performedon part or all of a circuit, and thedata fed into further circuit simu-lations. (EM simulation may beperformed without need of a filetranslation or explicit meshing).Designs may be created and edit-ed from both the schematic andthe layout, allowing you to workin either the electrical or physicalrepresentation, whichever bettersuits a given design.

Design Environment (E8900A/AN)

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Design Environment

Ability to customize the environ-ment is provided through theApplication Extension Language(AEL), a C-like language that canbe used for a wide variety oftasks. Because Advanced DesignSystem’s application interface iswritten with AEL, your own cus-tomizations can interact exten-sively with the system. AEL canbe used for such things as gener-ating custom libraries and layoutroutines, querying the databasefor design information, settingsystem preferences and options,and overriding higher-level de-fault configurations with thosefor a specific project or user.

Instrument Server

The instrument server capability is built into the DesignEnvironment, and provides a con-trol facility for bi-directional dataexchange with all instrumentssupported by the HP AdvancedDesign System. You can acquiredata from network analyzers,spectrum analyzers, and oscillo-scopes. Such data can be used to represent individual compo-nents, instead of datasheet orequation data; it can also be usedas a real-world simulation source.

The instrument server requireseither an HP-IB card or aNational Instruments GP-IB cardto be present in the computercommunicating with the instru-ment.

For network analyzers, rectangu-lar S-parameters are captured andstored.

Supported Network

Analyzers:

HP 8510B,C HP 8702HP 8703 HP 8719HP 8720 HP 8722HP 8752 HP 8753Wiltron 360

For spectrum analyzers, amplitude vs. frequency data iscaptured.

Supported Spectrum

Analyzers:

HP 71100A HP 71200AHP 71201 HP 71210AHP 8560 HP 8561HP 8562 HP 8563HP 8566A,B HP 8567AHP 8568A,B

For oscilloscopes, voltage vs. timedata is captured.

Supported Oscilloscopes:

HP 54100A,D HP 54110DHP 54111D HP 54120HP 54121 HP 54122HP 54123 HP 54710HP 54720 HP 54750

Other Supported

Instruments

HP 70820A Microwave TransitionAnalyzer — for this instrument, arange of data acquisition is possi-ble, including complex amplitudevs. frequency; complex amplitudevs. time; and table frequencies.

Additional Models

The HP Ptolemy module alsoincludes models that allowdesigners to download simulationdata to various instruments.Please see page 21.

File I/O

The Design Environment supportsthe import and export of Series IVmask (.msk) files as well as theimport of HPGL/2 files.

HP Advanced Design System sup-ports the following file formats forreading files into and writing filesout of the dataset:

• Touchstone

• A number of formats of MDIF:MODEL_MDIF, P2D, S2D, IMT, SPW, TIM, T2D, SDF*, GEN_MDIF

• Citifile (for file read only)

• Rawfile* Supports HP 89441 Vector Signal Analyzer

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Design Environment

Data Display

(E8901A/AN)

Features and Benefits• Allows graphical display of

simulation results, with a full setof plot types, trace types, andannotation of plots and traces,to better understand designperformance.

• Permits storage and retrieval of previous simulation resultsfor viewing and comparison toongoing design simulations.

• Provides ability to view andmanipulate data in customequations and expressions.

• Autoscaling for data fit andmarkers allows users to isolateand review data points quickly.

Overview

The Data Display module allowssimulation results to be viewedgraphically, much as they appearon analyzers and other instru-ments. Graphs can be customizedwith a choice of markers, colors,line styles, and captions. Portionsof plots can be instantly enlarged,and multiple data display win-dows can view the same data file,giving you the ability to look atyour data in several ways simulta-neously. Plot types include rectan-gular, polar, Smith (includingimpedance, admittance, andimpedance plus admittance),stacked rectangular (multiple y-axes overlaid onto one x-axis),and listing columns. Trace typesinclude line, scatter, histogram,digital, spectral, and “bus trace”(display of binary data for awhole bus, up to 128 bits width).

Both plots and traces allow choiceof line thickness, color, and linestyle. Plots can be annotated witha full range of drawing elements,including lines, rectangles, circles,text, polygons, and polylines.

Through its uses of a conceptcalled “datasets”, the Data Displaymodule allows you to slice yourdata for viewing and graphicalanalysis in any manner. Datasetsmaintain persistent storage of simulation results so that you canpull out all the data related to anysingle parameter or simulationcontrol factor — you don’t have to resimulate to create a differentview of your data. The results ofdifferent simulations in differentdatasets can be plotted to thesame Data Display window, allow-ing you to make comparisons.

The ability to manipulate data indatasets with your own equationsmeans that you can study the simulation results with flexibility.Dialog boxes show you all the data available to help you buildyour equations. Many useful ex-pressions, such as eye diagrams,histograms, adjacent-channelpower ratio, fast Fourier trans-forms, and VSWR are built in.

Autoscaling of axes on plots is provided to enable best fit of dataand regular tick mark spacings.Manual scaling is allowed as well.Markers are also available, allow-ing you to obtain a read-out of specific data values at any givenpoint. Delta markers enable you to look at incremental trace valueswith respect to a reference pointon that trace.

Configuration Detail

Requires the Design Environmentmodule (E8900A/AN).

13

Simulators

Circuit Simulation

Modules

HP Advanced Design Systemgroups its circuit analysis capabil-ity by simulator type. If you havemultiple simulators available, theappropriate simulator engine isselected automatically based onthe type of analysis you want toperform.

The following circuit simulatorsare available:

• Linear Simulator for linear andsmall signal S-parameter analyses

• Harmonic Balance Simulatorfor steady-state response frommixers, oscillators, and poweramplifiers

• Circuit Envelope Simulator foranalyzing complex modulation

• High Frequency SPICE to ana-lyze transient and/or start-upeffects

• Convolution Simulator toaccount for dispersion and skineffects in High-FrequencySPICE

Simulators

14

Overview

Linear frequency-domain circuitsimulation is used to analyze andoptimize RF and microwave cir-cuits (e.g., amplifiers, oscillators,couplers, filters, matching net-works) that operate under linearconditions. The technology can beapplied to the design of passiveand small-signal active circuitsused in wireless, RF, microwave,surveillance, radar, and othercommunication applications.

Once the circuit is drawn, thissimulator allows you to check thetopology automatically for uncon-nected pins and wires. The simu-lator then performs all necessarylinear measurements such as S-, Z-, Y-, and H-parameters, cir-cuit impedance and admittance,reflection coefficients and VSWR,gain, loss, noise, unilateral gain,noise figure, input/output noisetemperature, group delay, stabilityfactor, stability measure, andnoise-gain-stability circles. Inaddition, the simulator can per-form Swept Parameter Analysis,such as noise figure versus achange in a component value.

The simulator’s extensive passive and small-signal activedevice-model libraries includemany of the parts needed for the high-frequency designs,including improved multilayercoupled-line element models. Thesimulator also can perform linearanalysis with nonlinear models atuser-defined DC bias. And itoffers a parametric subnetwork-ing feature that allows customiz-ing and the use of any existingsubnetwork from another design.

Simulators

A Statistical Design packageuses the Monte Carlo method to predict yield by simulating aproduct’s manufacturing processwhere the units produced haverandomly-varying componentvalues (e.g., amplifiers, mixers).This helps to identify whichcomponents in your designrequire tighter control than others. A component’s pass/failstatus is determined by compar-ing your design’s simulated per-formance to your design’s actualrequirement. Yield is thendefined as the percentage of units passed.

A Symbolically-Defined Device(SDD) and a Frequency-DefinedDevice (FDD) allow you to createa user-defined model by specify-ing, on the circuit schematic, algebraic relationships for theport variables without having towrite source code.


Requires the Design Environmentmodule (E8900A/AN). The simula-tor includes the Circuit Modelslisted on page 18.

Linear Simulator

(E8881A/AN)

Features & Benefits• Offers parametric subnetwork-

ing for design customizationand convenience.

• Permits variables, equationsand functions specific to eachsubnetwork.

• Permits generalized noiseanalysis with temperature.

• Offers circuit optimization formaximizing performance.

• Contains microstrip, stripline,Finline, and Coplanar wave-guide models.

• Allows creation of user-definedlinear models and output equa-tions for design flexibility.

• Capable of back-annotating theDC solution at all nodes directlyonto the schematic, withouthaving to resimulate.

• Includes Monte Carlo analysisto predict manufacturing yieldprior to production.

• Provides Symbolically-DefinedDevice (SDD) and Frequency-Defined Device (FDD) to allowsimulating large- and small-signal behavior of a nonlineardevice without having to write C code.

• Offers SDD ability to modelhigh-level circuit blocks suchas mixers or amplifiers resultingin faster simulation runs.

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Circuit Envelope

Simulator (E8883A/AN)

Features and Benefits• Simulates sophisticated modu-

lated signals in high-frequencycircuits whose characterizationwas previously impractical orimpossible with SPICE orHarmonic Balance.

• Speeds the design of moderncommunication circuits basedon CDMA or TDMA technolo-gies.

• Optimizes circuits in the timedomain for best modulationcharacteristics, such as VCOfrequency settling time.

• Characterizes RF feedbackloops to aid in the design ofphase-locked loops andAutomatic Gain Control circuits.

• Efficiently analyzes higher-order(3rd, 5th, 7th) mixer intermodu-lation products and predictsspectral regrowth of amplifiersand mixers.

Overview

The HP Circuit Envelope Simulator allows the sophisticat-ed, modulated signals found intoday’s communication circuitsand subsystems to be efficientlyand accurately analyzed. The sim-ulator analyzes amplifiers, mixers,oscillators, and feedback loops inthe presence of modulated ortransient high-frequency signals.

Post-Processing Measurements

In all analyses, node voltages andbranch currents are computedand stored for display withoutresimulation. Complex user-defined post-processing functions,such as integration of a spectrum,conversion of simulation data tomatch formats of published wire-less standards, vector and matrixoperations, can also be accom-plished within the post processingdata display environment. PopularSPICE-type sorted listing of cir-cuit noise contributors is nowavailable for linear and nonlinearnoise analyses.

Performance Optimization

All circuit and system simulatorscan work in conjunction with tendifferent optimizers, ensuring thatyou obtain the best performancepossible from your designs.Please see page 24 for details.

Frequency-Defined Device

The FDD Model enables nonlineardevices, such as phase and fre-quency detectors, VCOs, modula-tors, and frequency multipliers, tobe more naturally described in thefrequency domain, rather than inthe time domain.

Another class of the FDDs can beused in both frequency and timedomain. An example is a clock orcarrier-recovery circuit whoseoutput frequency is based on theinput zero-crossing trigger-timeinterval.


Requires the Linear Simulator(E8881A/AN) and the DesignEnvironment (E8900A/AN).

Simulators

Harmonic Balance


Features & Benefits• New technology provides sig-

nificant improvements in memo-ry usage and simulation times.

• Simulates and optimizes nonlin-ear steady-state response ofcircuits.

• Offers swept variable analysis,parametric subnetworks, andlarge signal S-parameters.

• Capable of performing and dis-playing complex user-definedpost-processing functions.

• Frequency-Defined Device(FDD) is a powerful model usedfor nonlinear, behavioral model-ing in both frequency and timedomains without having to writeC code.

Overview

This fast Harmonic Balance simulator is especially useful for the design of nonlinear cir-cuits used in wireless RF andmicrowave communication sys-tems. The simulator is based on a new Krylov-subspace iterativesolver algorithm that offers signif-icant improvements in speed andmemory usage over previous ver-sions of this simulator. It simu-lates and optimizes the nonlinearsteady-state response of ampli-fiers, multipliers, mixers, oscilla-tors RF system models, etc. Itprovides performance measuressuch as DC bias, mixer-noise figure, oscillation frequency andphase noise, large-signal S-para-meters, and power-added efficien-cy. And it offers swept variable(e.g., power, frequency or circuitparameter) analysis, parametricsubnetworks, and large-signal S-parameters.

16

Simulators

In Comparison

to Harmonic Balance

Instead of representing the modulated signals as the sum of Fourier harmonics, as in theHarmonic Balance simulator,Circuit Envelope technology computes the modulation infor-mation in the time-domain, leav-ing only the RF carrier and the LOfor fast, accurate simulation inthe frequency domain. CircuitEnvelope technology is thereforefaster than a regular harmonicbalance simulation and also con-sumes less computer memory. Inaddition to its efficiency, CircuitEnvelope can analyze RF tran-sient response such as PLL locktimes, which Harmonic Balancecannot.

Time-Domain Optimization

In addition to simulating theinstantaneous amplitude, phaseand frequency of any signal har-monic, you can also optimize circuit-transient performanceusing the new time-domain optimization capabilities in HPAdvanced Design System. Forexample, you can optimize for the transient response of AGCsand for the locking time of phase-lock loops.


Requires the Harmonic BalanceSimulator (E8882A/AN), theLinear Simulator (E8881A/AN),and the Design Environment(E8900A/AN).

High-Frequency SPICE


Features & Benefits• Analyzes low- and high-

frequency, linear and non-linearlarge circuits in the time-domain.

• Directly uses high-frequencymodels such as microstrip andstripline transmission lines,bends, and gaps.

• Annotates on the schematic thecomplete solution at time=0.

• Provides time-domain optimiza-tion, overload-alert warning,swept-variable analysis, user-defined measurements and volt-age, and current probes at anylabeled node in the design.

• Time- to frequency-domaintransform allows RF designers to view results in the frequency-domain.

Overview

High-Frequency SPICE is particularly suited to time-domain analysis of large high-frequency RFICs that have thou-sands of transistors. It is used toanalyze the steady-state responseof mixers, oscillators, amplifiers,and other circuits. It is also usedto verify transient behavior, suchas start-up times in oscillators,filter step-function responses,pulsed RF network responses,high-speed digital and switchingcircuits, and more.

This simulator has been com-pletely re-designed. It now offersall the regular features of SPICEtransient analysis plus improvedconvergence for large circuits andsuch additional features as DCback-annotation to the schematic.In addition, the simulator is ableto use many high-frequency mod-els, such as microstrip transmis-sion lines, bends and gaps, with-out requiring the user to trans-

Circuit Envelope’s technology lets you analyze modulated andtransient RF signals by employinga hybrid time- and frequency-domain approach. It samples thecomplex modulation envelope(amplitude and phase, or I and Q)of the carrier in the time domainand then calculates the discretespectrum of the carrier and itsharmonics for each envelope timesample. Thus, the output from thesimulator is a time-varying spec-trum from which useful informa-tion, such as PLL frequency-vs-time transients, ACPR (adjacentchannel power ratio ), EVM (errorvector magnitude) and NPR(noise power ratio) can bederived.

In Comparison to SPICE

Because Circuit Envelope simulation samples the modula-tion envelope instead of the carrier, it has an inherent speedefficiency over SPICE. UnlikeSPICE, the modulation amplitudeand phase of any carrier harmonicis directly accessible for displayor time-domain optimization with-out the need for intermediatepost-processing. Where SPICEhas to rely on lumped-elementapproximations, Circuit Envelopesimulation can include accuratefrequency-domain models, suchas S-parameter data or microstripdiscontinuities.

17

can accurately analyze the effectsof discontinuities, dispersion,skin effects, and losses in trans-mission lines. The simulator canalso produce transient nonlinearanalyses with respect to optionalswept variables.

It can accurately simulate thefrequency-dependent behavior ofdistributed elements, such asmicrostrip and stripline, whichcannot be analyzed properly bySPICE-type tools. The results aremore accurate, at the expense oflonger simulation time. UnlikeHigh-Frequency SPICE, theConvolution Simulator can alsosimulate circuits that containcomponents characterized withmeasured S-parameter data, andit is particularly suitable for ana-lyzing transient conditions wherethe effects of dispersion and dis-continuities are significant.

It allows user-defined measure-ments, and voltage and currentprobes of designs. User-definedmeasurements can be manipulat-ed mathematically using the sim-ulator’s built-in post-processingcapability. The time to frequency-domain transform feature allowsRF designers to view the outputresults in the frequency domain.


Requires the High-FrequencySPICE Simulator (E8884A/AN).

Simulators

form the models into RLC equiv-alent circuits or revert to convo-lution. This is made possible byrepresenting these frequency-domain analytic models in termsof their Laplace transforms. InHigh-Frequency SPICE, the fre-quency dependent elements aremodeled with an approximationthat neglects some of the fre-quency dependent effects, suchas dispersion and high-frequencyloss, resulting in faster simula-tions. For more accurate fre-quency models with dispersioneffects and high-frequency loss,the Convolution Simulatorshould be used in conjunctionwith the High-Frequency SPICEsimulator, at the expense oflonger simulation times.

High-Frequency SPICE supportsextensive non-linear modelssuch as MOSFETs, MESFETs,and BJTs, and lumped and dis-tributed models such as capaci-tors, inductors, resistors, andsingle and coupled transmissionlines. It can perform nonlineartransient analyses with respectto optional swept variables. Forexample, you can plot the tran-sient response of an amplifierwith respect to another chang-ing variable such as power orcomponent value. When yourdesign is analyzed, circuitbranch currents and node volt-ages are calculated at each timestep and can be saved for mea-surement or subsequent prob-ing. The complete DC solutionat t=0s can be back annotatedto the schematic for viewing.

Additional capabilities of thissimulator are time-domain opti-mization, overload alert (forchecking breakdown voltage,excessive currents and powerdissipation), and user-definedmeasurements. User-defined

measurements can be manipu-lated mathematically using thebuilt-in post-processing capabili-ty. The time-domain to frequen-cy-domain transform featureallows RF designers to view theoutput results in the frequencydomain.

Configuration Detail:

High-Frequency SPICE requiresthe Linear Simulator(E8881A/AN).

Convolution Simulator

(E8885A/AN)

Features and Benefits• Accurately analyzes effects of

discontinuities, dispersion, skineffects, and losses in transmis-sion lines, all of which areimportant at high frequencies.

• Extends the capability of theHigh-Frequency SPICESimulator (E8884A/AN) byincluding arbitrary frequency-domain data files such as S-parameters.

• Allows swept-variable analysisfor reaching optimum solutions.

• Time- to frequency-domaintransform allows RF designersto view results in the frequency-domain.

Overview

The Convolution Simulator is an advanced time-domain simu-lator for high-frequency circuits.This simulator requires a High-Frequency SPICE license to run. It extends the capability of the High-Frequency SPICESimulator (E8884A/AN) and canhandle circuits that contain dis-tributed elements and S-para-meter data used for components.It can analyze circuit start-upconditions and transients and

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Nonlinear Models

• MESFET/HEMT Models

- Curtice quadratic- Curtice cubic- Advanced Curtice- Statz, et. al. (Raytheon)- TOM scaleable- HP Root MESFET/HEMT- EEFET3 and EEHEMT1- EETOM1- Materka and Modified

Materka- Tajima

• BJT Models

- Gummel-Poon, NPN, and PNP; with and without sub-strate terminals

- EEBJT2- VBIC- Philips MEXTRAM

• MOSFET/JFET Models

- N and P MOSFET- HP Root MOSFET- EEMOS1- BSIM1,2,3 MOS- MOS level 1,2,3- Philips MOS Model 9- Advanced Curtice JFET

• Diode Models

- HP Root- PN diodes

Passive Element Models

• Transmission Line Components

• Microstrip elements- Junction and discontinuity

models- Single and multiple coupled

lines with skin-effect loss and frequency dispersion

- Coupled line filter section- Sidewall and cover effects- Thin-film capacitors and

resistors- One-, two-, and four-port

interdigital capacitors- Four-, six-, and eight-finger

Lange Couplers- Tapered via hole, bond-wire,

and ribbon

Circuit Models

An extensive set of passive andactive linear and nonlinear modelsworks with each of the circuit sim-ulators.

HP EEsof Semiconductor

Device Models

The following bias-dependentmodels function both as nonlinearand linear models over the entireoperating bias range of the device.HP EEsof’s libraries of commer-cial devices are designed to workwith these models.

• The EEFET3 is a scaleable, biasdependent, empirical MESFETmodel. It accurately models bothDC and RF characteristics on awide class of devices

• The EEHEMT1 model is ascaleable, bias dependent,empirical HEMT model

• The EEMOS1 is a bias-depen-dent power MOSFET model

• The EEBJT2 model is a semi-physical, quasi-static, analyticalBJT model. It was designed toaccurately model the behavior ofNPN and PNP transistors in allregions of bias and in all deviceconfigurations

• The HP Diode Model is HPEEsof’s diode model

Public Domain

Semiconductor Device

Models

Linear Models

• Hybrid Pi and T-equivalent bipolar transistor

• Bipolar transistor models withalpha and beta current gains

• FET models with and withoutsource resistance

• FET noise models

• Dual-gate FET

• PIN diodes

- Spiral and rectangular inductors and interdigital capacitor

• Stripline elements- Single and coupled trans-

mission lines with skin-effect loss

- Offset Stripline- Junction and discontinuity

models•Tees•Cross

• Suspended substrate elements- Single and coupled transmis-

sion lines with skin-effect loss

- Multilayer printed circuit board coupled lines (up to 10 lines and 7 di-electric layers)

• Coplanar waveguide- Single and coupled lines- Junctions and

discontinuities

• Distributed elements, including ideal, physical, andcoaxial transmission line withcoupling

• Rectangular waveguide

• Finline models

• General lumped element mod-els, including resistors, capaci-tors, inductors, coupled coils,transformers, and gain, phaseshift, and time delay elements

• Antenna impedance elements

Simulators

SPICE Netlist Translator

(E8880A/AN)

Features and Benefits• Provides access to SPICE

netlists in the schematic.• Imports SPICE netlists from:

Berkeley SPICE 2G6, 3C, 3E; PSpice; HSPICE; HP SPICE.

• Allows existing SPICE netliststo be analyzed and optimizedwith a full range of high-frequency circuit simulators.

Overview

The SPICE Netlist translatorallows your existing designs in PSpice, HSPICE, and BerkeleySPICE to be translated into an HPAdvanced Design System subnet-work for analysis. Once in thesystem, the designs can be ana-lyzed with our full range of high-frequency circuit simulators (e.g., Convolution, S-parameter,Harmonic Balance, and CircuitEnvelope). This technology pro-vides more analyses and answersto your existing design problemsthan available from SPICE alone.This translator allows you to ana-lyze such problems as ACPR,mixer-noise figure and phase-locked loop transients.


Requires the Design Environ-ment module (E8900A/AN).

19

System Simulation

Modules

The following system simulationmodules are available in HPAdvanced Design System:

• HP Ptolemy

• RF System

HP Ptolemy Simulator

(E8823A/AN)

Features and Benefits• Provides hybrid dataflow and

time-domain design and simula-tion capability for mixed DSP,analog and RF systems.

• Comes with extensive DSP,communications, analog and RF model libraries to assemblereference systems quickly.

• Incorporates a user-defined C or C++ model builder that provides a “plug and play”approach to adding models toHP Ptolemy.

• Provides ability to co-simulatewith analog (High-FrequencySPICE) and RF (CircuitEnvelope) simulators.

• Comes with over 20 differentoptimization algorithms for fine-tuning system designs based onuser-specified design goals.

Overview

The HP Ptolemy Simulator is a system-level simulation anddesign solution based on a hybridof dataflow and timed-synchro-nous dataflow technologies. Itallows you to design and simulateDSP, RF and analog designs suchas RF and DSP receivers andtransmitters, modems, cellularphones, radar, etc.

Simulators

HP Ptolemy uses innovative simulation technologies to enabledesign and simulation of purelyDSP-based circuits such as FIR ilters or digital Costas loops. Inthe same environment, it also pro-vides the capability to analyze RFcircuitry chains such as amplifiers,mixers, and filters. The digital por-tion of the module helps you con-struct sophisticated algorithmsand simulate and observe perfor-mance via bit error rate, eye dia-grams, constellation diagrams andother measurements. The simula-tor’s RF modeling capabilityincludes the ability to add effectssuch as third order intercept,phase noise, frequency dependentVSWR effects and noise figures.HP Ptolemy also helps you modelreal-world effects in mixed analog,RF, and DSP systems, while accu-rately predicting performance.

Models

HP Ptolemy includes an extensiveset of models for designing DSPalgorithms and for behaviorallymodeling the analog and RF distortions that occur to signals in real-world analog or RF signalpaths. The model library includesover 500 models divided into threebroad groups: DSP models, com-munications, and analog / RF models (see HP Ptolemy Models,page 20).

1. DSP model library includes floating-point building blocks that range from simple multipliersand adders to complex equalizersand FIR filters. You can combinethese blocks quickly to exploreand optimize DSP algorithms with-out having to write code. Add theHP Ptolemy Fixed-Point Analysis(E8822A/AN) module to extendthese models to include fixed-point behavioral modeling.

20

Simulators

Co-Simulation

Between DSP, Analog and RF

By itself HP Ptolemy can simulatethe DSP, analog, and RF at thebehavioral level. However, youmay want to move from a purelytop-level behavioral simulation toa simulation with more realism.

With HP Ptolemy you can includea representation of a component,such as an amplifier, that has theactual transistors, capacitors, andother circuit-level parts, co-exist-ing with all of the behavioral mod-els. This co-simulation betweenHP Ptolemy and analog circuitry is possible through co-simulationarchitecture that is part of the HPAdvanced Design System. On oneschematic, in one user interface,you can build and co-simulate asystem that includes a mix of digi-tal and analog circuitry represent-ed at both behavioral and circuitlevel. HP Ptolemy can co-simulatewith RF System Simulator(E8853A/AN), Circuit Envelope(E8883A/AN) or High FrequencySPICE (E8884A/AN) for DSP sys-tem, analog circuit, and RF circuitcapability.

Optimization

The HP Ptolemy module alsoincludes an optimizer packagewith different algorithms for finetuning system design parameters.The optimizer includes innovativegenetic optimization techniquesthat can be applied to problemspreviously considered unsolvableby traditional optimization algo-rithms. The optimizer solution can also be used for things suchas optimizing gains, coefficientvalues, or filter bandwidths tomeet your set design goals such as BER (bit error rate) or adjacent channel power.

2. Communications libraryincludes a large number of blocksthat make it easy to assemble acommunications system and tostay focused on the section of thedesign you wish to investigate.The library includes items such asQAM modulators, demodulators,raised cosine filters, and a varietyof other standard communica-tions blocks.

3. Analog and RF models includes sophisticated modelingalgorithms developed from HP’syears of experience with analogand RF solutions. The libraryincludes mixer models, RF ampli-fier models, and oscillator mod-els. These models allow you toadd a variety of real-world distor-tions to communications signalssuch as phase noise from oscilla-tors, third-order intercepts, andnonlinear phase from IF filters.

With these sets, you can accurate-ly model everything in the com-munications signal path whetherthe part is analog, RF or DSPbased.

User-Defined Model Builder

HP Ptolemy provides an easy-to-use approach to adding custommodels using C or C++. You addmodels by specifying the numberof inputs, outputs, and parame-ters. The solution then builds thetemplate that handles the detailsof interfacing automatically. Yousimply add your engineering Ccode in the template, hit a buttonto compile, and you’re ready touse the model in the design.

After you have assembled a DSPdesign in block-diagram format,you can simulate and optimize thedesign using measures-of-perfor-mance such as bit error rate(BER), or by looking at eye diagrams or constellations.

HP Ptolemy Models

HP Ptolemy has extensive models for developing DSP andcommunications system designs.There are three groups of models:numeric, timed, and synthesiz-able. The numeric models simu-late DSP and digital algorithmsand models useful for basebanddesigns. The timed models arebehavioral analog and RF modelsincorporating accurate RF effects.These models are simulated withthe HP Ptolemy simulator.

Numeric Models

The numeric models in the following libraries provide models to build DSP and digitaldesigns at the base end.

• Numeric Communications:modems, convolutional coder,Viterbi decoder, phase shift,noise channel, raised cosine filter

• Numeric Control:bus merge, bus split, commutator, distributor, upsample, downsample fork

• Numeric Conversion:signal converters between different data types (float, integer, fixed, complex, timed)

• Numeric Logic: logic gates (AND, NAND, OR,XOR), registers, counters, latches

• Numeric Math: arithmetic functions, trigono-metric functions, add, multiply,max, average, integrate, log,modulo

• Numeric Signal Processing:FIR, IIR filters, equalizer, FFT

• Numeric Sources:constant, ramp, Gaussian, uniform, waveform, rectangle

• Numeric Special Functions:quantizer, limiter, Schmitt trigger, table

21

Circuit Envelope providesdetailed analog/RF (baseband ormodulated) analysis and simula-tion at the device level or with RF System Models.

High-Frequency SPICE providesdetailed analog/RF device-levelanalysis and simulation for model-ing secondary and subtle transient effects.


The HP Ptolemy Simulatorrequires the Design Environment(E8900A/AN).*RF System Simulator analyzes RF systemmodels and passive components. You mustadd a circuit simulator (e.g., Circuit Envelopeor High-Frequency SPICE) to run simulationswith semiconductor models. RF SystemModels (E8854A/AN) can also be used withCircuit Envelope, negating the need for RFSystem Simulator.

HP Ptolemy

Fixed-Point Analysis

(E8822A/AN)

HP Ptolemy includes a wide variety of DSP and communica-tions models that provide power-ful algorithm and modeling capa-bility using floating-point math.However, many DSP designs areimplemented using fixed-pointmath. This module adds fixed-point analysis and modeling capa-bility to the HP Ptolemy models.With this module designers canmodel fixed-point math effects(up to 256 bits using twos comple-ment or signed magnitude), bit-width effects (user-specifiable format), and quantization effects(rounding or truncations).


Requires HP Ptolemy Simulator(E8823A/AN) and the DesignEnvironment (E8900A/AN).

Simulators

HP vector signal analyzer allowsyou to bring real-world samples ofcomplex modulated digital signalsback into DSP Designer for use asdata sources in simulation. All ofthese measurement instrumenta-tion links make it easier to trans-late from design to hardwareimplementation and test.

Standard HP Ptolemy

RF Behavioral Modeling

HP Ptolemy includes RF modelsof mixers, amplifiers, noisy oscil-lators, etc. to model phase noise,third-order intercept, and frequen-cy-dependent effects (S21 only).

Optional Modules for

RF Modeling & Simulation

Many optional modules can be added to HP Ptolemy to supplement its analog/RF model-ing and simulation capability at levels of abstraction from systemlevel to circuit level. Optionalmodules include RF SystemSimulator* (E8853A/AN) and RFSystem Models (E8854A/AN),High-Frequency SPICE(E8884A/AN) and CircuitEnvelope (E8883A/AN).

Optional RF Circuit

Behavioral Modeling

Add the RF System Simulator and system models to model suchdetailed effects as intermodula-tion, noise figure, frequency-dependent effects (all S-parame-ters), harmonics, mixer spurious,and PLL transients.

Optional RF

Device-Level Modeling

Add Circuit Envelope and High-Frequency SPICE modules to HP Ptolemy to enable detailed circuit-level modeling of RF andtransient effects.

Timed Models

The models in the followingTimed libraries are for simulatinganalog and RF devices. Theyincorporate many RF phenomena,such as gain compression, S-parameters, noise figure, andintermodulation distortion, thatare very important in communica-tions.

• Timed Data Processing:binary coder, π/4 DQPSKdecoder, IQ coder, QPSKdecoder, symbol converter, symbol splitters

• Timed Filters:Bessel, Butterworth, Chebyshev,Elliptic, Gaussian, RaisedCosine

• Timed Linear:RF delay, phase shifter, splitter, integrate and dump

• Timed Modem:AM, DQPSK, FM, FMSK, MSK,PM, QAM, QPSK

• Timed Nonlinear:RF gain, mixer, RF multiplier,phase comparator

• Timed Source:impulse, N_tones, pulse, QAM,ramp, sinusoid

Additional Models

HP Ptolemy includes two additional models that allowdesigners to download simulationdata to an arbitrary waveformgenerator, vector signal analyzerand logic analyzer. The link to theHP arbitrary waveform generatorenables you to create, in DSPDesigner, complex modulated signals that can be downloadedand recreated in analog form foruse in actual hardware testing. A similar setup is available so thatdigital test vectors created in asimulation can be easily down-loaded to a logic analyzer andused as a test source for DSPhardware. Finally, a link to the

22

Simulators

RF System Simulator

(E8853A/AN)

Features and Benefits• Allows high-accuracy linear

and nonlinear simulations ofcomplete RF systems at the top level.

• Permits simulation of behavioralmodels and device-level modelsfor improved system verifica-tion.

• Has built-in measurements forforward- and reverse-powergain, intercept point, noise,dynamic range, etc. to accom-modate a wide range of designrequirements.

• Has extensive model set ofamplifiers, mixers, modulators,demodulators, phase-lock-loopcomponents and switches, fordesign flexibility.

• Contains a unique RF systembudget analysis that allowsusers to examine dozens of sys-tem measurements (TOI, 1dBc,power, gain, noise figure, etc.)at the system- or device-levelfor each component in the system regardless of circuittopology.

• Computes complete spectraincluding harmonics and inter-modulation and mixer-spuriousand noise for highest accuracy.

Overview

Engineers who develop completesystems of high-frequency compo-nents will find this simulator valuable. High-frequency circuitryposes a design challenge due tothe wave nature of the signal.Interactions between the variousparts of the system make it difficult to achieve desired costand performance objectives. Thetechnology built into this simula-tor helps to solve these problems.

The RF System Simulator pro-vides the ability to model an RFsystem with accurate block-levelmodels that can be replaced laterwith device-level models for fur-ther verification.

RF System Simulator is comprisedof four simulation technologies:linear, Harmonic-Balance, CircuitEnvelope, and RF system perfor-mance measurements. The linearsimulator is identical to theE8881A/AN Linear Simulator butrestricted to passive componentsand/or linearized system modelsof amplifiers and mixers. Thenonlinear simulator adds the ability to analyze nonlinear sys-tem models as well as passive circuitry. This capability is identi-cal to the E8882A/AN HarmonicBalance Simulator except semi-conductor models cannot be usedunless Harmonic Balance is alsoavailable. When digitally modulat-ed spectra are needed, the CircuitEnvelope simulator can be used.

(Please note that the RF SystemSimulator will not analyze simula-tions containing semiconductormodels unless a license for thesemiconductor models, as well as the appropriate circuit simula-tor license, are available).

A set of measurements tailoredfor RF system designers is alsoprovided. These include:

• Forward and reverse gain

• Forward power and reflectedpower

• Intercept point and intermodu-lation levels, and gain compres-sion

• Noise power, noise figure, andnoise-equivalent bandwidth

• Power spectrum I & Qenvelopes (if Circuit Envelopeis included)

• Mixer spuriousSpurious-free dynamic range,SNR, SINAD, and others

• S-parameter

A majority of these measurementscan be applied to each node in the system as part of the budget simulation.

Because full bi-directional nonlinear simulations using general topology are performed,the highest possible accuracy can be achieved, including higher-order harmonics and intermodula-tion distortions. In addition, HP’s Harmonic Balance andCircuit Envelope technologiesreduce simulation time and mem-ory usage to allow a large numberof tones in system simulation.

Models

See RF System Model set(E8854A/AN) on page 33.


Requires the Design Environmentmodule (E8900A/AN) and DataDisplay (E8901A/AN).

23

Simulators

Other Simulation

Solutions

HP Advanced Design System’s circuit and system simulators areaugmented by the electromagnet-ic simulation capabilities of:

• HP Momentum

• Standalone Momentum

These solutions are also augment-ed by the yield optimization capa-bilities of:

• Statistical Design

Momentum/Planar

EM Simulator

(E8921A/AN)

Features and Benefits • Offers “edge mesh” for better

characterizing the current-crowding behavior of high frequency signals.

• Uses adaptive frequency sam-pling (AFS) to give the highestfrequency sweep resolution fora minimal number of actualsolved frequencies.

• Has sidewalls (waveguidemode) to simulate the effects ofplacing a circuit near a pack-age sidewall.

• Incorporates box resonancemode to model package effectsand to find if box resonancesoccur in the frequency range ofinterest.

• DC operating point includedwith S-parameters for circuitsimulation that needs bias flow-ing to an active device throughthe S-parameters from HPMomentum.

• Simulates smaller circuits, withclose interactions, up to 4 timesfaster.

Overview

HP Momentum helps take theuncertainty out of physical designby performing accurate electro-magnetic analysis directly fromthe layout of HP Advanced DesignSystem. It is designed to analyzemultilayer planar geometries andprovide results in the form of S-parameters. You can then usethese results directly in HP’s circuit simulators includingHarmonic Balance, Convolution,and Circuit Envelope. With theuse of the optional SPICE ModelGenerator (E8891A), S-parame-ters can be used to produce aSPICE-equivalent circuit in for-mats that are compatible withseveral industry versions ofSPICE.

The HP Momentum simulator is based on the method-of-moments technology that is par-ticularly efficient at analyzing planar conductor and resistorgeometries. Planar structures ondifferent dielectric layers can beconnected together with vias.Slots can be drawn on groundplanes and their interactions effi-ciently solved, because only theslots are meshed, not the groundplane.

Since HP Momentum is part of HP Advanced Design System, it is now available on the PC underWindows NT and Windows 95.


Requires the Design Environ-ment (E8900A/AN), Data Display(E8901A/AN), and Layout(E8902A/AN).

Standalone Momentum

(E8920A)

Features and Benefits• Provides capabilities of

Momentum for designers whodo not need other HP AdvancedDesign System solutions.

Overview

If you are looking for the capabilities of Momentum(E8921A) but do not need to integrate with other HP AdvancedDesign System solutions, thenStandalone Momentum is the sim-ulator you should use. StandaloneMomentum gives the same electro-magnetic simulation capabilities as the integrated version, but pro-vides layout and a non-expandableversion of Project Design Environ-ment and Data Display. Non-expandable means that the circuitsimulators and other design solu-tions of HP Advanced DesignSystem are not available for thisproduct. This dedicated solutionwill provide S-parameters in eitherthe Touchstone file format or the HP CITIfile format, for use withother simulators.

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Performance

Optimization

Performance optimization letsyou specify a range of device or component values and thenautomatically compute the nomi-nal values that best meet yourperformance specifications. AllHP Advanced Design System simulators come with a family ofperformance optimizers that canbe applied to different problems.The optimizers are grouped intothree distinct categories: continu-ous-value, continuous- and/or discrete- value, and discrete-value.

Continuous-value optimizers

• Gradient

• Gradient Min/Max

• Quasi-Newton

• Least P

• Min/Max

Continuous- and/or discrete-valueoptimizers

• Random

• Random Min/Max

• Random Max

• Genetic

Discrete-value optimizer

• Discrete Value

This helps you understand whichcomponents in your designrequire tighter control than others. A component’s pass/failstatus is determined by compar-ing your design’s simulated per-formance to your design’s actualrequirement. The yield is thendefined as the percentage of units passed.

A yield optimization feature auto-matically adjusts nominal compo-nent values to increase predictedmanufacturing yield. This featurecan be applied to both linear andnonlinear circuits and systems. Itemploys a technique called designcentering, where the end result isa design that is able to tolerateunavoidable component varia-tions due to manufacturing, envi-ronmental, and modeling errors.

Compact statistical sensitivitydata is displayed on histograms tohelp you determine the Red-Xcomponents. Sensitivity displaysalso allow component toleranceassignment and nominal compo-nent value adjustment forincreased yield.

Tolerance assignments and distri-bution are available to the compo-nent parameters through devicelibrary information or in the formof normal (Gaussian), uniform, orarbitrary user-defined distribution(e.g., a bimodal distribution).


Requires the Design Environment(E8900A/AN) and any simulator.

Simulators

Statistical Design

(E8824A/AN)

Features & Benefits• Analyzes and optimizes manu-

facturing yield prior to produc-tion.

• Determines Red-X componentsthat need to be controlled forhigher production yield.

• Enables designers to compen-sate for unavoidable compo-nent variations.

• Provides the capability andaccuracy of traditional MonteCarlo analysis in a fraction ofthe time normally required.

• Allows post-production tuningto analyze and predict produc-tion yields for designs thatemploy tunable elements.

• Offers a data display featurethat allows yield and sensitivitydetermination at a glance.

Overview

The Statistical Design Packageprovides a solution for designersfaced with the need to designproducts for high-volume produc-tion. For low-volume production,this product ensures product reli-ability. The solutions in this pack-age include Yield Analysis, YieldOptimization, Design Centering,and many others that allow you togo beyond standard yield analysis.

The Statistical Design Packageuses the Monte Carlo method topredict yield by simulating a product’s manufacturing processwhere the units produced haverandomly-varying component values (e.g., amplifiers, mixers).

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HP DSP Synthesis

HP DSP Synthesis technologyincludes models, code genera-tors, simulators, and a compara-tor — driven by a powerful synthesis engine. Modules within this family include:

• Synthesis Engine

• VHDL Models & CodeGeneration

• Verilog Models and CodeGeneration

• Adaptive WaveformComparator

• PC VHDL Simulator

• PC Verilog Simulator

• PC Verilog &VHDL Simulators

• UNIX VHDL Simulator

• UNIX Verilog Simulator

• UNIX Verilog & VHDLSimulators

DSP Synthesis Products


26


Synthesis Engine

(E8836A/AN)

Features and Benefits• Provides estimation, schedul-

ing, binding, and RTL schematicgeneration to optimize high-level designs.

• Provides a summary of non-inferior design space fromwhich you can select resourceand performance combinations.

• Identifies components most frequently used and their limita-tions for bottleneck analysis.

• Automatically schedules theorder of operations in thedesign to minimize executiontime.

Overview

The synthesis engine of DSPSynthesis performs several majortasks in the transition from system-level block diagram toRegister Transfer Level (RTL)hardware description language.These tasks include estimation,scheduling, binding, and RTLschematic generation. The objec-tive for the Synthesis Engine is tooptimize the high-level design(using resource sharing, pipelin-ing and other techniques) devel-oped in DSP Designer accordingto your constraints. The output isan RTL description of the designin Verilog or VHDL. The schedul-ing and binding algorithms aresimple to use and require minimaluser interaction, unless you wishto specify a partial design as astarting point.

Estimation Capability

Estimation is used prior to syn-thesis and helps eliminate inferiordesign choices while reducingdesign times. The estimationengine provides you with a first-cut look at the chip area and performance.

Unlike other tools, DSP Synthesisenables designers to easily keeptrack of which constraints pro-duce which designs. This helps in the refinement of hardwaredesigns.

Area Estimation

The area estimator considers theimpact of components, registers,multiplexers, wiring, memory, I/Opads and unused components.Because register and multiplexerareas are not known to vary sig-nificantly with design, theirimpact on performance is not sig-nificant. Thus, one pass throughthe complete design phase canprovide the register and multi-plexer estimates. Memory areamay be estimated, assumingarrays in the specification arestored in memory. The number of I/O pads are estimated by theperformance required, and thenrounded-up to the best packagingavailable.

Performance Estimation

There are two main performancemetrics used in design synthesis:latency and throughput. Latencyis the total time taken to executethe algorithm on one set of inputdata. Throughput is the numberof solutions produced by the algo-rithm every unit time. (This isidentical to saying that through-put is the number of input datasets consumed per unit time.)

Latency is the premier metricused in non-pipelined design,which is preferred when the inputdata does not arrive very fast orarrives at irregular intervals. Onthe other hand, if the input dataarrives rapidly and at regularintervals, as in most DSP designs,pipelined design style is preferredand the performance is thenjudged by the throughput of thedesign.

The estimation capability enablesyou to make an informed decisionon the expected area-performancemetrics of the final design withoutgoing through the exhaustive andcomputationally expensive pro-cess of generating the actualdesigns. Estimation solutions provide answers to the followingtwo fundamental questions:

• If I use this many components inthe design, what will the perfor-mance be?

• If I want the design to achievethis much performance, what isthe minimum number of compo-nents required?

The estimation engine uses thebehavioral specification, clockcycle, and component delays toestimate a design space containingnon-inferior designs that span alarge spectrum of choices, fromslow and inexpensive designs tofast and expensive designs. Usingthe design space as a guide, youcan select those designs of inter-est and send them through the fullsynthesis process.

Design Constraints

and Specification Entry

In order to provide more guidance in the setting of designconstraints, DSP Synthesis pro-vides a series of tabbed dialogsthat you step through to specifyvarious design constraints. Thesetabbed dialogs include a spread-sheet specification entry dialog for tabular data, a dialog forlibrary selection, and a dialog fordesign style selection. Moreover,DSP Synthesis integrates thedesign constraint entry with theestimation solution, further assist-ing you in determining the design constraints.

27

Additionally, DSP Synthesis will,through a tabular summary, indi-cate the estimated resource-usageprofile to help identify resourcebottlenecks (high-utilization vs.low-utilization) and make appro-priate implementation decisions.

Bottleneck Analysis

Through a bottleneck analysis,you can gain important insightinto a design. For example, youcan identify which componentsare used most and determine the heavily-utilized componentslimiting the performance. You canalso determine the under-utilizedcomponents in a design. If cost isan important factor, some of theseunder-utilized elements can beshared to reclaim area. Throughthis unique capability, the finaldesign can be refined beyond thestandard synthesis capabilities.

Scheduling Capability

Once the estimation is run and the results are presented, you canchoose one of the designs to syn-thesize. The Synthesis Enginethen performs scheduling on theselected design. The purpose ofscheduling is to order the opera-tions in the design to minimize the execution time of the entiredesign. The following features canbe performed with the schedulingcapability of DSP Synthesis:

• Schedule basic blocks: sched-ules sequence of instructions

• Pipeline loops

• Schedule non-pipelined blocks

• Schedule pipelined specifica-tions and loops

Binding Capability

After the schedule is determinedfor a design, hardware resourcesare assigned to handle the opera-tions in the design. This bindingprocess offers you the followingfeatures:

• Allows complex sharing of components

• Generates steering logic automatically

• Handles partial designs to allowflexibility in synthesis

• Permits trade-offs betweencomponents and interconnectareas

• Minimizes area

• Generates data path and control path

The binding task is identical forboth pipelined and non-pipelineddesigns. In addition to bindingresources, the Synthesis Enginealso produces the control signals.The algorithm is very flexible inthat several different objectivescan be used, such as minimizinginterconnect area, maximizingtestability of the design, and mini-mizing the area subject to meetingclock-cycle requirements.

You can also specify a fixed number of registers, in whichcase this number overrides minimizing the register count. You may wish to specify a partialdesign as the input, thus impart-ing your experience to the designprocess. Multifunction compo-nents can also be handled proper-ly. For example, an 8-bit addition-al instruction can be executed ona 12-bit or an 8-bit adder and thebinding algorithm determines thebetter choice. In addition, whenyou specify extra resources, suchas registers, the Synthesis Engineconsiders the tradeoff betweenthese extra resources and thewiring and steering logic area.

Pipelined vs. Non-pipelined

The Synthesis Engine treatspipelined and non-pipelineddesigns separately. The non-pipelined design space consists of average execution time andnumber of major resources, whilethe pipelined design space con-sists of expected throughput andnumber of major resources. Thequantity of major componentsand their impact on throughput(in the case of pipelined design)and average execution times (for non-pipelined design) will be estimated.

Design Space Exploration

After estimation is run, theSynthesis Engine provides aspreadsheet/tabular summary of the superior design space. This table displays the estimatednumber of resources (both over-all total and number of eachresource type) and estimated performance (throughput forpipelined and latency for non-pipelined) for various designimplementations. From this table,you select which resource andperformance combination(s) theSynthesis Engine should pursue.

Instead of requiring you to selecta single candidate resource/per-formance combination, performthe synthesis process, and thenselect another candidateresource/performance combina-tion and re-start the synthesisprocess, DSP Synthesis providesyou with the ability to selectmore than one combination,queue the various design con-straints, and automatically directthe synthesis engine through eachdesign constraint combination.


28


Requires HP Ptolemy Fixed-Point Analysis (E8822A/AN), HPPtolemy Simulator (E8823A/AN),and the Design Environment(E8900A/AN).

Verilog Models and Code

Generation (E8835A/AN)

Features and Benefits• Provides models for use with

Synthesis Engine and HP Ptolemy.• Generates Verilog code.

Overview

The Verilog models are includedin the Synthesizable DSP library.Each of the models in this librarycomes with a Verilog description.These models can be used todevelop a design that can be usedwith the Synthe-sis Engine andcode generation. These modelscan also be simulated with HPPtolemy. The models include bar-rel shifters, adders, multipliers,counters, logic gates, and regis-ters.

Generation of an RTL designdescription is the vehicle bywhich synthesized designs areexported to ASIC vendors orFPGA solutions for implementa-tion. The design will start at ahigh level of abstraction (behav-ioral level) and transformationswill proceed until the design isinstantiated in terms of parame-terized modules or architecture-specific primitives or macros. Atthis level, the design is expressedas an RTL description and it issuitable for logic synthesis or forplace and route. RTL code gener-ation is part of the HDL code gen-erator which also performs thefollowing operations:


VHDL Models and Code

Generation (E8834A/AN)

Features and Benefits• Provides models for use with

Synthesis Engine and HP Ptolemy.• Generates VHDL code.

Overview

The VHDL models are included in the Synthesizable DSP library.Each of the models in this librarycomes with a VHDL description.These models can be used todevelop a design that can be used with the Synthesis Engineand code generation. These mod-els can also be simulated with HP Ptolemy. The models include barrel shifters, adders, multipli-ers, counters, logic gates, and registers.

Generation of an RTL designdescription is the vehicle bywhich designs are exported toASIC vendors or to FPGA solu-tions for implementation. Thedesign starts at a high level ofabstraction (behavioral level) andtransformations proceed until thedesign is instantiated in terms ofparameterized modules or archi-tecture-specific primitives ormacros. At this level, the design isexpressed as an RTL descriptionand it is suitable for logic synthe-sis or for place and route. RTLcode generator is part of the HDLcode generator, which performsthe following operations:

• Construct a correct and simulatable VHDL description

• Generate the VHDL test vectors for HDL simulation.This also includes collectingoutput test vectors for wave-form comparison

Schematic Generation

The Synthesis Engine generatesschematic representations of the structural implementationdesigns. These schematics showyou the optimized result of thescheduling and binding.

User Interface

Because DSP Synthesis is integrated with the rest of the HP Advanced Design System solutions, the same graphical userinterface guides you through theentire synthesis process. Thisincludes navigating the followingdesign steps:

• Selection of the behavioralschematic parts to be synthesized

• Designation of design constraints/specifications

• Choice of vendor libraries

• Usage of estimation techniquesfor reducing the design space

• Scheduling and binding

• Viewing of synthesized results

• Management of the numeroussynthesized implementations

• Generation of HDLs (Verilogand VHDL)

• HDL simulation interface

• Verification using HDL

• Comparison of adaptive waveform

Configuration Details

Requires VHDL Models and Code Generation (E8834A/AN) or Verilog models and CodeGeneration (E8835A/AN), HPPtolemy Fixed-Point Analysis(E8822A/AN), HP PtolemySimulator (E8823A/AN), and the Design Environment(E8900A/AN).

29

Overview

The Adaptive Waveform Comparator provides a design verification step for the transitionbetween a system-level design and RTL Hardware DescriptionLanguage implementation.

Design verification is the processof comparing the results of DSPDesigner with the results pro-duced by third-party HDL simula-tors on the generated HDL code.In the HDL code generationphase, the test bench from theuser interface is automaticallytranslated to an equivalent HDLcounterpart so a comparable setof test vectors is used.

Adaptive Waveform

Comparator Engine

Due to variations in set-up time, different simulators mayproduce waveforms that are notexact replicas of each other.These waveforms are neverthe-less functionally equivalent at thepoints of interest. Since the wave-forms are not exact duplicates ofeach other, a simple text-baseddiff provides little help with per-formance verification. The Adaptive Waveform Comparatorenables you to compare the func-tional equivalence of these twowaveforms.

The Adaptive WaveformComparator compares two waveforms at the points of inter-est, by aligning the two wave-forms so their variations due tolatency, component delays, andother factors can be handled auto-matically. The Adaptive WaveformComparator can also be used inthis way to compare the simula-tion results from DSP Designerand VHDL or Verilog simulations.

Display the

Comparison Result

The Adaptive Waveform Com-parator sends the comparisonresult to the Design Environmentand displays the results in twodigital waveforms, stacked one on top of the other. The resultingwaveforms are generated andaligned.


Requires Data Display(E8901A/AN).

HDL Simulator*

The DSP Synthesis suite includesa HDL simulator for either Verilogor VHDL. This simulator can beinvoked from within the DesignEnvironment. The RTL HDL filegenerated from the SynthesisEngine can be verified throughHDL simulation against the origi-nal behavioral simulation.

The VHDL simulator uses the VHDL description and testbenches created during VHDLgeneration. Invocation, compila-tion, and simulation is automati-cally accomplished and the VHDLoutput vectors are collected fordisplay or use with the adaptivewaveform comparison.*No part number (not sold separately).


• Construct a correct and simulatable Verilog description

• Generate Verilog test vectors for HDL simulation. This alsoincludes collecting output testvectors for waveform compari-son


Requires HP Ptolemy Fixed-Point Analysis (E8822A/AN), HP Ptolemy Simulator(E8823A/AN), and the DesignEnvironment (E8900A/AN).

Adaptive Waveform

Comparator

(E8833A/AN)

Features and Benefits• Accepts input from DSP Designer

and HDL simulations for comparison.

• Processes two waveforms todetermine closeness of fit in thearea of interest (user-defined time range or time delta from atrigger point).

• Generates a status report indicating the mismatch points and the overall degree of fitbetween the waveforms.

• Displays a graphical comparisonbetween two waveforms.

30

Digital Filter

(E8825A/AN)

Features and Benefits• Creates filter coefficients for

IIR and FIR in either fixed-point or floating-point formats.

• Enables design of Low-Pass, High-Pass, Bandpass,Bandstop, Multipass,Multistop, Differentiator,Hilbert transformer, RaisedCosine, Raised-Root CosineFilters.

• Automatically builds fixed- or floating-point versions ofthe designed filter in theschematic, for easy use insystem simulations and siliconimplementation.

• FIR filter-coefficient designmethods include Equiripple,Least Squares, and window-ing.

• IIR filter-coefficient design methods include Chebychev I,Chebychev II, Eliptic,Butterworth, and auto select.

• Filter order can be user-speci-fied or automatically calcula-tor-based on filter specifica-tions.

• Includes optimizer-weightingfunction to control filter designgoals

Overview

Because digital filters are one of the most common DSP circuits used, you need an efficient way to design, analyzeand create schematics for them.HP’s Digital Filter module works tightly with HP Ptolemy(E8823A/AN) to allow you to goeasily from filter specification tosynthesizable schematic imple-mentation.

Digital Filter allows you to create FIR and IIR filters by sim-ply entering frequency and ampli-tude specifications. Digital Filterthen designs the coefficients andallows you to analyze the filter in terms of frequency response,phase response, and impulseresponse. Digital Filter alsoallows you to compare floating-point and fixed-point filter perfor-mance for a specified bit width.


Schematic Generation

After the filter coefficients have been designed and refined,you can automatically createschematic implementations of thefilter in HP Ptolemy. Simply selectwhat form of the filter you wishto implement (cascaded secondorder, Direct form II, etc.) andDigital Filter builds up theschematic representation withfixed- or floating-point modelsand loads in the proper coeffi-cient values. This can be helpfulwith time-consuming problemssuch as a 128 tap FIR filter.

In summary, HP’s Digital Filtermodule works with HP Ptolemyto provide a quick and easy flow from filter specification toschematic design implementationand/or to silicon implementation(with DSP Synthesis).


Requires Design Environment(E8900A/AN).

Digital Filter builds this schematic for you automatically.

31

Model Sets

HP Advanced Design Systemincorporates models that permityou to simulate a wide variety ofboth DSP and analog circuitry.The model sets offered are:

• RF Passive Circuit Models

• Multilayer Interconnect Models

• HP Ptolemy Matrix Models

• RF System Models

• Antenna and PropagationModels

• Analog Model Development Kit

• SPICE Model Generator

Model Sets and Vendor Component Libraries

Model Sets and Vendor Libraries

32

ability to have models on multiplelayers. With the flexible multilayersubstrate definition, you choosehow many layers the substratewill have and the parameters thatdescribe a vertical cross-section ofthe multilayer structure.

The models available in theMultilayer Interconnect Modelsinclude:

• Multiple coupled lines (1 to 10)with variable widths and spacing

• Multiple coupled lines (1 to 16)with constant width, spacing,and layer

• Multiple coupled corners ofarbitrary angle (1 to 16) withconstant width and spacing

• Multiple coupled corners (1 to 16) with variable pitch,

constant width and spacing

• Multiple coupled slanted lines (1 to 16)

• Multiple coupled crossovers (1 to 8)

• Multiple coupled radial lines (1 to 5)

• Discontinuities such as gap,open stub, cross, tee, and vias

• Multiple layer (2 to 16) substratedefinition (metal and dielectricproperties)


Requires the Linear Simulatormodule (E8881A/AN) and theDesign Environment (E8900A/AN).


RF Passive Circuit

Models (E8950A/AN)

Features and Benefits• Provides a wide assortment of

common RF part models forboard-level design.

Overview

This module provides models for many common RF parts.When combined with other circuitmodels, users are able to betteranalyze a board-level design. The models provided are:

• Air-core inductors

• Tapped air-core inductors

• Balun transformers

• Toroidal ferrite-core inductors

• Broadband n2:1 Guanella transformers with ferrite

• Ruthroff 4:1 ferrite/transmissionline transformer

• Ferrite 0 degree and 180 degreeferrite hybrid combiner

• Wireline and Wirepac 90 degreereentrant couplers

• Ideal 90 degree and 180 degreehybrid couplers

• Chip capacitors

• Piezoelectric crystals with holder

• Transmission line transformers

• Multiple coupled resistive coils

• Resistive pads


Requires the Linear Simulatormodule (E8881A/AN) and theDesign Environment(E8900A/AN).

Multilayer Interconnect

Models (E8951A/AN)

Features and Benefits• Allows definition of multilayer

structures for PCB, MCM, or IC package analysis.

• Allows simulations fromschematics as opposed to EManalysis of layouts.

• Allows definition of complexstructures beyond microstrip orstripline configuration.

Overview

This module provides models for multiple coupled lines used inmultilayer structures such asprinted circuit boards, multichipdevices, and IC packages. Thesemodels allow for better analysisof anticipated layout effects, with-out requiring the HP MomentumPlanar EM simulator. There is aresultant trade-off in simulationspeed vs. accuracy. The effects of impedance, loss, crosstalk, anddelay are modeled with the under-lying 2-D electromagnetic fieldsolver used by these models. The advantages of the MultilayerInterconnect Models over micro-strip and stripline models are thata greater number of coupled linemodels are available, models canbe placed on any specific layer,and you do not need to specifymicrostrip or stripline operationbecause it is computed automati-cally.

These models are also a supersetof the printed circuit board models included in the LinearSimulator module. Key advan-tages over these models are easierparameter entry, more availablemodel configurations, and the

33

RF System Models

(E8854A/AN)

Features and Benefits• Contains complete set of block-

level RF models and measure-ments, which allow fast, accu-rate modeling of RF Systems.

• Offers compatibility with RF System Simulator and othersimulators.

Overview

This module provides RF systemmodels that allow system-levelanalysis. Circuit- and system-levelmodels can be combined foranalysis. The following modelsare provided:

• Gain blocks (nonlinear, bi-directional, seven differentnonlinearity specifications)

• Mixer (intermodulation table,seven different nonlinearities,LO and RF feedthrough, noise)

• Filter library (Butterworth,Chebyshev, Elliptic, Bessel,Gaussian, Nyquist, Low-PassFilter, Band-Pass Filter, Band-Stop Filter, High-Pass Filter)


• Modulators & Demodulators(AM, FM, PM, QPSK, π/4 DQPSK,IQ and arbitrary N-state modula-tors)

• Phase-lock loop components(VCO with phase noise, divide by N, frequency phase detector)

• Switch and algorithmic compo-nents (SPDT, DPDT, integrator,differentiator, sample and hold,sample quantizer, serial-parallelconverters, etc.)

• Linear and nonlinear data filemodels (.S2P, .S2D, .P2D)

• Passive elements (isolator, phase shifter, couplers, radio-link models, splitters, and attenuators)


Requires the Linear Simulator(E8881A/AN) or the RF SystemSimulator (E8853A/AN), and theDesign Environment (E8900A/AN).

HP Ptolemy Matrix

Models (E8826A/AN)

Features and Benefits• Provides over 50 matrix math

functions for both fixed- andfloating-point numeric data.

• Provides co-simulation link toMATLAB.

Overview

This module adds matrix process-ing capability to the HP PtolemySimulator. The Matrix Modellibrary includes everything fromsimple matrix math routines, suchas matrix adders and multipliers,to more complex routines, suchas matrix inversions and matrixsingular-value decomposition.With this module, system-leveldesigns can pass and manipulatematrix data in the same mannerthat scalar values can be manipu-lated in HP Ptolemy. The modelset also enables use of MATLABscripts in the HP Ptolemy environ-ment (co-simulation). Matrixmath capability makes construc-tion of sophisticated DSP algo-rithms very efficient and simple.


Requires the HP PtolemySimulator (E8823A/AN) and the Design Environment(E8900A/AN).

34

Analog Model

Development Kit

(E8890A/AN)

Features and Benefits• Improved and user-friendly

ANSI-C allows creation andcompiling of custom C-code circuit models, resulting infaster simulation time.

Overview

This kit allows you to create your own circuit and system element models, compile them,and link them into HP AdvancedDesign System. Written in ANSI-Ccode, these elements can be usedin linear, nonlinear, circuit enve-lope, transient, and convolutioncircuit simulations. Models cannow be created by simply speci-fying the symbol (which definesthe number of ports) and para-meters. The interface then auto-matically builds the C andschematic interface code (AEL)necessary to incorporate yourmodel into the Design Environ-ment. You simply add your engi-neering C code in the template,hit a button to compile, andyou’re ready to use the model in your design. The interface alsosupports Series IV Senior nonlin-ear models with little or no modification.


Requires the Linear Simulator(E8881A/AN) or the RF SystemSimulator (E8853A/AN), and the Design Environment(E8900A/AN).


Antenna and Propagation

Models (E8856A/AN)

Features and Benefits• Provides models of signal

propagation effects for system-level analysis of mobile commu-nication products.

• Offers verification environmentthat is in compliance with majorcellular standards.

• Permits modeling of loss, complex multipath, and fadingeffects for design flexibility.

Overview

This module helps designers ofmobile communication productsexamine how the dynamic radio-signal propagation channel affectsthe performance of the system.The models provided are compli-ant with the following cellularindustry standards: GSM (all scenarios), IS-97 CDMA, and IS-54 TDMA.

Each model has an option forurban, suburban, and rural path-loss prediction. The models arebased on a statistical treatment of electromagnetic equations governing radio wave propaga-tion. The models give you thecapability to evaluate the entirelink (transmitter/channel/receiv-er) of many wireless systems.Also included are base-stationand mobile-station antenna mod-els. These antenna models acceptinformation on location, eleva-tion, vehicle speed, and direction.

When used in a simulation, theradio propagation between two or more antennas is modeled in astatistical manner to produce multipath effects with Rayleighand Rician probability distribu-tions. Simulations involving multi-ple propagation channels, such as adjacent channel interferencetests or diversity systems, canalso be effectively modeled.


Requires the HP PtolemySimulator (E8823A/AN) and the Design Environment(E8900A/AN).

35


The SPICE Model Generatordevelops models using four different topologies:

• Ideal transmission line topology

• N-section ladder network

• Lumped Pi topology

• Rational polynomial representa-tion (HSpice or ApSim Spiceformats)

The first three models are low-frequency extraction from S-parameter data. The fourthmodel uses curve fitting to fre-quency data. The first three mod-els are applied when the frequen-cy data points in the S-parameterdata file are free of noise. If the S-parameter data is taken from anetwork analyzer, noise may bepresent in the low frequenciesand the rational polynomial repre-sentation should be applied.

The SPICE model generator alsoallows for full-chip verification inthe SPICE simulator after you’vedone the RF design in HPAdvanced Design System.


Requires the Design Environment(E8900A/AN).

SPICE Model Generator

(E8891A/AN)

Features and Benefits• Enables the generation of

SPICE models from S-parame-ter data to speed work flow.

• Develops models from four different topologies for designflexibility.

• Allows full chip verification onSPICE after having performedthe RF design.

Overview

The SPICE Model Generator letsyou convert a frequency-domainS-parameter characterization intoa model that SPICE can use. TheS-parameters can come from theHP Advanced Design System fre-quency-domain simulator, High-Frequency Structure Simulator,Momentum, or network-analyzermeasurement. This model genera-tor develops a netlist containing asubnetwork representing themodeled structure.

36


The following part/vendor partlibraries are available in the HP Advanced Design System:

• E8952A Microwave TransistorLibrary (chip FETs and BJTs,and HEMTs)

• E8953A RF Transistor Library(packaged BJTs and FETs, andMOSFETs)

• E8954A High-Frequency DiodeLibrary (PN and Schottky)

• E8955A Analog Parts Library(diodes, N and P channelJFETs, MOSFETs, and BJTs)

• E8956A RF Passive SMTLibrary (resistors, inductors,capacitors)

• E8957A Murata SMT Capacitorand Inductor Library (measure-ment-based GRH & GRMseries)

Vendor Libraries

Part of the power of HP AdvancedDesign System lies in its extensiveactive- and passive-device modellibraries. Palettes of model datafor over 90,000 popular devicesfrom numerous vendors are avail-able to place in your design. Awide range of SMT capacitors,inductors, and resistors are avail-able. The system’s active devicelibraries contain measurement-based, bias-dependent transistormodels that are backed by yearsof verification and experience. The SMTs contain physical layoutinformation as well as electricaldata.

Our extensive BJT, FET, and MOS-FET device libraries come com-plete with package layout informa-tion for each device so there is noneed to create the layouts manual-ly. Also, surface mount technology(SMT) libraries of resistors, induc-tors, and capacitors have bothelectrical and layout information.

37

HP Advanced Design System provides a variety of solutions to help you produce and test aphysical layout of your designs.These solutions include a graphi-cal editor, a design rule checker,translators, and a graphical cellcompiler.

Physical Design Products


38

Layout

(E8902A/AN)

Features and Benefits• Provides ability to build and

simulate circuits directly in the layout.

• Has wide range of output formats for layouts andschematics.

• Integrates with mask-making equipment.

• Provides extensive editing features for design flexibility.

Overview

The Layout module is a powerfulgraphical editor that allows inter-active physical design and simula-tion of PCB, RFIC, MIC or MMIClayouts. Layout can be used withoptional solutions that specifical-ly address the problems of high-frequency designs, help reduceerrors, and finish designs faster.

Optional modules that can beadded to Layout include:

• Momentum PlanarElectromagnetic Simulatorfor performance verification

• Design Rule Checker used intesting for layout errors

• Translators such as DXF,IGES, GDSII and Gerber

• Graphical Cell Compiler foradding custom parameter-ized layout AEL macros

Like the schematic editor, theLayout editor lets you select com-ponents for placement from agraphical palette of simulationmodels. You select a true-to-scale“ghosted” image of the compo-nent, select the proper orienta-tion, and place it in your design.

When you are ready to update the schematic, you can do sointeractively or automatically. Inthe interactive mode, you pick acomponent in the layout and drag its symbol into position inthe schematic. This gives you precise control over the schemat-ic. Changes made in either repre-sentation are tracked by theDesign Synchronization Engine(DSE), which is at the heart of the system. This insures that yoursimulations represent your latestchanges, and thus increase accu-racy. The DSE gives you the flexi-bility to choose how layout com-ponents are depicted in the schematic. For instance, you can simulate a meandering traceas an ideal electrical connection if it is part of your bias network, or simulate every discontinuityalong the trace for greater accura-cy at higher frequencies.

An important feature of theLayout editor is simulation ofLayout, which gives you the abilityto build and simulate the circuitdirectly in the layout. You canintermix circuits that are repre-sented in either schematic or lay-out; for instance, a complicatedmeander line may be easier todraw in the layout than in theschematic. You have the flexibilityto design in whichever representa-tion is necessary or more intuitive.

Layout Editor Features

• Work where it’s most natural:generate layouts from schemat-ics or schematics from layouts

• Cross-probe your circuit tocheck the schematic-layoutmatch

• Simulate layouts directly

• Freeze item positions inschematic or layout


• Place or delete items in yourschematic and layout simultane-ously

• Check nodal mismatchesbetween schematic and layout

• Reference designators (e.g., R1, TL2) automaticallygenerated on silk-screen layers

• Check for wires or unconnectedpins in layout

• Create or flatten hierarchy withone command

• Break traces or add tees totraces in one step

• Traces can be converted toequivalent circuits, shorts, ortransmission lines

• Trace corners can be rounded,chamfered, or square

• Step and repeat; rotate, scale,and mirror

• Insert, move, copy, stretch,delete, unlimited undo

• Process offsets correct forunder- or over-etching

• Attach or edit properties ofobjects

• Snap to pins, grid, or verticesplus new snapping modes: edge,circle center, intersection, andline center

• Unlimited number of layers;dozens of colors and fill patterns

• All-angles or orthogonal entry

• Simulation expressions can beutilized in layout

• Logical equivalent pins

• Correct interlayer connectionsare enforced

• Improved user interface

• Enhanced logical operators:merge, subtract, or, xor

• Ground-plane management

39

Layout Basic

(E8944A/AN)

Please see page 8 for a descriptionof this reduced-capability module.

Layout Basic is a non-expandableversion of layout. It can be addedto HP RF Designer (E8940A).

Artwork Translators

Many output formats are availablefrom Layout that link to otherdesign solutions.

Integration with mask-makingequipment is made possible withthe GDSII Stream File interface.Integration with mechanical CADsystems is made possible with theIGES interface, or the popularDXF translator for AutoCad(TM).The Gerber translator is widelyused in the production of PCboards. Thus, your designs can be connected to almost any otherpopular CAD system on the market.

The following translators are available:

Bi-directional translators:

• GDSII Translator (E8904A/AN)

• IGES Translator (E8903A/AN)

• EGS Generate/Archive (built in,no purchase necessary)

Output-only translators:

• DXF and Gerber Translator(E8906A/AN)


New Gerber Features

The Gerber Translator has beenupdated to be compliant with theextended Gerber RS274X stan-dard. This new standard formatincludes:

• Embedded format, unit anddata information

• Embedded apertures

• Custom aperture definitions

• Film control statements

• Multiple layers embedded in a single file

• Special polygon definitions

Additionally, the Gerber transla-tor has been enhanced with thefollowing features:

• More layer control — selectlayers to translate without mod-ifying the mask resource file

• A layer dialog box has beenadded where layers can beturned on/off

• Better Gerber file naming —mask layer name (and optional-ly mask layer numbers ) areused to identify layers

• Gerber file merging — a filmmerge menu enables the user tocreate a new Gerber file whichis a combination of mask layers

• Automatic Hole/Empty supportand embedded aperture tableusing Gerber Standard RS 274X


Layout requires the DesignEnvironment module (E8900A/AN).All Artwork Translators (GDSII,IGES, DXF & Gerber) require theLayout module (E8902A/AN).

AutoCad (TM) is a U.S. trademark of Autodesk, Inc.

40

Fast and Easy Operation

In addition to the ability to writecustomized rules, HP Design RuleChecker has a fast, automatedmode that prompts for simplespacing and width rules withoutrequiring you to write AEL code.For more complicated rules, theUser Interface focuses on ease ofuse, with the design rules enteredin an easy-to-understand processflow.

Since both HP Design RuleChecker and Layout operate with-in the same environment, designscan be drawn, checked, and edit-ed all with the same software.

When errors are encountered, HP Design Rule Checker automat-ically identifies the error type,magnifies that portion of the lay-out, and highlights the specificpolygon segments that break the design rule. Users can easilysequence through errors with themouse, either editing or ignoringreported errors. Error files canalso be saved and restored.


Requires the Design Environmentmodule (E8900A/AN) and theLayout module (E8902A/AN).

Design Rule Checker

(E8907A/AN)

Features and Benefits• Verifies PC board, hybrid, RFIC

or MMIC layouts.• Checks against user provided

rules.• Identifies the error type, magni-

fies that portion of the layout,and highlights the specific seg-ments that break the design rule.

Overview

HP Design Rule Checker is integrated in HP Advanced DesignSystem. It is used to verify PCboard, hybrid, RFIC or MMIC layouts generated by the system’slayout so you can catch criticaldrawing or design errors beforeyour circuit board or mask is fabricated. For example, if twotraces are placed too closelytogether on a mask, or if a tracewidth falls below a specified tol-erance, HP Design Rule Checkerwill identify and highlight theerror.

Flexible Rule Writing

Designs are checked against a setof rules provided by the user. Alldesign verification rules files arewritten in the system’s databaselanguage of AEL. You can easilywrite rules for checking polygonspacings, widths, and grid align-ment. You can write more compli-cated rules to check FET gate ori-entation, air bridge post separa-tions, etc. Once created, rulesfiles can be saved and reused forother designs.


Graphical Cell Compiler

(E8908A/AN)

Features and Benefits• Simplifies adding parameterized

artwork to schematics.• Provides rich set of controls for

artwork manipulation.

Overview

In the past, whenever layout artwork had to be added to aschematic, it was done as either a fixed footprint instance or as an artwork macro written in thedatabase language of AEL. Use of AEL is more flexible becauseartwork macros can be parameter-ized, but it is a manual processand requires familiarity with theAEL language. The Graphical CellCompiler in HP Advanced DesignSystem makes the job of addingparameterized artwork an easyprocess.

In general, controls are attached tolayout primitives to stretch, repeator move them. Controls can befixed values or parameterized andtied together with equations. Youdetermine the logical sequence forapplying controls to produce thefinal artwork, after which theGraphical Cell Compiler will pro-duce a compiled AEL macro. Thecompiled AEL macro can then beassigned to any schematic primi-tive or subcircuit.

Construction lines are used as control references and can beplaced at any angle relative to theobject. Operations such as stretch-ing, moving or repeating are donerelative to the control reference.The Controller Viewer gives youan easy way to see and modifywhich controls are defined and inwhat order they will execute.


Requires the Design Environmentmodule (E8900A/AN) and theLayout module (E8902A/AN).

41

Framework Links (sometimescalled integration modules) allowyou to integrate your HP designswith third-party vendors (e.g.,Mentor Graphics and CadenceDesign Systems*) to provide afully integrated process thatmaintains the integrity of yourhigh-frequency designs. Separateintegration modules are availablefor schematic and layout transfer,each utilizing the HP Interme-diate File Format (IFF) as theexchange mechanism. The HPIFF is an ASCII intermediate file for both the schematic andlayout transfers, allowing the HP Advanced Design System and EDA vendor solutions to beinstalled on different machines,platforms or sites.

Framework Links

Framework Links

*Cadence is a trademark of Cadence Design Systems, Inc.

42

Features and Benefits• Allows bi-directional schematic

transfers to speed and simplifydesign processes.

• Permits RF board and IC designschematics to be sharedbetween HP Advanced DesignSystem and Mentor GraphicsDesign Architect.

Overview

High-frequency circuits can be entered and edited on theschematic in either the MentorDesign Architect or the HP envi-ronment. All edited material canbe transferred to either environ-ment. All properties and designhierarchy are preserved throughthe translation. Simulation andhigh-frequency physical designmust occur in HP AdvancedDesign System. This preserves thehigh-frequency design featuressuch as specialized plots, testequipment I/O, optimization andtuning, data presentation types,and special analysis types. Mentorcomponent libraries can be usedfor simulation in HP Advanced

Framework Links

Design System, but HP simulatorproperties must be attached andpin/property attributes modified onany component for the simulator torecognize the part. The HP LibraryTranslator (E8969A/AN) is recom-mended to facilitate this.



Compatibility

This module is used in conjunctionwith the Mentor RF Gateway prod-uct (sold by Mentor Graphics) toprovide the complementary IFFschematic transfer. The MentorFalcon Framework Version B.2 and higher are supported.

Layout

Schematic

Library Library

Schematic

Simulation

Data Mgmt

Data Display

HP IFF

LibraryTranslator

Third Party CAD Tool HP EEsof

HP IFF Layout

Mentor IFF Schematic Translator (E8965A/AN)

43

Mentor IFF Layout

Translator (E8966A/AN)

Features and Benefits• Allows bi-directional layout

transfers from HP AdvancedDesign System to MentorGraphics Board Station, tospeed and simplify designprocesses.

• Permits physical designs to beshared between HP AdvancedDesign System and MentorGraphics Board/MCM/HybridStation.

• Transfers part footprints into HP Advanced Design Systemfor library creation.

• Offers single-button transfer ofHP schematic and layout toMentor Board Station for easeof use.

Overview

This integration module provides unidirectional layouttransfer between the HPAdvanced Design System andMentor’s Board/MCM/ HybridStation. It does not support directtransfer of physical designs fromthe HP Advanced Design Systemto Mentor’s IC Station (GDSII fileformat must be used).

With the Mentor IFF LayoutTranslator you can create andrefine the high-frequency physicaldesign in the HP Advanced DesignSystem, then transfer it to MentorBoard Station. Once in BoardStation, the high-frequency designis treated as a fixed high-frequen-cy region. This region is used as asingle logical part with ports onthe region boundary. It can bemoved and rotated like any otherBoard Station geometry, and anyboard can have a large number of

Framework Links

high-frequency regions. You control which parts in the high-frequency region are included inthe bill of materials (BOM) used inBoard Station. This allows pack-aged components to be includedin the BOM, while excluding vari-able components (like transmis-sion line elements).

The Mentor IFF Layout Translatoralso allows Mentor Board Stationcomponent geometry (“footprint”)to be transferred to the HPAdvanced Design System’s layout.When these component geome-tries are used in the HP AdvancedDesign System, and the design istransferred back to Board Station,the original geometry is usedinstead of being transferred again,reducing transfer time. A compo-nent geometry that has been trans-ferred must be merged with anappropriate model and its high-frequency simulator properties, in order to simulate it in HPAdvanced Design System. The HPLibrary Translator (E8969A/AN) isrecommended to facilitate this.


Requires the Design Environment(E8900A/AN), Layout (E8902A/AN),and Mentor IFF Schematic Tran-slator (E8965A/AN) modules(required for layout transfer topreserve the Mentor schematic-to-layout connectivity).

Compatibility

This module is used in conjunc-tion with the Mentor RF Gatewayproduct (sold by Mentor Graph-ics) to provide the complement-ary IFF schematic transfer. The Mentor Falcon FrameworkVersion B.2 and higher are sup-ported for uni-directional layouttransfer (HP to Mentor).

IFF Schematic Translator

(E8967A/AN)

Features and Benefits• Allows bi-directional schematic

transfers to speed and simplifydesign processes.

• Allows schematics to be sharedbetween HP Advanced DesignSystem and third-party EDAvendors such as Cadence.

Overview

This integration module providesbi-directional schematic transferbetween HP Advanced DesignSystem and all EDA vendors(other than Mentor Graphics) that support IFF schematic trans-lation. The module requires the IFF Schematic Translator fromthe vendor to complete the IFFtranslation. The schematic trans-fer functionality will be deter-mined by the EDA vendor’s prod-uct; its operation may be similarto the Mentor IFF SchematicTranslator but cannot be guaran-teed by HP.



Compatibility

A Cadence Composer IFFschematic translation moduleis included with this module. It supports the Cadence DesignFramework II version 9502 orhigher. Solutions are available forCadence Concept and ViewlogicPowerView from these vendors,not from HP EEsof. Please con-tact these vendors for informa-tion.

44

IFF Layout Translator

(E8968A/AN)

Features and Benefits• Allows bi-directional layout

transfers from HP AdvancedDesign System to third-partyEDA tools, to speed and simplifydesign processes.

• Allows physical designs to beshared between HP AdvancedDesign System and third-partyEDA vendors such as Cadence.

• Transfers part footprints into HP Advanced Design Systemfor library creation.

Overview

The IFF Layout Translator provides unidirectional layouttransfer between HP AdvancedDesign System and all EDA vendors (other than MentorGraphics) that support IFFschematic translation. The module requires the IFF LayoutTranslator from the vendor tocomplete the IFF translation. Thelayout transfer functionality willbe determined by the EDA ven-dor’s product; its operation maybe similar to the Mentor IFFLayout Translator but cannot beguaranteed by HP.



Compatibility

Solutions are available forCadence Allegro and InterceptTechnologies Pantheon fromthese vendors, not from HPEEsof. Please contact these vendors for information.

Framework Links

may not be interpreted in thesame fashion between HP andother EDA vendors. For example,a transistor may use a pin num-bering scheme that conflicts withthe HP simulation model; or thepin names for a capacitor may bedifferent (POS vs. PLUS). Forproper simulation within the HPAdvanced Design System, pin andproperty mapping is required.

The Library Translator is a semi-automatic solution that isable to read an IFF file containingthe EDA vendor parts. This allows you to view the existingpart properties, select what HPsimulation model the part shouldbe mapped to, edit the simulationmodel values, and potentiallyattach a footprint geometry. You can then export the enhancedpart definition to an IFF file. Partattributes/properties will be auto-matically converted by the HP IFF Schematic Translator. An HPlibrary is then created by readingthe IFF file of new parts and sav-ing this information into a userlibrary. After a library is created,all future imports/exports use theconversion information to convertdesigns being read in the HPAdvanced Design System orexported by it. The componenttranslation information can besaved to a file to facilitate incre-mental library updates in thefuture. With a component map-ping file, parts that are the sameare automatically translated andonly the new or changed partsneed to be re-mapped.


No licenses required.

Compatibility

Supports HP Advanced DesignSystem simulation models only.

Library Translator

(E8969A/AN)

Features and Benefits• Creates an HP-equivalent

library of third-party EDA vendor libraries for design flexibility.

• Allows mapping of pin andproperty attributes.

• Permits the addition of HP simulation model parameters.

• Comes with a ComponentTranslation Table that allowsincremental library updates.

Overview

The Library Translator allowsaccess to parts that exist in eitheryour electronic corporate database or your digital/analog EDAvendor-system data base. Themodule helps translate these parts libraries into an HP equiva-lent-parts library including simu-lation information. This facilitatesdesign transfer between HP andanalog design solutions by provid-ing common parts in both sys-tems. The Library Translator operates independently of the HP Advanced Design System and requires that the EDA vendorsolution be able to export/import an IFF schematic file.

In the HP Advanced DesignSystem a library part is composedof a schematic symbol, a physicalfootprint, and an electrical simu-lation model. In other EDA ven-dor solutions, a part may be justthe symbol and physical footprint.Part information may also includethe part number, statistical infor-mation, thermal information, cost,reliability, tolerance, etc. It is pos-sible that some part attributes

E8900ADESIGN ENVIRONMENT

E8881A Linear Simulator

E8965A Mentor IFF Schematic Translator

E8901AData Display

E8902ALayout

E8853ARF System Simulator

E8823AHP Ptolemy Simulator

E8967A IFF Schematic Translator

E8880A SPICE Netlist Translator

E8952A Microwave Transitor Library

E8953A RF Transitor Library

E8954A High-Frequency Library

E8956A RF Passive SMT Library

E8957A Murata SMT Capacitor Library

E8882A Harmonic Balance

Simulator

E8883A Circuit Envelope

Simulator

E8884A High-Frequency

SPICE

E8885A Convolution Simulator

E8950A RF Passive Circuit Models

E8951A Multilayer Interconnect Models

E8854A RF System Models

E8824A Statistical Design

E8890A Analog Model

Development Kit

Vendor Parts Libraries

Model Sets

for use with any simulator

for use with any circuit simulator

E8854A RF System Models

Model Sets

Framework Integration

E8921A Momentum

E8908A Graphical

Cell Compiler

E8907A Design Rule

Checker

E8966A Mentor IFF Layout Translator

E8968A IFF Layout Translator

Framework Integration

E8903A IGES Translator

E8904A GDSII Translator

E8905A Gerber & DXF Translator

Artwork Translators

E8969A Library Translator

E8826A HP Ptolemy Matrix Models

E8856A Antenna & Propagation Models

Model Sets

E8822A HP Ptolemy Fixed

Point Analysis

E8833A Adaptive Waveform

Comparator

E8825A Digital Filter

E8834A VHDL Models & Code Generation

E8835A Verilog Models & Code Generation

Model & Code Generation

HDL SimulatorsPC VHDL Simulator

PC Verilog SimulatorPC VHDL + Verilog Simulator

UNIX VHDL SimulatorUNIX Verilog Simulator

UNIX VHDL + Verilog Simulator

E8955A Analog Parts Library

E8891A SPICE Model

Generator

E8836ASynthesis Engine

45

Ordering Structure

Ordering Structure

Each of the modules in the diagram below can be ordered separately or is included in bundled suites. However, withthe exception of the Library Translator, Digital Filter and Adaptive Waveform Comparator, each module requires themodule connected above it. For example:The Convolution Simulator requires High-Frequency SPICE, Linear Simulator and Design Environment .The PC VHDL Simulator requires the Synthesis Engine, either the VHDL Models & Code Generator or the VerilogModels & Code Generator, HP Ptolemy Fixed-Point Analysis, the HP Ptolemy Simulator, and the Design Environment. The Library Translator, Digital Filter and Adaptive Waveform Comparator can be ordered independent of any othermodule.

46

HP Advanced Design Systemcourses are configured to meet the needs of distinct areas of com-munications signal path design,including RFIC, RF Board, Micro-wave Circuit, CommunicationsSystem, and DSP. Students learnabout topics that directly relate to their field of interest. Availablecourses include:

• HP Advanced Design SystemEssentials

• Using HP Advanced DesignSystem for RF and MicrowaveCircuit Design

• Using HP CommunicationSystems Designer

• Using HP DSP Designer

• Using HP DSP Synthesis andHDL for DSP Hardware Design

• HP Momentum for HP Advanced Design System Users

• AEL Programming for HPAdvanced Design System Users

• Physical Design and Customiza-tion for HP Advanced DesignSystem Users

Designers can attend classes atspecially-equipped training centersaround the world or arrange foron-site instruction at their compa-nies. Our training program givesdesigners the right start using HPEEsof’s powerful design software.

Additional Solutions

Additional solutions, which arenot integrated into HP AdvancedDesign System, are available fromHP EEsof to help you with relatedaspects of design. These include:

HP High-Frequency Structure

Simulator 5.0

For electromagnetic modeling ofarbitrarily-shaped, passive 3Dstructures.

In HFSS you’ll find such featuresas:

• Finite-element simulation andmesh engines that are fasterthan previous releases andreduce memory requirements

• A drawing package that pro-vides broad compatibility withother 3D drawing solutions

• A solid-model parts library thatpermits complex shapes andstructures to be entered

• Unlimited “undo” and 3D panand zoom flexibility, to save youtime and reduce errors in thedesign entry process

HP IC-CAP 5.0

A versatile device-modeling pro-gram in which we’ve incorporated:

• A user-friendly Windows-stylegraphical interface that makesyou more productive

• A flexible data manager thatallows you to utilize data fromexternal measurement databas-es and physical device simula-tion solutions

• A real-time graphical tuner thatshows you how each parameteris related to simulated deviceperformance

• Enhanced versions ofBSIM3v3.1 model, the PhilipsMOS Model 9, and the HP RootFET model to improve accuracyand ease-of-use

• Support for the HP E2050ALAN/HP-IB Gateway, whichallows remote control of testinstrumentation via the LAN,and the HP 8720D family of network analyzers for high-frequency device characteriza-tion

Support &Training

Customer Education

HP EEsof has dedicated signifi-cant resources to its on-going customer education program.Courses have been developed toenable you to become productiveas quickly as possible. Construct-ed to closely approximate thedesign process, students learn touse the software through solvingan engineering design problem.For example, our course titled“Using HP Advanced DesignSystem for RF and MicrowaveCircuit Designers” takes a stan-dard block diagram and worksthrough the design and simulationof each major component. HPEEsof courses explain all majorfeatures of the software and pro-vide application-oriented exam-ples of real-life solutions.Additionally, students typicallyspend over half their class timeworking on real-world lab exercis-es, ensuring a high degree of confidence when they return totheir workplaces.

Support, Training and Services

Description Model # Page #

Library Translator E8969A/AN 44IGES Interface Translator E8903A/AN 39GDS-II Stream Interface Translator E8904A/AN 39Layout E8902A/AN 38Layout Basic E8944A/AN 39Linear Simulator E8881A/AN 14Mentor IFF Layout Translator E8966A/AN 43Mentor IFF Schematic Translator E8965A/AN 42Microwave Circuit Designer Premier E8912A/AN 7Microwave Circuit Designer Pro E8911A/AN 7Microwave Transistor Library 36Model Sets 31Momentum (Planar EM Simulator) E8921A/AN 23Multilayer Interconnect Models E8951A/AN 32Murata SMT Capacitor Library 36Ordering Structure 45Performance Optimization 24Physical Design Products 37Platform Compatibility 48RF Board Designer Premier E8943A/AN 8RF Board Designer Pro E8942A/AN 8RF Designer E8940A/AN 8RF Passive Circuit Models E8950A/AN 32RF Passive SMT Library 36RF System Models E8854A/AN 33RF System Simulator E8853A/AN 22RF Transistor Library 36RFIC Designer Premier E8889A/AN 6RFIC Designer Pro E8888A/AN 6Simulators 13SPICE Model Generator E8891A/AN 35SPICE Netlist Translator E8880A/AN 19Standalone Momentum E8920A 23Statistical Design E8824A/AN 24Support and Training 46Supported Instrumentation 11System Requirements 48Synthesis Engine E8836A/AN 26Vendor Component Part Libraries 36Verilog Models & Code Generation E8835A/AN 28VHDL Models & Code Generation E8834A/AN 28

47

Index

Description Model # Page #

Adaptive Waveform Comparator E8833A/AN 29Analog Model Development Kit E8890A/AN 34Analog Parts Library 36Antenna and Propagation Models E8856A/AN 34Artwork Translators 39Circuit Envelope Simulator E8883A/AN 15Circuit Models 18Circuit Simulation Modules 13Communication System Designer E8850A/AN 3Communication System Designer Premier E8852A/AN 3Communication System Designer Pro E8851A/AN 3Convolution Simulator E8885A/AN 17Co-simulation 20Data Display E8901A/AN 12Design Environment E8900A/AN 9Design Rule Checker E8907A/AN 40Digital Filter E8825A/AN 30Documentation 48DSP Designer Pro E8821A/AN 4DSP Designer E8820A/AN 4DSP Products 25DSP Synthesis 5, 25DSP Synthesis PC Verilog E8830A/AN 5, 25DSP Synthesis PC VHDL E8838A/AN 5, 25DSP Synthesis PC Verilog & VHDL E8831A/AN 5, 25DSP Synthesis UNIX Verilog & VHDL E8840A/AN 5, 25DSP Synthesis UNIX Verilog E8832A/AN 5, 25DSP Synthesis UNIX VHDL E8831A/AN 5, 25DXF & Gerber Translator E8906A/AN 39Framework Links 41Graphical Cell Compiler E8908A/AN 40Harmonic Balance Simulator E8882A/AN 15High-Frequency Library 36High-Frequency SPICE Simulator E8884A/AN 16High-Frequency Structure Simulator 5.0 46HP HFSS 5.0 46HP Ptolemy Simulator E8823A/AN 19HP Ptolemy Fixed-Point Analysis E8822A/AN 21HP Ptolemy Matrix Models E8826A/AN 33IC-CAP 5.0 46IFF Layout Translator E8968A/AN 44IFF Schematic Translator E8967A/AN 44

Index

For more information, contact your local

HP Sales office or the nearest listing in

your telephone directory.

United States:

Hewlett-Packard Company

Test and Measurement Organization

5301 Stevens Creek Blvd., Bldg 51L-SC

Santa Clara, CA 95052-8059

(800) 452 4844

Canada:

Hewlett-Packard Canada Ltd.

5150 Spectrum Way

Mississauga, Ontario L4W 5G1

(905) 206 4725

Europe:

Hewlett-Packard

European Marketing Centre

P.O. Box 999

1180 AZ Amstelveen

The Netherlands

Japan:

Hewlett-Packard Japan Ltd.

Measurement Assistance Center

9-1, Takakura-Cho, Hachioji-Shi,

Tokyo 192, Japan

(81-426) 56-7832

Latin America:

Hewlett-Packard

Latin American Region Headquarters

5200 Blue Lagoon Drive, 9th Floor

Miami, Florida 33126 U.S.A.

(305) 267 4245/4220

Australia/New Zealand:

Hewlett-Packard Australia Ltd.

31-41 Joseph Street

Blackburn, Victoria 3130

Australia

(800) 629 485

Asia Pacific:

Hewlett-Packard Asia Pacific Ltd.

17-21/F Shell Tower, Times Square

1 Matheson Street, Causeway Bay

Hong Kong

Fax: (852) 2506 9285

http://www.hp.com/go/hpeesof

Data subject to change.

© 1998 Hewlett-Packard CompanyPrinted in USA ADS/TECH 3/98 POD 5966-2190E

Documentation

HP Advanced Design Systemcomes with complete on line documentation, as well as a hard-copy “Getting Started” manual tailored to your design process.These materials include engineer-ing examples to get you up andrunning quickly. In addition to on-line documentation, you canorder a set of hardcopy manuals:HP 8900AD (for the complete setof HP Advanced Design Systemmanuals) or HP 8820AD (for theDSP Designer manuals).

System Requirements

These are the system require-ments for the use of HP AdvancedDesign System on workstations(WS) and PCs.

Displays: High-resolution color(Super VGA, 1024/768, 15-inchmin.)

RAM: 64 MB min for WS; 64 MB min for PCs

Swap Space: 200 MB recom-mended for WS and PCs

Hard Disk: 500 MB recommend-ed for WS and PCs, plus swapspace

Security: In WS, a codeword is locked to an individual comput-er ID; in PCs the codeword is locked to an external deviceattached to the parallel port

For additional information on this subject, please contact your HP representative.

Platform

Compatibility

HP Advanced Design System products are supported on popularworkstations and PC platformsincluding:

• HP workstations running 9.x, 10.2

• Sun workstations running Solaris1.x to 2.x

• Intel/Pentium 90 MHz CPU orhigher running Windows 95 orWindows NT 4.0

Product Information

This data sheet describes HP Advanced Design SystemVersion 1.0

For additional information on relat-ed HP EEsof products please see:

Brochures: Literature#

HP Advanced Design System 5966-2870E

HP DSP Designer 5966-2869E

HP RFIC Designer 5966-2071E

HP RF Board Designer 5966-2872E

Data Sheets

IC-CAP 5.0 Modeling Suite 5965-7742E

HP Momentum 5963-7129E

HP/Mentor Graphics Integration 5963-6630E

HP High-Frequency StructureSimulator 5.0 5963-9794E

Transitioning to HP AdvancedDesign System 5966-4029E

Web Support

Bookmark www.hp.com/go/hpeesof.It is the URL of the HP EEsof website. The site contains detaileddescriptions of our products, services, documentation, supportorganizations, libraries, and more.

Documentation and System Requirements

hp advanced design system - university of texas at...

Documents