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7/26/2019 Honeywell PLC

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Honeywell ML -200A presentation by Pawan Kumar


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System Description

CPU redundancy- ndependent CPU rac! wit" Master# $ac!up CPU% switc"o&er 'rom Master CPU tobac!up CPU is (0 ms w"ene&er Master CPU 'ails)

Power supply redundancy 'or CPU # *+ rac!s)

,etwor! edundancy . in/ topolo/y pro&ides dualcommunication pat"s to *+ rac!s)

*+ networ! redundancy usin/ rin/ topolo/y networ!%built in twisted pair 'or local (00m1 or ber-opticnetwor!s 'or remote *+ 2!m1

$ase *+ capacity en"anced to 23404 352 slots 'rom36 bases1


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System Arc"itecture

As


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Analo/ *+ Modules

Analo/ input module ran/e includes current% &olta/e%7D # t"ermocouple)

Analo/ output modules are current # &olta/e outputtype)

Hi/" resolution% 68 bit

L9D status displays 'or U,*9+ conditions


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Di/ital *+ Modules

Di/ital *+ modules% c"annel density o' 4% 68% 32 # 8:points)

All di/ital *+ modules "a&e L9D 'or c"annel statusindication and are wit" p"oto coupler isolation)

Cate/ories; 2:


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Communication Module ML-200 "as specic communication module to support

open networ! communication at super&isory le&el%control le&el and de&ice le&el)

=ast 9t"ernet Modules=9net1; Peer-to-peer inte/rationwit" ot"er ML-200 systems o>ers scalable plat'ormand Modbus 7CP*P Master*Sla&e protocols pro&ideinter'ace to t"ird party SCADA*HM panels alon/ wit"

inte/ration wit" Honeywell?s 9@perion System) Serial Communication ModulesSnet1; Modbus

7U*ASC Master*Sla&e protocols are user denedprotocols 'or inter'acin/ wit" t"ird party de&ices)

Probus-DP Pnet1; Pro&ides inter'ace to systems and

eld de&ices o&er Probus-DP networ!% con'orms tonternational Standard o' 9, (0650% supports autobaud rate detect)

De&ice,et Dnet1; Pro&ides inter'ace to eld de&icesw"ic" communicate o&er De&ice,et networ!)


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Power Supply

$attery type; Man/anese Dio@ide Lit"ium $attery

,ominal


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CPU

Pro/ram Lan/ua/e; Ladder Dia/ram% SeFuential =unctionC"art% Structured 7e@t% and nstruction List &iew only1

Pro/ram memory; 3M$

Ma@imum number o' *+ bases; 36

Ma@imum number o' slots; 352 36 bases @ 62 slots1

Ma@imum base *+ Usin/ 8: C" D*D+ module; 23404 8:c" G352 slots1

Ma@imum *+ e@tension distance per node; 600m CA7(1% 2!m

=iber +ptic1 CPU operation mode; U,% S7+P% D9$U

CPU restart mode; Cold or Barm restart

Ma@imum number o' nodes; 36


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Parts # =unctions; +perationMode Switc"

+peration mode switc" U,*9M*S7+P U, Mode ; Pro/ram runnin/

S7+P Mode; Pro/ram stop

9M Mode ; +peration mode can be set by t"epro/rammin/ tool)

B"en !ey switc" is c"an/ed 'rom U, 9M% S7+P 9M operation mode retains t"e pre&ious mode)

B"en !ey switc" is c"an/ed 'rom 9M U,% 9M S7+P operation mode c"an/es to t"e altered mode)

' !ey switc" is not in 9M mode% operation mode orpro/ram download is not allowed by t"e pro/rammin/ tool)Howe&er% monitorin/ and data c"an/in/ are allowed)


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Parts # =unctions; L9D U,*S7+P L9D; S"ows operation status o' CPU module)

reen li/"t; U, modeI t"e module is in operation)

U, operation by operation mode switc")

U, operation by pro/rammin/ tool wit" operation mode switc" in 9M)

ed li/"t; S7+P modeI t"e module is in operation)

U, operation by operation mode switc")

S7+P operation by pro/rammin/ tool wit" operation mode switc" in 9M)

BA L9D; +,9LL+B1; Barnin/% +==; ,ormal 9 L9D; +,9D1; Critical 9rror% +==; ,ormal

$A7 L9D; =our di/it display o' t"e +peration Status

,ormal +peration

Barnin/

9rror

Displayin/ redundant status;

9D +,; Master*$ac!up CPU in redundant operation)

9D +==; Master*$ac!up CPU in sin/le operation)

MAS79 +,; CPU is operatin/ as Master)

MAS79 +==; CPU is operatin/ as $ac!up)

CPU classication ; CPU-A and CPU-$


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ContinuedJ Displayin/ e@tension networ! status; Displays

communication status wit" e@pansion base)

AC7 +, 9LL+B1; C"annel is in operation)

L,K +, 99,1; C"annel lin! is enabled)

, +, 99,1; in/ topolo/y is establis"ed in e@pansion networ!)

, +==; in/ topolo/y is interrupted and runs in a bus condition or

networ! is not establis"ed)


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Parts # =unctions;

Sync) Connector ; nter'ace connector between CPUs 'ormonitorin/ and data s"arin/)

eset*D) Clear switc"; esets CPU w"en switc" is set to t"ele't)

Le't Center; 9S97

Le't more t"an 3s Center; +&erall 9S97

Clears data w"en switc" is set to t"e ri/"t)

i/"t Center; clears memory area 'or M% auto-allocatedretain% /eneral data memory address)

i/"t more t"an 3s Center; Clears memory area 'or M%

autoallocated retain% eneral Data Memory Address and Area Caution; Data clear is only per'ormed in S7+P mode)


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Parts # =unctions; Main $ase

6 $ase attac"ed /uide "ole =or attac"in/ t"e main base to t"e panel in

t"e control panel)

2 Power module connector =or installation o' Power Supply module)

3 CPU module connector =or installation o' CPU module 2 slots1)

: Module built-in connector =or installation o' communication modules)

( = terminal 7"e /round terminal connected to t"e s"ielded pattern

o' PC$ board)


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Parts # =unctions; 9@pansion $ase

6 $ase attac"ed /uide "ole =or attac"in/ t"e main base to t"e panel in t"e

control panel)

2 Power module connector =or installation o' power supply module)

3 9@tension dri&e module connector =or installation o' e@tension dri&e module)

: Module built-in connector =or installation o' *+% special and ot"ercommunication modules)

( = terminal 7"e /round terminal connected to t"e s"ielded pattern o' PC$board)


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Parts # =unctions; Power Module

6 Power L9D; DC(< power indication L9D)

2 ,C; ,ot used)

3 ndicates U, state o' system)

U, terminal +== w"en CPU S7+P error occurs)

+== w"en CPU mode is c"an/ed to S7+P mode)

: = terminal; round terminal 'or electric s"oc! pre&ention)

( L terminal round terminal o' power lter)

8 Power input terminal

2ML-AC62% 2ML-AC63 ; AC660

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