Chapter 4: 4.2 A and B

4.2) Let's extend the SRC instruction set by adding the instruction "swap ra, rb". Let's say it uses op-code 7. Its function is exactly what you expect.a) give me the abstract RTN. It should start with "swap (:= op=7)"b)Now, look at the data path, and write the concrete RTN. I want to see steps with the T#'s marked, but you can show the abbreviated fetch portion.HINT: The ALU can hold a value straight off the bus! Just as it's legal to clock a value on the bus into A, the bus value can also be stored directly into C.You can do this! Look at the Concrete RTN for SRC's Add (slide 18) to see how to move data in-to/out-of registers.Answer:a) swap(:=op=7) (R[ra]R[rb] : R[rb]R[ra]):

b) Concrete RTN:STEPRTN

T0 MAPC: CPC+4;

T1 MDM[MA] : PCC;

T2 IRMD;

T3 MDR[ra];

T4 CR[rb];

T5R[ra]C;

T6R[rb]MD;

Note: This homework only produced two results: Three people got it right. Everyone else made exactly the same mistake: instead of dumping one of the registers to MD, they put it in A. The problem, then, becomes getting the value out of A. Register A cannot write a value onto the bus; it would have to go through C. This would mean having to put a known zero value on the bus, and setting the accumulator to add (so that C = A + 0 C = A) to get As data into C. Only then could we bring that value to the other register. Looking at any of the block diagrams for the data path should have revealed this limitation, and we discussed this when we mentioned the limits of the 1-Bus architecture. These limitations came up two or three times. This error was worth 1.5 points.