ECE/Comp Sci 352 Digital System Fundamentals

Homework 3 Solutions - Spring 2001Problem solutions © 2000 Prentice Hall

1. (3-35)*

2. (3-38) *

3. (3-39).

4. (3-41)*

5. (3-42).

C1 T3 T2+ T1C0 T2+ A0B0C0 A0 B0++ A0 B0+( )C0 A0B0+ A0B0 C0+( ) A0 B0+( )= = = = =

C1 A0B0 A0C0 B0C0+ +=

S0 C0 T4⊕ C0 T1T2⊕ C0 A0B0 A0 B0+( )⊕ C0 A0 B0+( ) A0 B0+( )⊕ C0 A0B0 A0B0+⊕= = = = =

S0 A0 B0 C0⊕ ⊕=

1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 00 1 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 10 1 1 0 1 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

11011 10110 000100 1011100

+ 10000 + 10101 + 011000 + 0100100

01011 01011 (–) 011100 0000000

+43 = 0101011

-17 = 1101111

-43 = 1010101

+17 = 0010001

43 0101011

+(–17) + 1101111

10011010

= 26 = 0011010

–43 1010101

+ 17 + 0010001

= –26 = 1100110

101111 -17 001011 11 110001 -15 101010 -22

+ 111011 -5 + 100010 -30 + 110010 -14 + 001001 9

101010 -22 101101 -19 100011 -29 110011 -13

a) b) c) d)

1

ECE 352 Homework #3 Solutions

Spring 2001

Problem 7: (a) Pi = Ai ⊕ Bi , i = n+3, n+2, n+1, n. (b) Gi = Ai • Bi , i = n+3, n+2, n+1, n. (c) Ci = Gi-1 + Pi-1 • Ci-1, i = n+4, n+3, n+2, n+1. So, Cn+1 = Gn + Pn • Cn Cn+2 = Gn+1 + Pn+1 • Cn+1 = Gn+1 + Pn+1 • Gn + Pn+1 • Pn • Cn Cn+3 = Gn+2 + Pn+2 • Cn+2 = Gn+2 + Pn+2 • Gn+1 + Pn+2 • Pn+1 • Gn + Pn+2 •Pn+1 •Pn • Cn Cn+4 = Gn+3 + Pn+3 • Cn+3 = Gn+3 + Pn+3 • Gn+2 + Pn+3 • Pn+2 • Gn+1 +

+ Pn+3 • Pn+2 • Pn+1 • Gn + Pn+3 • Pn+2 • Pn+1 • Pn • Cn

Problem 8: An+3,n = 1110

Bn+3,n = 0011 Using the equations above: Pn+3,n = 1101 Gn+3,n = 0010 Cn+4,n = 11100 Sn+3,n = 0001 Problem 9: There are 2 separate blocks of the same CLA module that are connected to each other through the signal, C4. From Problem 7, the following equation is derived: C4 = G3 + P3 • G2 + P3 • P2 • G1 + P3 •P2 •P1 • G0 + P3 •P2 •P1 • G0

Since Pi functions take longer (3 delays) than Gi functions (2 delays), the first level computation for C4 will take 3 delays, waiting for the Pi values. Then the Ci function also takes 2 delays. So it takes 3 + 2 = 5 gate delays in total to compute C4. Now, the equation for S7 = A7 ⊕ B7 ⊕ C6 . Since A7 and B7 terms are readily available, C6 has to be analyzed first. But, C6 = G5 + P5 • G4 + P5 • P4 • C4

In the C6 equation, the slowest term to compute is C4 with 5 gate delays from above. Since it also takes 2 gate delays (Ci function) to compute C6, in total 5 + 2 = 7 gate delays necessary for the C6 computation. Going back to the S7 equation, we also need 3 gate delays for Si function.

Hence, it takes 7 + 3 = 10 gate delays in total to compute S7. Problem 10: (3-47) The solution to this was inadvertently omitted from the text solutions. If has now been added there. Here is an alternative solution that uses only two-level logic. It has not been verified. Using CAFE, the following equation is obtained where the inputs are: A = {A,B,C,D} and B = {E,F,G,H} and the output is X X = -D*E*F*G*H + -C*E*F*G + -C*-D*E*F*H + -B*E*F + -B*-D*E*G*H + -B*-C*E*G + -B*-C*-D*E*H + -A*E + -A*-D*F*G + -A*-C*F*G + -A*-C*-D*F*H + -A*-B*F + -A*-B*-D*G*H + -A*-B*-C*G + -A*-B*-C*-D*H Problem 15: Extra logic is added to modify the circuit of BCD adder to handle subtraction as well using 9’s complementer. When Add/Subtract = 0, the circuit functions as BCD adder. It is set to 1 for subtraction. See the block diagram on next page

B Inputs

9’s COMPLEMENTER

MUX 0 1 Add/Subtract

A Inputs

Augend

Carry in

Addend

Output Carry BCD Result

BCD ADDER

Problem Solutions – Homework 3

6. (3-45)*

10. (3-47) Not that the problem should read “whether B is > A.”

The solution uses a series of cells and a carry much like the ripple carry in a binary adder.

11. (3-49)*

12. (3-50)

13. (3-51)

S A B C4 S3 S2 S1 S0a) 0 0111 0110 0 1 1 0 1b) 0 0100 0101 0 1 0 0 1c) 1 1100 1010 1 0 0 1 0d) 1 0101 1010 0 1 0 1 1e) 1 0000 0010 0 1 1 1 0

ABCin

Cout

A3B3 A2

B2 A1B1 A0

B0

X

Logic 0

A

B

Cin

Cout

The truth table for the cell:

Ci Ai Bi Ci+1

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1

78430258 98989899 09580089 99999999

416790 995433 900000 000000

a) 5678 b) 1995 c) 30 d) 2048 +7655 +7812 +880 +9279 3333 (–)193 (–) 90 1327

2

Problem Solutions – Homework 3

14. (3-52)*

15. (3-53)

BCD

Gates: 8

Literals: 9

A B C D E F G H0 0 0 0 0 1 0 0 11 0 0 0 1 1 0 0 02 0 0 1 0 0 1 1 13 0 0 1 1 0 1 1 04 0 1 0 0 0 1 0 15 0 1 0 1 0 1 0 06 0 1 1 0 0 0 1 17 0 1 1 1 0 0 1 08 1 0 0 0 0 0 0 19 1 0 0 1 0 0 0 0

H D=

G C=

F BC BC+=

E ABC=

EXCESS-3

Gates: 4

Literals: 4

A B C D E F G H0 0 0 1 1 1 1 0 01 0 1 0 0 1 0 1 12 0 1 0 1 1 0 1 03 0 1 1 0 1 0 0 14 0 1 1 1 1 0 0 05 1 0 0 0 0 1 1 16 1 0 0 1 0 1 1 07 1 0 1 0 0 1 0 18 1 0 1 1 0 1 0 09 1 1 0 0 0 0 1 1

H D=

G C=

F B=

E A=

9’s Complementer(Problem 3-52(a))

Quad 2-to-1 MUX

Select = 1 Select = 0

BCD Adder (Figure 3-35)

S3 S2 S1 S0

A3 A2 A1 A0

Cin

Select

S = 0, AddS = 1, Subtract

B3 B2 B1 B0

If the result is negative, it is given as a 10’s complement number.

3

16. +(a) (8 points) For each of the circuits below, indicate whether the output of the circuit together with its input variables will have even or odd parity.

(b) (8 points) Fill in the truth table for the given circuit:

A B C T1 T2 T3 T4 F1 F2

0 0 0 1 1 0 1 0 0

0 0 1 1 1 0 0 0 1

0 1 0 1 1 0 1 0 0

0 1 1 0 0 0 0 0 0

1 0 0 1 1 1 0 0 1

1 0 1 1 1 1 0 1 1

1 1 0 1 1 1 0 0 1

1 1 1 0 1 0 0 0 1

X

YZ

W

P1

X

YZ

W

P2

XYZ

WV

X

YZ

W

P3

P4

P1: (Circle one) Even Odd P2: (Circle one) Even Odd

P3: (Circle one) Even Odd P4: (Circle one) Even Odd

BA

F1C

F2

T1 T2

T3

T4

1

17. +a) (8 points) Implement the following functions using the decoder with inverted outputs and NAND gates and inverter shown below. No other logic may be used, only wires.

F = A B C + A B CG = A B + A C = ABC + ABC + ABC + ABC

For the given variable order on diagram below, minterms of F are 6,5 andof G are 3, 7, and 5. The solution with 6 and 3 interchanged was accepted too.

b) (8 points) A special encoder is to implement the following partial truth table. For all other input combinations, the encoded outputs C3, C2, C1, C0 are don’t cares. Give simplified expressions for C3, C2, C1, and C0.

I1 I2 I3 I4 C3 C2 C1 C0

1 0 0 0 0 0 0 1

0 1 0 0 0 0 1 1

0 0 1 0 1 0 0 0

0 0 0 1 1 1 1 1

20

21

22

3-to-8

Decoder

01

234

567

ABC F

G

C3 = I3 + I4___________________

C2 = I4_______________________

C1 = I2 + I4___________________

C0 = I1 + I2 + I4___ ____________

2

18. +(a) (8 points) An 8-bit carry lookahead adder is given below.

(b) (6 points) A number has the 7-bit binary value 0101100. In the table below, give the 8-bit representation for positive and negative numbers using the representation specified.

+ A in Sign-Magnitude 0 0 1 0 1 1 0 0

– A in Sign-Magnitude 1 0 1 0 1 1 0 0

+ A in 1’s Complement 0 0 1 0 1 1 0 0

– A in 1’s Complement 1 1 0 1 0 0 1 1

+A in 2’s Complement 0 0 1 0 1 1 0 0

– A in 2’s Complement 1 1 0 1 0 1 0 0

C0 = 0

Si

Pi

Ci

Gi

Location of Values:

CLA CLA

PFA PFA PFA PFA PFA PFA PFA PFA

0 1 1 1 10 0 0 1 0 0 1 1 0 1 1

0 1 0 0 0 0 0 0 01 1 1 1 1

1 0 0 0 0 0 0 0

1

1 1 1 1 1 10 0

1

3

20. + (THERE IS NO PROBLEM 19) (a) (10 points) A multiplexer and an inverter are shown below with the select input already defined. Implement the function F using the inverter and the multiplexer.

F(A, B, C, D) = B C + B D + A B C

b) (10 points) In a Xilinx field programmable gate array each cell consists of a structure that appears as inter-connected multiplexers. Programming is achieved by placing 0’s and 1’s stored in a memory on the data inputs to some of the multiplexers. A scaled-down version of a cell is shown below. Add the “select” input variables and the programming values (0’s and 1’s) on the data inputs on the four input multiplexers needed to implement the function. No other logic may be used! [Hint: expand the expression into the form:G = A B G0(C, D, E, F) + A B G1(C, D, E, F) + A B G2(C, D, E, F) + A B G3(C, D, E, F).]

G(A, B, C, D, E, F) = A B C D + A B C D + B E F + B E F+ A B C + A B E

A C D B F

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 0

0 1 1 0 1

0 1 1 1 1

1 0 0 0 0

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 0

1 1 1 0 1

1 1 1 1 1

B

S0

S1S2

01

234

567

8 ×××× 1 MUX

Y

ACD

B

0

1

1

BB

B

BB

4

= AB (CD + CD) + AB(EF + EF) + AB(EF + EF) + A B(C + E)

S0

S1

01

23

4 ×××× 1 MUX

Y

S0

S1

0123

4 ×××× 1 MUX

Y

S0

S1

01

23

4 ×××× 1 MUX

Y

S0

S1

0123

4 ×××× 1 MUX

Y

S0

S1

0123

4 ×××× 1 MUX

Y

ABE

C0111

FE0 110

DC0110

FE0 110

5

21. a) (6 points) Perform the following computations on unsigned numbers. Clearly show your work for each computation given such as complement operations performed, carries or borrows out of the most significant bit (or most significant magnitude bit), etc. Don’t just give the final answer. Indicate in each case whether or not there is an overflow. If the result is negative, give the final answer as a sign (–) and a magnitude.

111010011+11101110 11000001 Overflow? Yes No

111011111–11101110 11110001 => (–)00001111 Overflow? Yes No

11100001–11011110 00000011 Overflow? Yes No

b) (10 points) Perform the following computations on signed numbers. The operands are given in the representation specified. Clearly show your work for each computation given such as complement opera-tions performed, carries or borrows out of the most significant bit (or most significant magnitude bit), etc. Don’t just give the final answer. Note that for a complement representation, the answer are to be left in the representation. Indicate in each case whether or not there is an overflow.

Sign-Magnitude 1 10101011–11001011 111000000 => 00100000 Overflow? Yes No

2’s Complement

111010011+11101110 11000001 Overflow? Yes No

1’s Complement

110001001+11001001 01010010 Overflow? Yes No

+1 => 010100112’s Complement 1 10101010 => 10101010–10000000 =>+10000000 00101010 Overflow? Yes No

Sign-Magnitude

10001001+00001001 10000000 Overflow? Yes No

6

22. An engineer in an advanced extraterrestrial alien society is to design a digit adder for a code similar to our BCD. However, these aliens have six fingers on each hand instead of five. As a consequence, their digit arithmetic is base 12 with digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A and B. Using the two 4-bit binary adders given below, you are to design the logic in the outlined boxes to form a base 12 adder by answering each of the following questions:

a) (4 points) What value in binary must be added to the output from Z of the top adder to per-form the correction for the base 12 addition?

SPECIAL NOTE: If you can’t answer the above, contact an exam proctor and they will give you the value and deduct 4 points so that you can work the rest of the problem!

b) (8 points) Add minimized two-level logic for Cout, the signal that indicates that a correction is to be made and a carry is to occur into the next base 12 digit, in the upper box in the dia-gram.

c) (4 points) Add the wires in the lower box in the diagram that apply the right constant value from part a) above or a 4-bit zero to the left port of the second adder.

C = K + Z3 Z2

Add value 0100_________

•

•

•

••

••

Outputcarry

C

0

Addend Augend

Inputcarry

4-bit binary adder

Z3 Z2 Z1 Z0

K

4-bit binary adder

S3 S2 S1 S0

BCD sum

K is the carry outfrom the most significant bit

binary adder.of the

0

7