Organic Electronics 12 (2011) 1841–1845

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Organic Electronics

journal homepage: www.elsevier .com/locate /orgel

Letter

Holography and plasma oxidation for uniform nanoscale twodimensional channel formation of vertical organic field-effecttransistors with suppressed gate leakage current

Donghyun Kim a,b, Jaewook Jeong a,b,1, Hwarim Im a,b, Sungmo Ahn b,c, Heonsu Jeon b,c,Changhee Lee a,b, Yongtaek Hong a,b,⇑a Department of Electrical Engineering and Computer Science, Seoul National University, 599 Gwanak-ro, Gwanak-gu, Seoul 151-744, Republic of Koreab Inter-University Semiconductor Research Center, Seoul National University, 599 Gwanak-ro, Gwanak-gu, Seoul 151-744, Republic of Koreac Department of Physics and Astronomy, Seoul National University, 599 Gwanak-ro, Gwanak-gu, Seoul 151-747, Republic of Korea

a r t i c l e i n f o

Article history:Received 16 January 2011Received in revised form 1 July 2011Accepted 6 July 2011Available online 7 August 2011

Keywords:Vertical organic field effect transistorsOrganic thin film transistorsLaser holography

1566-1199/$ - see front matter � 2011 Elsevier B.Vdoi:10.1016/j.orgel.2011.07.019

⇑ Corresponding author at: Department of ElectrComputer Science, Seoul National University, 599 Ggu, Seoul 151-744, Republic of Korea.

E-mail address: yongtaek@snu.ac.kr (Y. Hong).1 Present address: Daegu Gyeongbuk Institute of Sc

(DGIST), Daegu, Republic of Korea.

a b s t r a c t

Vertical organic field-effect transistors (VOFETs) with nanoscale channel openings havebeen fabricated using pentacene as an active layer material. To achieve uniform nanoscaletwo-dimensional channel openings, a laser holography lithography has been introduced.Uniformly distributed and well-aligned holes with 250 nm diameter were successfullyobtained with the laser holography lithography. VOFET devices with these channel open-ings have shown high on/off ratio of about 103 without any further treatment. Gate leakagecurrent was also decreased with an additional insulating layer generated on the gate elec-trode sidewall via plasma oxidation.

� 2011 Elsevier B.V. All rights reserved.

1. Introduction structures. With a vertical configuration, channel length

Organic thin-film transistors (OTFTs) have been investi-gated by many researchers due to low process temperatureand thus, easy application to flexible electronics. On a de-vice fabrication aspect, making a short channel lengthhas been pointed out as one of the key solutions to over-come weak points of the OTFTs such as low carrier mobilityand low current density. To realize OTFTs with short chan-nel length, conventional photolithography techniques or e-beam lithography techniques have been employed [1–5].However, the process cost for these lithography techniquesis too high to be applied in large area and low cost applica-tions. One alternative approach to obtain sub-micron chan-nel length is using a vertical configuration for transistor

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ical Engineering andwanak-ro, Gwanak-

ience and Technology

can be defined as the thickness of active layers, so onecan make short channel length just by controlling thethickness of active layers precisely during a deposition pro-cess. Many researchers have introduced various types ofvertical organic field effect transistors (VOFETs) so far [6–10]. In many cases, however, VOFET devices suffer rela-tively large gate leakage because most VOFETs rely onSchottky barrier between gate electrodes and semiconduc-tor materials to modulate current flow through the semi-conductor layer, and to suppress gate leakage current.Although an additional insulation layer to gate electrodesurface by forming thin aluminum oxide layer has beenintroduced to overcome the large gate leakage under largegate voltage applied [11], the process needs several stepsduring gate electrode fabrication process which may influ-ence the quality of organic semiconductor and the sidewallof gate electrode cannot be oxidized properly when rela-tively thick gate electrode is needed.

In addition to gate leakage, semiconductor leakage be-tween source and drain has been pointed out as one ofthe main leakage paths which results in reduced on/off

1842 D. Kim et al. / Organic Electronics 12 (2011) 1841–1845

ratio, and it is mainly originated from improper currentsuppression and imperfect carrier depletion in off state[12]. To reduce off-state current effectively and to enhanceon/off ratio, it is essential to make current channel open-ings smaller and more uniform. Therefore, making gatepattern with shadow mask and evaporation technique isnot feasible because obtaining sub-micron feature throughvacuum evaporation method is extremely difficult andhighly ordered patterns like porous shape cannot be ac-quired with shadow mask. Although conventional e-beamlithography has been used to make channel opening pat-terns with sub-micron feature size [13], it is an intrinsi-cally expensive process. Polystyrene sphere basedshadow mask method has also been used to obtain sub-mi-cron porous channel opening patterns, namely colloidallithography technique [14], but it is very difficult to obtainuniform channel opening patterns through this method.Therefore, in this study, we report a laser holographylithography method to form highly uniform nanoscaletwo-dimensional channel openings for VOFET devices.The laser holography has been recently used to make uni-form photonic crystal structure in various optical applica-tions like light-emitting diodes (LEDs) and photoniccrystal slab waveguides [15,16]. It is a simple and masklesslithography technique which has many advantages in mak-ing well-aligned nanoscale reciprocal structures, but it hasnot been much used to make electrical device applicationsyet.

Fig. 1. (a)–(d) Fabrication processes and (e) a schematic configuration ofvertical organic field effect transistors. (a) Photoresist coating afteraluminum, chrome hardmask and two silicon nitride layers deposition.(b) Etching each layers after holography lithography process. (c) Plasmaoxidation of gate electrode surfaces after removing photoresist. (d)Pentacene active layer and gold source electrode deposition after etchingsilicon nitride layer and removing hardmask.

2. Experimental

The simplified process flow and schematic configura-tion of the fabricated VOFETs are illustrated in Fig. 1.Fig. 2 shows scanning electron microscope (SEM) imagesof top and cross-section views of the fabricated devicesat several process steps. On a heavily doped silicon sub-strate which would act as a drain electrode, the first siliconnitride (SiNx) layer, aluminum (Al) gate electrode layer, thesecond SiNx layer, and chrome (Cr) hardmask layer havebeen sequentially deposited. Each SiNx layer was formedby a plasma enhanced chemical vapor deposition (PECVD)process and its thickness was about 50 nm. Each metallayer (Al, Cr) was deposited with an e-gun evaporator.The thicknesses of Al gate and Cr hardmask layers wereabout 100 and 40 nm, respectively. After photoresist wasspun-coated (Fig. 1a), the sample was exposed to the peri-odical line-shaped interference patterns generated from alaser holography system [15,16]. Negative type photoresistwas used to make two dimensional (2-D) nanoscale pat-terns. After exposing the substrate to the laser holographyline-shaped image two times in orthogonal directions anddeveloping it in AZ�300 MIF developer, 2-D interferencepatterns (or holes) were formed in the unexposed area(Fig. 2a). The pitch between each channel opening couldbe controlled in 200 nm–1 lm range by adjusting the angleof stage where the sample is located. In this work, we fixedthe pitch in 500 nm to obtain small and uniform porouspatterns having holes with about 250 nm diameters. Weexpect that the gate controllability would be furtherenhanced by making channel openings smaller, because

the portion of the effective depletion region to the wholechannel area, which is controlled by applied gate voltage,would be increased [14]. Since we need to perform addi-tional plasma treatment process, however, the channelopenings were maintained to be greater than 250 nmdiameter considering overall device thickness, which isabout 200 nm in this study.

By using these patterns, we etched the device structurethrough a reactive ion etching (RIE) process, producing thesame holographic patterns for the vertical stack of Cr etchhardmask, the second SiNx and Al gate layers (Fig. 1b). Toreduce gate leakage current we have oxidized the Al gatesidewall surfaces. To effectively oxidize the sidewall, thesample was tilted in the plasma chamber during the plas-ma oxidation process. The oxygen plasma treatment (nowO2 plasma for 10 min) was performed four times for thesame sample tilted in four different directions to equallyoxidize the surface of the Al gate electrode sidewall(Fig. 1c). After removing the first SiNx layer (Fig. 2b) withRIE process, pentacene (Tokyo Chemical Industry, P0030,240 nm, @ 3 Å/s) and gold (Au, 100 nm, @ 2 Å/s) sourceelectrode layers have been sequentially deposited using athermal evaporation method (Figs. 1d and 2c and d). The

Fig. 2. SEM images of (a) top view of photoresist layer with two dimensional well-aligned porous patterns, (b) top-view of the vertical stack after oxygenplasma and etching of the first SiNx layer, (c) top and (d), (e) cross-section views after depositing pentacene and gold electrode layers.

D. Kim et al. / Organic Electronics 12 (2011) 1841–1845 1843

fabricated VOFETs were measured with a semiconductorparameter analyzer (Agilent 4155C) in air under darkconditions.

3. Results and discussion

Fig. 3a and b show the transfer characteristics and out-put characteristics of the fabricated VOFETs, respectively.Size of the measured device, i.e. size of Au source electrodewas about 2 � 2 mm2 for this result. Because VOFETs haveshort channel length, they can be operated even in lowdrain voltage region below 1 V. We investigated the trans-fer characteristics as we swept the gate voltage (VG) from 2to �2 V with �0.02 V step and increased the drain voltage(VD) from 0 to�1 V with�0.2 V step. Current flow betweensource and drain electrodes (ID) was effectively suppressedwhen positive VG was applied. When positive voltage is ap-plied to the gate electrode, energy barrier near the gateelectrode is enhanced and the effective depletion regionis expanded, which inhibits the current flow betweensource and drain electrode. On the other hands, when neg-ative voltage is applied to the gate electrode, the current isincreased due to the lowered energy barrier near the gateelectrode and reduced effective depletion region. On/off ra-tio was obtained up to about 103 when �0.1 V was appliedto VD. It is noted that no additional ultra-thin organic semi-conductor layers were inserted before pentacene deposi-tion, which is known to improve on/off ratio [17] of theVOFETs. Therefore, on/off ratio can be further improved iforganic multilayer approach is used. We also obtained out-

put characteristics of the fabricated VOFETs for the samevoltage range as in the transfer curves. Drain voltage wasswept from 0 to �1 V with �0.01 V step, and the gate volt-age was changed from 2 to �2 V with �0.4 V step. Likeother VOFETs, our devices did not show saturation behav-ior when large VD was applied [6,11]. Gate leakage currentwas maintained under hundreds of nano-amperes for rela-tively large VG values. The mobility of pentacene in VOFETswas estimated by the space charge limited current (SCLC)model [8] because the conventional mobility extractionmethod which is widely used in OTFTs cannot be appliedin VOFETs. Our current density to the applied drain voltage(J–VD) was fitted quite well to the SCLC model, and themobility extracted with SCLC model was estimated as1.2 � 10�4 cm2/Vs, which is a quite low value comparedwith conventional OTFTs, but common in vertical typetransistor devices. Although VOFETs have shown lowmobilities compared with lateral-type OTFTs, the shortchannel length of VOFETs which is 240 nm in current de-vices, and a number of channel openings covering eachVOFET devices enable a large current driving capabilityeven in low voltage regimes.

Fig. 4 shows the effect of plasma oxidation on Al gatesidewall surfaces of VOFETs, which in this case have chan-nel openings with 1 lm diameter. It is indicated that theoxidized gate surfaces can suppress the gate leakagecurrent levels originated from high gate bias exceedingSchottky barrier and improper Schottky junction formationbetween gate electrode and active layer. Especially, theeffect of plasma oxidation is more prominent in an off-state, when positive voltages are applied to gate electrodes,

Fig. 3. (a) Transfer characteristics and (b) output characteristics ofVOFETs with channel openings of about 250 nm diameter.

Fig. 4. Suppressed gate leakage current levels after plasma oxidation ofgate electrode surfaces.

1844 D. Kim et al. / Organic Electronics 12 (2011) 1841–1845

and this contributes to on/off ratio enhancement due tolower leakage current levels. Without these additionalinsulation structures, it is typically challenging to obtainproper transistor characteristics because maintainingSchottky contact for various semiconductor materials ischallenging. An insertion of additional insulating structure

by oxidizing gate electrode surface may allow us to usemany semiconductor materials in the active layer.Although we can produce 2-D patterns only over3 � 3 cm2 area due to equipment limitation, it is noted thatthe laser holography lithography can produce reciprocalpatterns over large area (>50 � 50 cm2) [18]. Therefore, ifthis plasma oxidation process is combined together, ourmethod can produce uniform 2-D nanoscale patterns forhigh performance VOFET arrays over large area substrate.Furthermore, adjusting exposure times and direction en-ables making various reciprocal lateral patterns such aslines and squarely or hexagonally aligned hole arrays.Since these patterns are well-aligned and have uniformshape generally, devices with minimal performance varia-tion can be easily made.

4. Conclusion

In summary, we have used a laser holography lithogra-phy technique to make 2-D channel opening patterns infabricating VOFET structures. Holographically generatedsmall channel opening patterns were well-aligned andquite uniform in size and shape. The gate electrode side-wall was oxidized with oxygen plasma to further reducegate leakage. The pentacene VOFET with the channel open-ing size of about 250 nm in diameter showed on/off ratio ofabout 103 without any further treatment. We believe thatby introducing better gate electrode sidewall oxidationprocess and optimizing the channel opening size, the de-vice performance can be further improved.

Acknowledgment

This work was supported by the Industrial StrategicTechnology Development Program (KI002104, Develop-ment of Fundamental Technologies for Flexible Com-bined-Function Organic Electronic Device) funded by theMinistry of Knowledge Economy (MKE, Korea).

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