SESE--273: Processor Design 273: Processor Design

History of Computers History of Computers

Virendra SinghVirendra SinghVirendra SinghVirendra SinghIndian Institute of ScienceIndian Institute of Science

BangaloreBangaloreBangaloreBangalorevirendra@computer.orgvirendra@computer.org

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Courtesy: Prof. Vishwani Agrawal

Historic EventsHistoric EventsHistoric EventsHistoric Events1623, 1642: Wilhelm Strickland/1623, 1642: Wilhelm Strickland/BlaiseBlaise Pascal built a Pascal built a mechanical counter with carrymechanical counter with carrymechanical counter with carry.mechanical counter with carry.18231823--34: Charles Babbage designed difference engine. 34: Charles Babbage designed difference engine. http://www.youtube.com/watch?v=0anIyVGeWOI&feature=relatedhttp://www.youtube.com/watch?v=0anIyVGeWOI&feature=related19431943 44: John44: John MauchlyMauchly (professor) and J(professor) and J PresperPresper19431943--44: John 44: John MauchlyMauchly (professor) and J. (professor) and J. PresperPresperEckert (graduate student) built ENIAC at U. Eckert (graduate student) built ENIAC at U. Pennsylvania.Pennsylvania.1944: Howard Aiken used 1944: Howard Aiken used “separate data and program “separate data and program memories”memories” in MARK I in MARK I –– IV computers IV computers –– Harvard Harvard ArchitectureArchitecture..19451945--52: John von Neumann proposed a “52: John von Neumann proposed a “stored stored program computerprogram computer” EDVAC (Electronic Discrete Variable ” EDVAC (Electronic Discrete Variable Automatic Computer) Automatic Computer) –– Von Neumann Architecture Von Neumann Architecture ––

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p )p )use the same memory for program and data.use the same memory for program and data.

Most Influential DocumentMost Influential DocumentMost Influential DocumentMost Influential Document

“Preliminary Discussion of the Logical“Preliminary Discussion of the LogicalPreliminary Discussion of the Logical Preliminary Discussion of the Logical Design of an Electronic Computing Design of an Electronic Computing Instrument ” 1946 report by A W BurksInstrument ” 1946 report by A W BurksInstrument, 1946 report by A. W. Burks, Instrument, 1946 report by A. W. Burks, H. H. Holdstine and J. von Neumann. H. H. Holdstine and J. von Neumann. Appears inAppears in Papers of John von NeumannPapers of John von NeumannAppears in Appears in Papers of John von NeumannPapers of John von Neumann, , W. Aspray and A. Burks (editors), MIT W. Aspray and A. Burks (editors), MIT Press Cambridge Mass 1987 pp 97Press Cambridge Mass 1987 pp 97--Press, Cambridge, Mass., 1987, pp. 97Press, Cambridge, Mass., 1987, pp. 97146.146.

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History ContinuesHistory Continuesyy

19461946--52: Von Neumann built the IAS computer52: Von Neumann built the IAS computer19461946 52: Von Neumann built the IAS computer 52: Von Neumann built the IAS computer at the Institute of Advanced Studies, Princeton at the Institute of Advanced Studies, Princeton ––A prototype for most future computersA prototype for most future computers..19471947--50: Eckert50: Eckert--Mauchly Computer Corp. built Mauchly Computer Corp. built UNIVAC I (Universal Automatic Computer), used UNIVAC I (Universal Automatic Computer), used in the 1950 census.in the 1950 census.1949: Maurice Wilkes built EDSAC (Electronic 1949: Maurice Wilkes built EDSAC (Electronic D l S A i C l l ) h fiD l S A i C l l ) h fiDelay Storage Automatic Calculator), the first Delay Storage Automatic Calculator), the first storedstored--program computer.program computer.

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First GeneralFirst General--Purpose ComputerPurpose ComputerFirst GeneralFirst General Purpose ComputerPurpose ComputerElectronic Numerical Electronic Numerical Integrator and CalculatorIntegrator and CalculatorIntegrator and Calculator Integrator and Calculator (ENIAC) built in World War II (ENIAC) built in World War II was the first general was the first general purpose computerpurpose computerp p pp p p–– Used for computing artillery Used for computing artillery

firing tablesfiring tables–– 80 feet long, 8.5 feet high and 80 feet long, 8.5 feet high and

several feet wideseveral feet wideseveral feet wideseveral feet wide–– Twenty 10 digit registers, each Twenty 10 digit registers, each

2 feet long2 feet long–– Used 18,000 vacuum tubesUsed 18,000 vacuum tubes–– 5,000 additions/second5,000 additions/second–– Weight: 30 tonsWeight: 30 tons–– Power consumption: 140kWPower consumption: 140kW

© 2004 Morgan Kaufman Publishers

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The Atanasoff StoryThe Atanasoff StoryThe Atanasoff StoryThe Atanasoff StoryJohn Vincent Atanasoff, a professor of John Vincent Atanasoff, a professor of physics at Iowa State College (now physics at Iowa State College (now University), and his technical assistant, University), and his technical assistant, Clifford Berry, built a working electronic Clifford Berry, built a working electronic computer in 1942.computer in 1942.The First Electronic Computer, the The First Electronic Computer, the Atanasoff StoryAtanasoff Story, by Alice R. Burks and , by Alice R. Burks and yy yyArthur W. Burks, Ann Arbor, Michigan: Arthur W. Burks, Ann Arbor, Michigan: The University of Michigan Press, 1991.The University of Michigan Press, 1991.

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y gy g

FirstFirst--Generation ComputersGeneration ComputersFirstFirst Generation ComputersGeneration Computers

Late 1940s and 1950sLate 1940s and 1950sLate 1940s and 1950sLate 1940s and 1950sStoredStored--program computersprogram computersP d i bl lP d i bl lProgrammed in assembly languageProgrammed in assembly languageUsed magnetic devices and earlier forms Used magnetic devices and earlier forms of memoriesof memoriesExamples: IAS, ENIAC, EDVAC, UNIVAC, Examples: IAS, ENIAC, EDVAC, UNIVAC, p , , , ,p , , , ,Mark I, IBM 701Mark I, IBM 701

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The Organization of IAS ComputerThe Organization of IAS ComputerThe Organization of IAS ComputerThe Organization of IAS ComputerAccumulator (AC) Multiplier/Quotient (MQ) Input/

H

Arithmetic Logic Circuits

OutputEquipment

ATA

PATH

Memory Buffer Register (MBR) DA

Instr. Buffer (IBR) Program Counter (PC)

Instruction Register (IR) Memory Address Reg (MAR)

MainMemory

(M)12Instruction Register (IR) Memory Address Reg. (MAR) 212 x 40 bitwords

ControlCi it

ControlSi CONTROL UNIT

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Circuit Signals CONTROL UNIT

IAS Computer Machine LanguageIAS Computer Machine LanguageIAS Computer Machine LanguageIAS Computer Machine Language

40 bit d t hi i t ti d40-bit word, two machine instructions per word.

Left instruction Right instructiong

bit 0 7 8 19 20 27 28 39

8-bit opcode 12-bit memory address8 bit opcode 12 bit memory address(operand)

Ref: J. P. Hayes, Computer Architecture and Organization, New York:McGraw Hill 1978

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McGraw-Hill, 1978.

IAS Data Transfer Instructions (7)IAS Data Transfer Instructions (7)IAS Data Transfer Instructions (7)IAS Data Transfer Instructions (7)InstructionInstruction OpcodeOpcode DescriptionDescriptionInstructionInstruction OpcodeOpcode DescriptionDescriptionLOAD MQ 00001010 AC ← MQLOAD MQ, M(X) 00001001 MQ ← M(X)LOAD MQ, M(X) 00001001 MQ M(X)STOR M(X) 00100001 M(X) ← ACLOAD M(X) 00000001 AC ← M(X)( ) ( )LOAD – M(X) 00000010 AC ← – M(X)LOAD |M(X)| 00000011 AC ← |M(X)|| ( )| | ( )|LOAD – |M(X)| 00000100 AC ← – |M(X)||

Ref. W. Stallings, Computer Organization & Architecture, Sixth Edition,

1111

Prentice-Hall, 2003, page 23.

IAS Unconditional Branch IAS Unconditional Branch (2)(2)Instructions (2)Instructions (2)

InstructionInstruction OpcodeOpcode DescriptionDescriptionJUMP M(X,0:19) 00001101 next instruction ( )

M(X,0:19)JUMP M(X,20:39) 00001110 next instruction

M(X,20:39)

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IAS Conditional BranchIAS Conditional BranchInstructions (2)Instructions (2)

InstructionInstruction OpcodeOpcode DescriptionDescriptionJUMP +M(X,0:19) 00001111 IF AC ≥ 0,

then nextthen next instruction M(X,0:19)

JUMP +M(X,20:39) 00010000 IF AC ≥ 0, then next instructionM(X,20:39)

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IAS Arithmetic Instructions (8)IAS Arithmetic Instructions (8)IAS Arithmetic Instructions (8)IAS Arithmetic Instructions (8)InstructionInstruction OpcodeOpcode DescriptionDescriptionADD M(X) 00000101 AC ← AC+M(X)ADD |M(X)| 00000111 AC ← AC+|M(X)|SUB M(X) 00000110 AC ← AC─M(X)SUB |M(X)| 00001000 AC ← AC ─ |M(X)|MUL M(X) 00001011 AC, MQ ← MQ×M(X)DIV M(X) 00001100 MQ, AC ← MQ/M(X)( ) ( )LSH 00010100 AC ← AC x 2RSH 00010101 AC ← AC / 2

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IAS Address Modify Instructions (2)IAS Address Modify Instructions (2)IAS Address Modify Instructions (2)IAS Address Modify Instructions (2)

InstructionInstruction OpcodeOpcode DescriptionDescriptionSTOR M(X,8:19) 00010010 M(X,8:19) ←

AC(28 39)AC(28:39)

STOR M(X 28 39) 00010011 M(X 28 39)STOR M(X,28:39) 00010011 M(X,28:39) ← AC(28:39)

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How IAS Computer Adds Two How IAS Computer Adds Two N bN bNumbersNumbers

Suppose the numbers are stored inSuppose the numbers are stored in memory locations 100 and 101, andThe sum is to be saved in memoryThe sum is to be saved in memory location 102

I t ti O d D i tiInstruction Opcode DescriptionLOAD M(100) 00000001 AC ← M(100)ADD M(101) 00000101 AC AC M(101)ADD M(101) 00000101 AC ← AC+M(101)STOR M(102) 00100001 M(102) ← AC

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IAS Computer Machine CodeIAS Computer Machine CodeIAS Computer Machine CodeIAS Computer Machine Code

00000001 000001100100 00000101 000001100101 Load 100 Add 101

00100001 000001100110 00000000 000000000000Stor 102 Stop

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Save Program in MemorySave Program in MemorySave Program in MemorySave Program in Memory

Address 0

First program wordS d d

Address 0

Second program word

Address

mor

y

Load programWord 100Word 101Word 102

MemLoad program

Counter, PC

Word 102

Address max

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Address max

Executing the ProgramExecuting the ProgramExecuting the ProgramExecuting the ProgramAccumulator (AC) Multiplier/Quotient (MQ) Input/

H

Arithmetic Logic Circuits

OutputEquipment

ATA

PATH

Memory Buffer Register (MBR) DA

Program Counter (PC) MainMemory

(M)12

Instr. Buffer (IBR)

Instruction Register (IR) Memory Address Reg (MAR) 212 x 40 bitwords

ControlCi it

ControlSi CONTROL UNIT

Instruction Register (IR) Memory Address Reg. (MAR)

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Circuit Signals CONTROL UNIT

IAS Instruction CyclesIAS Instruction CyclesStore machine code in contiguous words of memory.Store machine code in contiguous words of memory.Place starting address in program counter (PC)Place starting address in program counter (PC)Place starting address in program counter (PC).Place starting address in program counter (PC).Start program: MAR ← PCStart program: MAR ← PCRead memory: IBR ← MBR ← M(MAR), Read memory: IBR ← MBR ← M(MAR), fetchfetchy ( )y ( )Place left instruction (Load) in IR and operand (address) Place left instruction (Load) in IR and operand (address) 100 in MAR, 100 in MAR, decodedecodeRead memory: AC ← M(100)Read memory: AC ← M(100) executeexecuteRead memory: AC ← M(100), Read memory: AC ← M(100), executeexecutePlace right instruction (Add) in IR and operand (address) Place right instruction (Add) in IR and operand (address) 101 in MAR, 101 in MAR, decodedecodeRead memory and add: AC ← AC + M(101), Read memory and add: AC ← AC + M(101), executeexecutePC ← PC + 1PC ← PC + 1

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IAS Instruction Cycles (Cont )IAS Instruction Cycles (Cont )IAS Instruction Cycles (Cont.)IAS Instruction Cycles (Cont.)MAR ← PCMAR ← PCRead memory: IBR ← MBR ← M(MAR), Read memory: IBR ← MBR ← M(MAR), fetchfetchPlace left instruction (Place left instruction (StorStor) in IR and operand ) in IR and operand (( ) p) p(address) 102 in MAR, (address) 102 in MAR, decodedecodeMBR ← AC, MBR ← AC, executeexecuteWrite memoryWrite memoryPlace right instruction (Stop) in IR and operand Place right instruction (Stop) in IR and operand 000 in MAR000 in MAR decodedecode000 in MAR, 000 in MAR, decodedecodeStop, Stop, executeexecute

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Hardware ContainsHardware ContainsHardware ContainsHardware ContainsData storage devicesData storage devicesData storage devicesData storage devices

MemoryMemoryRegistersRegisters

Decode and execution devicesDecode and execution devicesExecution unit (arithmetic logic unit, ALU)Execution unit (arithmetic logic unit, ALU)( g , )( g , )Data transfer busesData transfer busesControl unitControl unit

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Registers in IASRegisters in IASgg

Register Size(bit ) FunctionRegister (bits) Function

Program counter (PC) 12 Holds mem. address of next instruction

Accumulator (AC) 40 Temporary data storage

Multiplier quotient (MQ) 40 Temporary data storage

Memory buffer (MBR) 40 Memory read / write data

Instruction buffer (IBR) 20 Holds right instr. (bits 20-39)

Instruction register (IR) 8 Holds opcode part of instruction

Memory address (MAR) 12 Holds mem. address part of instruction

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Register TransferRegister TransferRegister TransferRegister Transfer

Transfer data synchronously with clockTransfer data synchronously with clockRegister to registerRegister to register through ALU logicRegisters to register through memory (write)Register to register through memory (read)

D t t f th h i ti bData transfer through communication busSource register writes on busDestination register reads from busDestination register reads from busControl circuit provides read / write signals for bus and memory

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Communication BusCommunication BusCommunication BusCommunication BusA device writing

on busA device neither

writing on nor

outputs inputs

greading from busoutputs inputs

1 010

00

01

Control signalsBus

1

outputs inputs

A d i diControlcircuitpc

ode

ontro

lgn

als

2525

A device readingfrom bus

circuit

Op

Co

sig

Control CircuitControl Circuit –– Finite State MachineFinite State MachineControl Circuit Control Circuit Finite State MachineFinite State MachineStart

Readmemory

Decodeleft

instruction

MAR ← PCPC ← PC+1

Fetch Instruction

y instruction

ExecuteDecode

righti t ti

Executeinstruction

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Von Neumann BottleneckVon Neumann BottleneckVon Neumann BottleneckVon Neumann BottleneckVon Neumann architecture uses the same

f i t ti ( ) dmemory for instructions (program) and data.Th ti t iThe time spent in memory accesses can limit the performance. This phenomenon is referred to as von Neumann bottleneckreferred to as von Neumann bottleneck.To avoid the bottleneck, later architectures restrict most operands to registersrestrict most operands to registers (temporary storage in processor).

Ref : D E Comer Essentials of Computer Architecture Upper Saddle

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Ref.: D. E. Comer, Essentials of Computer Architecture, Upper SaddleRiver, NJ: Pearson Prentice-Hall, 2005, p. 87.

John von Neumann (1903John von Neumann (1903--1957)1957)John von Neumann (1903John von Neumann (1903 1957)1957)

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Second Generation ComputersSecond Generation ComputersSecond Generation ComputersSecond Generation Computers1955 to 1964Transistor replaced vacuum tubesMagnetic core memoriesFloating-point arithmeticHigh-level languages used: ALGOL, g g g ,COBOL and FORTRANSystem software: compilers, subroutine y p ,libraries, batch processingExample: IBM 7094

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p

Third Generation ComputersThird Generation ComputersThird Generation ComputersThird Generation ComputersBeyond 1965Integrated circuit (IC) technologySemiconductor memoriesMemory hierarchy, virtual memories and cachesTime-sharinggParallel processing and pipeliningMicroprogrammingMicroprogrammingExamples: IBM 360 and 370, CYBER, ILLIAC IV, DEC PDP and VAX, Amdahl 470

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,

C Programming Language and C Programming Language and O SO SUNIX Operating SystemUNIX Operating System

N

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1972 Now

Theory of ComputingTheory of Computingy p gy p gAlan Turing (1912-1954) gave a model of computing in 1936 – Turing Machine.Original paper: A. M. Turing, “On Computable Numbers with an Application to the Entscheidungsproblem*,” Proc. Royal Math. Soc., ser. 2, vol. 42, pp. 230-265, 1936.Recent book: David Leavitt, The Man ,Who Knew Too Much: Alan Turing and the Invention of the Computer (Great Discoveries), W. W. Norton & Co., 2005.), ,

* The question of decidability, posed by mathematician Hilbert

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mathematician Hilbert.

Turing MachineTuring MachineTuring MachineTuring MachineProcessor

PP

Read-write head

Infinite memory tape (data)

tiInfinite memory tape (data)

Machine instruction: sh ti oj sk

Present state of processorSymbol on tape

OperationNe t state of processor

3333

Next state of processor

Turing MachineTuring MachineggFour operations:– oj = tj, replace present symbol ti by tj

o R mo e head one position to right– oj = R, move head one position to right– oj = L, move head one position to left– oj = H, halt the computationj

Universal Turing Machine: small instruction set, #symbols × #states < 30; can perform any possible (computable) computation.possible (computable) computation.Computable means that Turing machine halts in finite number of steps.R l t h fi it th fi dReal computers have finite memory – they find certain problems intractable.

Ref: J P Hayes Computer Architecture and Organization New York:

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Ref: J. P. Hayes, Computer Architecture and Organization, New York: McGraw-Hill, 1978.

Incompleteness TheoremIncompleteness TheoremIncompleteness TheoremIncompleteness TheoremIn 1931, the Czech-born mathematician K Göd l (1906 1978) d dKurt Gödel (1906-1978) demonstrated that within any given branch of mathematics, there would always be some propositions that couldn't besome propositions that couldn t be proven either true or false using the rules and axioms.Gödel's Theorem has been used to argue that a computer can never be as smart as a human being because the extent of its knowledge is limited by a fixed set of axioms whereas people canfixed set of axioms, whereas people can discover unexpected truths. See http://www.miskatonic.org/godel.htmland other websites.

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The Barber ParadoxThe Barber ParadoxBy Linda ShaverBy Linda Shaver

(An Example of(An Example of UndecidabilityUndecidability))(An Example of (An Example of UndecidabilityUndecidability))

In a particular town, there’s a particular barbershop with a peculiar sign in the window that reads:

“This barber shaves all and only those men ofthe town who do not shave themselves.”

Question: According to the sign in the window, does the barber shave himself?

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The Now GenerationThe Now GenerationPersonal computersLaptops and PalmtopsNetworking and wirelessSOC and MEMS technologyAnd the future!And the future!

Biological computingMolecular computing N t h lNanotechnologyOptical computingQuantum computing

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