high-speed switched serial fabrics improve system design · high-speed switched serial fabrics...

Pentek, Inc. • One Park Way, Upper Saddle River, NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: [email protected] • http://www.pentek.com

1

High-speed Switched Serial Fabrics Improve System Design

High-speed Switched Serial

Fabrics Improve System DesignFirst Edition

Pentek, Inc.One Park Way, Upper Saddle River, New Jersey 07458

Tel: (201) 818-5900 • Fax: (201) 818-5904

Email: [email protected] • http://www.pentek.com

Copyright © 2008 Pentek Inc.

All rights reserved.

Contents of this publication may not be reproduced in any form without written permission.

Specifications are subject to change without notice.

Pentek, GateFlow, ReadyFow and VIM are registered trademarks of Pentek, Inc.

Switched Serial Fabrics

FPGA Resources

Products

Applications

Linksby

Rodger H. HoskingVice-President & Cofounder of Pentek, Inc.

®


2


Preface

The VMEbus, well into a third decade of widespread development, continues as the dominant bus structure for high-performance embedded systems. In an industry characterized by a steady succession of new device offerings with speed

and density increases every few months, the VMEbus has retained its leadership position not simply because it was basedon a sound electrical and mechanical architecture. Indeed, the major reason for its longevity has been a series of perfor-

mance and feature enhancements promoted and nurtured by a broad base of VMEbus vendors.

In a similar venue, the PMC mezzanine card has become the dominant architecture for mezzanine I/O in VMEbus-based embedded systems. Making its debut in 1994, the PMC was successfully adopted for both commercial and

government electronic systems. During the next decade, important extensions to the PMC standard included ruggedizedand conduction-cooled versions for severe environments and the adoption of the processor PMC specification.

When VXS, a proposal for standardizing gigabit serial switched fabrics shook the embedded community in 2002 aspart of the VMEbus renaissance, XMC, a natural extension of that technology to PMC modules was inevitable.


3


What is a Switched Fabric?Switched Serial Fabric Technology

The traffic in switched fabrics consists of packetsthat contain a packet information header, the payloaddata itself, and then usually a footer at the end forintegrity.

It’s like a package sent into the FedEx system: thebarcode on the label makes sure it gets through thesystem and to where it’s going on time.

Each protocol uses different packet structures andsome contain error checking and even error correction.

Let’s see how the switching works.

A switched fabric system connects devices togetherto support multiple simultaneous data transfers, usuallyimplemented with a crossbar switch.

The packet header provides the necessary routinginformation between source and destination.

Most of you already know about some existingparallel switched fabrics for backplanes such as RACEwayand SkyChannel.

The new generation of switched fabrics uses gigabitserial links instead; there are many contenders forbackplane traffic in embedded systems.

We will look at the most popular ones.

Figure 1 Figure 2



4


Infiniband is primarily aimed at server and storagesystem connectivity for box-to-box links.

StarFabric strength is in providing transparent seriallinks between PCI devices.

PCI Express and the advanced switching extensionis Intel’s initiative for connectivity between processorsand boards in personal computers and workstations.

HyperTransport is promoted by AMD for connectionswithin personal computers.

RapidIO is targeted for embedded computercomponent vendors and system integrators. It addressesthe needs of real-time computing at several levels.

Now let’s see how these fabrics have been adapted tothe popular VMEbus.

Switched Fabric Standards VXS: Switched Serial Fabric for VMEbus

VXS is the popular name for a switched serialbackplane fabric implementation for VMEbus.

Officially, it is being defined by the VITA standardsorganization as specification VITA 41. It defines twotypes of cards.

The VXS Payload Card is a processor, memory or I/Oboard, identical in concept to popular board functionsalready in use.

It has a new P0 connector that contains two serialports for data transfers across the backplane.

Each serial port has four differential gigabit seriallines ganged together for input and another four seriallines for output, and they are commonly referred to as4X serial ports.

The VXS Switch Card is a new type of board withmany serial ports and cross point switches to join thePayload cards.

The VXS specification is fabric-transparent, in thatthere are five subspecifications, one for each of the fivefabrics we just reviewed.


Figure 3 Figure 4


5


VXS Switch CardVXS Payload Card

The VXS Payload card has a standard 6U VMEoutline with standard VME64x backplane connectorsfor P1 and P2.

You can see the new P0 backplane connectormounted between P1 and P2.

This is the new seven row MultiGig RT-2 connectorfor P0 and it handles two full duplex 4X serial ports.

The VXS Switch card has a 6U VME board formfactor but no P1 and P2 connectors.

Instead, it uses several MultiGig RT-2 connectors tohandle up to eighteen 4X full-duplex switched serial ports.

This board joins the payload cards so they can talkto each other.

As you may already have guessed, we obviously needa new backplane.


Figure 5 Figure 6


6


Here’s a possible implementation of a 20-slot VXSbackplane.

It has 18 payload slots, nine on the left and nine onthe right. It also has two switch slots in the center.

The P0 connectors on the payload boards each havetwo 4X serial ports that are wired in copper through thebackplane to the 4X serial ports on the switch boards.

Example: 20-Slot VXS Dual Redundant Star Backplane

Notice there are two links between the switchboards so they can talk to each other as well.

This arrangement gives you two redundant seriallinks between every pair of boards in the cage.

And remember, unlike a bused backplane, all ofthese switched links can be operating at the same time.


Figure 7


7


How Fast Are Switched Serial Fabrics? FPGA Switched Serial Fabric IP Cores

Xilinx offers a simple link layer protocol IP coreengine called Aurora that interfaces with the RocketIOgigabit serial physical layer interfaces available on theVirtex-II Pro family.

Xilinx also offers complete protocol processing IPcores for all of the popular switched serial fabrics wediscussed earlier.

Altera supports its Stratix GX Multi-GigabitTransceivers with the SerialLite link layer protocol aswell as full implementations of switched fabric IP cores.

The nice thing about this strategy is that you candesign and build FPGA-based hardware products thatadapt to different fabrics, depending on the protocol IPcore you install.

The raw speed of serial fabrics is governed by threefactors:

The serial bit clock frequency, the inherent 8b10bchannel encoding efficiency of 80% and the number oflanes or parallel bit streams ganged together in theinterface.

Since there are 8 bits per byte, the peak rate expressedin MB/sec becomes the serial rate expressed in GHz,times the number of lanes, divided by 10.

For VXS, with four bit lanes or 4X, the peak transferrate in each direction is the serial bit clock divided by 2.5.

The table above shows the transfer rates for eachVXS link for both 2.5 and 3.125 GHz bit clocks.

Of course, there is some additional overhead in thepacket protocols.

Figure 8 Figure 9



8


5 Slot Switchless VXS Backplane Switchless Backplane System Concept

Bustronic of Fremont CA and Pentek jointly devel-oped and announced a simple, 5-slot VXS backplanethat allows developers to get started with VXS technologywithout the need for a VXS switch card.

The backplane has three VXS payload slots and twolegacy VME slots. All five slots share the commonVMEbus.

Since there is no VXS switch card slot, the two 4XVXS links of each of the three VXS payload cards arejoined together in a ring.

Each VXS card connects to the other two VXS cardsthrough one dedicated 4X serial link capable of operatingany protocol, including the Xilinx Aurora link layerprotocol.

One benefit of this backplane is that it provides alow-cost development platform and product test envi-ronment for board vendors. It also provides systemintegrators with a low-cost platform for smaller systemswith just a few cards that need extremely high-speedinterconnects between the cards.

The system above, based on the switchless 5-slotVXS backplane, shows a multiprocessor DSP boardconnected to a dual channel A/D board and a dualchannel D/A board with dedicated VXS links.

Each of the VXS link connections shown provides afull-duplex data path operating at speeds up to 1.25 GB/seceach.

For example, the high speed A/D board shownabove could be any of the Pentek 68xx series boardswith maximum sampling rates ranging from 215 MHzto 2 GHz.


Figure 10 Figure 11


9


XMC: Switched Serial Fabric for PMC PMC/XMC Connector Definition


Defined under VITA 42, the XMC specificationextends the PMC card by adding new connections tosupport gigabit serial interfaces plus a growing list ofalternative I/O standards.

As shown in Figure 12, VITA 42.0 is the base specifica-tion that includes general information, reference andinheritance documentation, dimensional specifications,connectors, pin numbering and primary allocation of pairingand grouping of pin functions. This document is stilldesignated as a draft document, but it was released for trialuse for an 18-month period ending March 2007. Recom-mendations gathered during the trial will be used to producea final released specification.

XMCs can be single- or double-width modules thatuse a pin-socket connector with 114 pins arranged in a6 x 19 array. A single-width XMC can have one or twoconnectors with pin functions as shown in Figure 13. Adouble-width XMC can have up to four connectors.

To support gigabit serial interfaces, notice that bothP15 and P16 connectors define 10 full-duplex differen-tial pair lines. The VITA 42.0 base specification doesnot dictate signal types, data rates, protocols, voltagelevels or grouping for these signals. Instead, it wiselyleaves that up to the several sub-specifications that follow,allowing XMCs to evolve as new standards emerge.

VITA Doc Description Status

42.0 Base Specification, general info, Draft

connectors, mechanical, etc. released

42.1 Parallel RapidIO Approved

42.2 Serial RapidIO Approved

42.3 PCI Express Approved

42.4 HyperTransport Draft

42.5 Aurora Planned

42.10 General-purpose I/O Draft

Figure 12

P15 Primary XMC Connector

● 10 differential pairs each direction● JTAG● System Management● Auxiliary● 3.3 V Power:

● Main: 4 pins, 1 A/pin, 13.2 W● Auxiliary: 1 pin, for system management

● Variable Power● 8 pins, 1 A/pin● 5 V (40 W max) or 12 V (96 W max)● Modules must accept 5 V or 12 V● Carriers may provide 5 V or 12 V

P16: Secondary XMC Connector

● 10 more differential pairs each direction● High-speed or single-ended user I/O● Extensions of gigabit serial fabrics

Figure 13

In fact, contrary to the fundamental mission ofsupporting serial interfaces, the first sub-specification,VITA 42.1, defines these same pins for ParallelRapidIO. While VITA 42.1 is approved and fielded,few vendors have embraced this standard and haveinstead opted for the more popular serial protocols.

As shown in Figure 13, most of the pins on P15 arereserved for serial links, power and other functions, butP16 has a wealth of user-defined pins now being addressedby the VITA 42.10 General Purpose I/O draft specifica-tion. It offers a standardized way of implementing inter-faces for popular system I/O including Ethernet, USBports, RS-232, RS-485, Serial ATA, Fibre Channel, andSAS (Serial Attached SCSI). The clear benefit here is thatby following these definitions, XMC and carrier boarddesigners can achieve a much wider range of interoperab-ility, the essential goal of industry standards.


10


FPGAs: New Device Technology FPGAs: New Development Tools

FPGA Resources

It’s virtually impossible to keep up to date on FPGAtechnology, since new advancements are being madeevery day.

The hottest features are processor cores inside thechip, computation clocks of up to 500 MHz, and lowercore voltages to keep power and heat down.

A few years ago, dedicated hardware multipliersstarted appearing and now you’ll find literally hundredsof them on-chip as part of the DSP initiative launchedby virtually all FPGA vendors.

High memory densities coupled with very flexiblememory structures meet a wide range of data flowstrategies. Logic slices with the equivalent of over 10million gates result from silicon geometries shrinkingdown to 0.1 micron.

BGA and flip chip packages provide plenty of I/Opins to support on-board gigabit serial transceivers andother user-configurable system interfaces.

New announcements seem to be coming out everyday from chip vendors like Xilinx and Altera in a never-ending game of outperforming the competition.

To support such powerful devices, new design toolsare appearing that now open up FPGAs to both hard-ware and software engineers. Instead of just acceptinglogic equations and schematics, these new tools acceptentire block diagrams as well as VHDL and Verilogdefinitions.

Choosing the best FPGA vendor often hingesheavily on the quality of the design tools available tosupport the parts.

To minimize some of the tricky timing work forhardware engineers, excellent simulation and modelingtools help to quickly analyze worst case propagationdelays and suggest alternate routing strategies to mini-mize them within the part. This can really save onehours of tedious troubleshooting, not only duringdesign verification but also for production testing.

In the last few years, a new industry of third partyIP (Intellectual Property) core vendors now offerthousands of application-specific algorithms. These areready to drop into the FPGA design process to help beatthe time-to-market crunch and to minimize risk.

Figure 14 Figure 15


11


FPGAs: The Vital Ingredient

Figure 16

FPGAs offer a collection of resources ideally suited forperipheral I/O functions. FPGAs may be configured toimplement numerous electrical interface standardsand a variety of protocol engines. By reconfiguring itsFPGA, not only can a single I/O product replace severallegacy products, it can also adapt to future standards andprotocols as well. This forestalls product obsolescence, bothat the board level and at the deployed system level.

Another reason FPGAs find their way onto VMEboards and mezzanine cards is their unmatched abilityto implement real-time signal processing and high-levellocal control. FPGAs deal effectively with the very highfront-end data rates for A/D and D/A converters,network interfaces, sensor arrays, and high-speed datachannels by mustering a troop of high-performancehardware resources, configured to match the specifictask at hand. For more sophisticated front-end process-ing, most FPGAs now feature DSP engines with built-in hardware multipliers to tackle the toughest algorithmswith ease. Arrays of these engines can be deployed in parallel,completely surpassing the capabilities of general-purposeprogrammable RISC or DSP processors that must executeserial instructions.

By performing these types of intensive protocol,formatting, decoding and DSP functions on the mezza-nine, the workload for the processor on the carrier boardcan be significantly reduced. This may lead to fewerprocessors or fewer processor boards in the system, forconsiderable savings in system cost and size.

With integrated microcontrollers, FPGAs can nowimplement a complete system-on-a-chip. Executing aprogram coded into the FPGA or from an externalFLASH, these microcontrollers can perform complexprocessing tasks to implement real-time control functionsfor adaptive processing, signal classification, targetidentification and object recognition. Having intimatecontact with the surrounding DSP hardware, FPGAmicrocontrollers can modify real-time operating param-eters and modes very efficiently—often well beyond thescope of larger systems with more loosely coupled elements.

With such widespread use of FPGAs on board-levelproducts, the emergence of built-in gigabit serial inter-

FPGA Resources

faces on these devices was a major windfall for switchedserial fabrics. During the last five years, both Xilinx andAltera have invested heavily in developing this technol-ogy, and have now produced three generations of FPGAswith gigabit serial interfaces as shown in Figure 16.

Xilinx offers their RocketIO GTP transceivers onthe latest Virtex-5 LXT family devices with bit rates upto 3.125 GHz. Altera offers their Stratix-II GXmultigigabit transceivers with bit rates up to 6.375 GHz.Both vendors support these physical interfaces withSERDES (serializer/deserializer) hardware engines thatperform serial/parallel conversion so that data and clockare combined in the signaling on each differential pairover the external serial channel.

Protocol engines for specific standards can beconfigured using FPGA logic so that FPGAs can adaptto different protocols as required. They interface to theSERDES and correctly process protocol-specific packets,header information, control functions, error detectionand correction, and payload data format. The strategymakes FPGA-based VXS boards and XMC mezzaninestruly fabric-transparent and allows one hardware design tobe deployed in several different fabric environments.

The new Xilinx Virtex-5 LXT devices advance thetechnology even further by including a built-in PCIExpress end point engine. This saves FPGA resources forother tasks and offers a standardized internal interface forsending and receiving data.


12


FPGA Resources

Figure 17 Figure 18

GateFlow® FPGA Design Resources GateFlow FPGA Design Kit

If you want to add your own algorithms to Pentekcatalog products, we offer the GateFlow FPGA DesignKit that includes VHDL source code for all the standardfactory functions.

VHDL is one of the most popular languages usedin the FPGA design tools. The GateFlow Design Kitincludes the VHDL source code for every softwaremodule we use to create these standard factory featuresof the product.

The standard factory configuration supports a widerange of operating modes, timing and sync functions, aswell as several different data formatting options.

This includes control and status registers, peripheralinterfaces, mezzanine interfaces, timing functions, dataformatting, channel selection, interrupt support, anddata tagging.

These are also fully supported with our ReadyFlowBoard Support Package.

We also include a special User Block, positionedright in the data stream, so you can easily drop in yourown custom signal processing algorithms.

GateFlow is Pentek’s flagship collection of FPGADesign Resources. The GateFlow line is compatiblewith the Xilinx Virtex products and is available as threeseparate offerings:

If you want to add your own custom algorithms, weoffer the GateFlow FPGA Design Kit.

We also offer popular high-performance signal-processing algorithms in the GateFlow IP core Library.These algorithms are designed expressly for XilinxFPGAs and Pentek hardware products

Installed Cores are delivered to you pre-installed inyour Pentek FPGA-based product of choice and are fullysupported with Pentek ReadyFlow® Board SupportLibraries.

Let’s start with the GateFlow FPGA Design Kit.


13


FPGA Resources

Figure 19 Figure 20

GateFlow Design Kit User Block GateFlow Design Kit Project Files

Here’s a simplified block diagram of a typicalsoftware radio mezzanine showing the FPGA as thelarge green box and external hardware devices connectedto it.

The yellow blocks inside the FPGA are VHDL codemodules that handle the standard factory functions andinterfaces.

The User Block is a VHDL module that sits in thedata path with pin definitions for input, output, status,control, and clocks.

In the standard product, the User Block is config-ured as a straight wire between input and output.

If you, the FPGA designer, can create an IP core ora custom algorithm inside the User Block so that itconforms to the pin definition, you will have a very low-risk experience in recompiling and installing the customcode.

And remember, you can also make changes outsidethe User Block, since we provide source code for all themezzanines.

The GateFlow Design Kit is intended to be usedwith the Xilinx ISE Foundation Tool Suite and custom-ers should be trained and familiar with this tool andFPGA design principles, in general.

The design kit installs as a complete project filewithin the ISE environment and includes all the projectfiles that Pentek engineers used to create the standardfactory product. These include configuration anddefinition files, VHDL source, JTAG definition filesand I/O block diagrams.

The design kit also includes several utilities, but oneimportant resource is the FPGA Loader Utility.


14


FPGA Resources

Figure 21

GateFlow Design Kit Loader Utility GateFlow IP Core Library and Installed Cores

Figure 22

Normally, the FPGA is loaded from a nonvolatileEEPROM with the standard factory configuration code,when the product is powered up.

The FPGA Loader Utility allows the processorassociated with the FPGA product to reconfigure theFPGA as a software task, effectively overwriting thefactory configuration code.

This can be done without turning off power,without disassembling the board or system and withoutattaching any special cables or harnesses to the board.

In this way, the FPGA can be reconfigured duringinitialization to install custom operational modes andfeatures. It can also facilitate product upgrades andenhancements to dramatically extend product longevity.

The Loader Utility is especially useful as a runtimeresource. The user can select a new mode of operationand cause a new FPGA configuration upload, to imple-ment that mode as part of the runtime executable code.

Pentek is an AllianceCore Member, a third partyprogram sponsored by Xilinx for companies thatspecialize in specific areas of expertise in developingFPGA algorithms for niche application areas. Theseinclude image processing, communications, telecom,telemetry, signal intelligence, wireless communications,wireless networking, and many other disciplines.

Pentek offers popular high-performance signalprocessing algorithms in the GateFlow IP Core Library.These algorithms are designed expressly for XilinxFPGAs and Pentek harware products. The cores take fulladvantage of the numerous hardware multipliers toachieve highly-parallel processing structures that candramatically outperform programmable RISC and DSPprocessors. They are fully compatible with the GateFlowFPGA Design Kit we just discussed.

Installed Cores are delivered to you pre-installed inyour Pentek FPGA-based product of choice and are fullysupported with Pentek ReadyFlow Board SupportLibraries. Purchasing these popular factory-installedcores saves you the time and costs of acquiring FPGAtools and developing custom FPGA code.

● Pentek is a Xilinx AllianceCoremember

● IP Cores are designed expressly forXilinx FPGAs

● IP Cores are tested and certified for Pentekproducts

● The IP Core Library is compatible with the GateFlowDesign Kit


15


FPGA Resources

Figure 23

VXS and XMC: Extreme Connectivity

Figure 23 depicts a high-speed data acquisition andanalysis system that utilizes products with VXS andXMC, the switched serial fabrics we presented in theopening section of this handbook. These interfaces areimplemented within the FPGAs of the products in thissystem which utilizes a switchless VXS backplane.

Starting at the top left, we have a software radioXMC mezzanine that connects to a G4 PowerPCprocessor board via an XMC interface implemented inits on-board FPGA. The processor board itself is equippedwith an XMC site and connects to the switchless backplanevia the VXS interface of the on-board fabric switch.

Next, we have a high-speed A/D and D/A converterboard that connects to the backplane via VXS which isimplemented in its on-board FPGA.

We also have a second software radio XMC mezza-nine that connects to a VXS platform equipped withXMC and PMC sites; the XMC interface is imple-mented in its on-board FPGA.

A legacy PMC 1553 mezzanine is also connected tothe VXS platform via its PMC site and transfers data tothe fabric switch through the connection implementedin the FPGA of the VXS platform.

In the next section, we will introduce you to Pentekproducts with extreme connectivity. Products that canbe used to create a system such as this.


16


Products

Model 4207 MPC8641D PowerPC Processor with Virtex-4 FPGA - VME/VXS

Figure 24

The Pentek Model 4207 PowerPC® VME/VXS I/Oprocessor board targets embedded applications that requirehigh-performance I/O and processing. With twoPMC/XMC module sites, the 4207 offers powerful one-slot solutions with nearly unlimited high-speed connectivity.

Utilizing a unique crossbar switch architecture, the4207 allows you to make the connections you wantbetween board resources and high-speed interfaces. Youdon’t need hardwiring, or FPGA space to define yourI/O data flow and resource assignment.

The Freescale® MPC8641 utilizes the AltiVec® engineto perform parallel processing of multiple data elements(SIMD) with 128-bit operations. The AltiVec processorexecutes both fixed- and floating-point instructions. It isavailable with either single or dual e600 PowerPC corewith maximum clock frequency of 1.5 GHz.

The 4207 may be optionally equipped with a XilinxVirtex-4 FX FPGA, either the XC4VFX60 or theXC4VFX100. Two 4X RocketIO ports provide high-speed serial data paths to and from the FPGA.

Unused FPGA resources are available for the user toimplement custom signal-processing configurations andalgorithms using Pentek’s GateFlow FPGA Design Kitand the high-performance IP Core Library.

The Model 4207 is supported with world-classsoftware for initialization, control and optimization. Inaddition to GateFlow, this includes real-time OSsupport for VxWorks and Linux, board support packageand VSIPL scientific and engineering functions.

For more information on this product, click 4207

Model4207

■ MPC8641 single or dual corePowerPC processor to 1.5 GHz

■ Xilinx Virtex-4 FX Series FPGA■ Hosts two PMC or XMC modules■ On-board dual gigabit Ethernet

interfaces

■ Optional on-board 4-Gbit dualoptical Fibre Channel controller

■ Optional dual optical gigabitserial Fibre Channel interface

■ Up to 2 GB DDR2 SDRAM

■ Two 64-bit PCI-X buses■ VME64x master/slave interface■ Optional VXS interface■ Ruggedized and conduction-

cooled versions

http://pentek.com/products/Detail.cfm?Model=4207


17


Products

Model 6821 215 MHz A/D with Xilinx Virtex-II Pro FPGAs - VME/VXS

Either two or four FPDP-II ports connect theFPGAs to external digital destinations such as processorboards, memory boards or storage devices.

Optional 4X switched serial fabric ports, compliantwith the VITA 41 VXS backplane fabric standard,deliver data to VXS devices using two full-duplex1.25 GB/sec data ports.

Since the switched fabric interface is implementedusing the Rocket I/O gigabit serial transceivers in theFPGAs, the Model 6821 can support any of the switchedfabric protocols including Serial RapidIO, PCI Expressor the lightweight point-to-point link layer protocol, Aurora.

A VMEbus interface supports configuration of theFPGAs over the backplane and also provides data andcontrol paths for runtime applications.

Figure 25

Model6821


The Model 6821 is a 6U single slot board with theAD9430 12-bit 215 MHz A/D converter.

Capable of digitizing input signal bandwidths up to100 MHz, it is ideal for extremely wideband applicationsincluding radar and spread spectrum communicationsystems.

The sampling clock can be supplied either from afront panel input or from an internal crystal oscillator.Data from the A/D converter flows into two XilinxVirtex-II Pro FPGAs where optional signal processingfunctions can be performed. The size of the FPGAs canrange from the XC2VP20 to the XC2VP50.

Two 128 MB SDRAMs, one for each FPGA,support large memory applications such as swingingbuffers, digital filters, DSP algorithms, and digital delaylines for tracking receivers.



18


Products

Model 6822 215 MHz 2 Channel A/D with Xilinx Virtex-II Pro FPGAs - VME/VXS

The Model 6822 is identical to the Model 6821except it features two AD9430 215 MHz 12-bit A/Dconverters. Each A/D delivers its data directly into theassociated Virtex-II Pro FPGA.

The interfaces and other resources of the Model6822 are the same as the Model 6821 just described.

Both the 6821 and 6822 feature powerful clockingand synchronizing features that allow multiple boards tobe used in multichannel applications where the phaserelationship between channels is critical.

This supports applications such as beamforming,direction finding, diversity receivers and phased-arrayradar applications.

Model6822

Figure 26




19


Products

Model 6826 2 GHz A/D with Xilinx Virtex-II Pro FPGA - VME/VXS

Here’s a high-performance A/D board with twoAtmel AT84AS008 2 GHz 10-bit A/D converters.

Immediately following each A/D is an advanced 8:1demultiplexer that packs eight 10-bit samples across an80-bit parallel bus which reduces the transfer rate to250 MHz, so the FPGA can handle it.

The back end of the board is similar to the 6822but uses a single larger FPGA and we have doubled thesize and width of the external RAM and doubled thespeed by using DDR RAM.

This allows us to capture real time 8-bit datasamples continuously at 2 GHz on both channels untilthe memory is full.

Hopefully, you can reduce the input data rate byprocessing within the FPGAs, but if all the data must besent out of the board, the interfaces are really put to thetest.

If we use 8-bit samples, each A/D generates 2 GB/secat full speed.

The four 400 MB/sec FPDP ports run out of speedat an A/D sample rate of 1.6 GHz for one channel.

With VXS, however, the two 1.25 GB/sec ports canmaintain continuous streaming data at up to 2.5 GB/sec,nicely handling the full 2 GHz A/D speed for onechannel.

Model6826

Figure 27




20


Products

Model 7140 Dual Multiband Transceiver with Virtex-II Pro FPGA - PMC/XMC

A GC4016 four-channel narrowband digital downconverter can be sourced from the A/D converters, fromthe delay memory, or from the PCI bus.

Two 4X switched serial ports, implemented with theXilinx Rocket I/O interfaces, connect the FPGA to theXMC connector with two 1.25 GB/sec data links to thecarrier board.

A dual bus system timing generator allows separateclocks, gates and synchronization signals for the A/Dand D/A converters. It also supports large, multichannelapplications where the relative phase of the communica-tion channels must be preserved.

The 7140 is available in commercial, ruggedizedand conduction-cooled packaging for deployment in awide range of application environments.

Figure 28


The Model 7140 is a complete transceiver PMC/XMCmodule. It includes two 105 MHz 14-bit A/D convert-ers and two 500 MHz 16-bit D/A converters to supporttwo wideband receive and transmit communicationchannels.

The Xilinx Virtex-II Pro FPGA features 6 milliongates of logic density and 232 hardware multipliers forimplementing DSP functions.

It also features 512 MB of SDRAM for implement-ing transient capture of up to 1.28 seconds of A/D datafor radar applications or digital delay memory for signalintelligence tracking applications at 100 MHz.

A 16 MB flash memory supports the boot code forthe two on-board IBM 405 PowerPC microcontrollercores within the FPGA.

A 9-channel DMA controller and 64 bit / 66 MHzPCI interface assures fast efficient transfers amongmodule data sources.



21


Products

Model 7141 Dual Multiband Transceiver with Virtex-II Pro FPGA - PMC/XMC

A GC4016 four-channel narrowband digital down-converter can be sourced from the A/D converters, fromthe delay memory, or from the PCI bus.

Two 4X switched serial ports, implemented with theXilinx Rocket I/O interfaces, connect the FPGA to thenew XMC connector with two 1.25 GB/sec data linksto the carrier board.

A dual bus system timing generator allows separateclocks, gates and synchronization signals for the A/Dand D/A converters. It also supports large, multichannelapplications where the relative phase of the communica-tion channels must be preserved.

Also available as Model 7141-703 is a conduction-cooled version for deployment in a wide range ofapplication environments.

Figure 29


The Model 7141 is similar to the Model 7140transceiver PMC/XMC module. However, the 7141includes two 125 MHz 14-bit A/D converters and two500 MHz 16-bit D/A converters to support twowideband receive and transmit communication channels.

The Xilinx Virtex-II Pro FPGA features 6 milliongates of logic density and 232 hardware multipliers forimplementing DSP functions.

It also features 512 MB of SDRAM for implement-ing transient capture of up to 1.28 seconds of A/D datafor radar applications or digital delay memory for signalintelligence tracking applications at 100 MHz.


A 9-channel DMA controller and 64 bit / 66 MHzPCI interface assures fast efficient transfers amongmodule data sources.



22


Model 7142 Multichannel Transceiver with Virtex-4 FPGAs - PMC/XMC

Figure 30

The Model 7142 is a Multichannel PMC/XMCmodule. It includes four 125 MHz 14-bit A/D convert-ers and one upconverter with a 500 MHz 16-bit D/Aconverter to support wideband receive and transmitcommunication channels.

Two Xilinx Virtex-4 FPGAs are included: anXC4VSX55 or LX100 and an XC4VFX60 or FX100.The first FPGA is used for control and signal processingfunctions, while the second one is used for implement-ing board interface functions including the XMC interface.

It also features 768 MB of SDRAM for implementingup to 2.0 sec of transient capture or digital delay memoryfor signal intelligence tracking applications at 125 MHz.


A 9-channel DMA controller and 64 bit / 66 MHz PCIinterface assures efficient transfers to and from the module.

A high-performance 160 MHz IP core wideband digitaldownconverter may be factory-installed in the first FPGA.

Two 4X switched serial ports, implemented with theXilinx Rocket I/O interfaces, connect the second FPGAto the XMC connector with two 2.5 GB/sec data linksto the carrier board.

A dual bus system timing generator allows separateclocks, gates and synchronization signals for the A/Dand D/A converters. It also supports large, multichannelapplications where the relative phases must be preserved.


Products

Figure 30



23


Model 7150 Quad 200 MHz 16-bit A/D with Virtex-5 FPGAs - PMC/XMC

Products

Figure 31

■■■■■ Dual Virtex-5 FPGAs■■■■■ Four 200 MHz, 16-bit A/Ds■■■■■ 1.5 GB DDR2 SDRAM■■■■■ VITA 42.0 XMC compatible

■■■■■ LVDS Clock/Sync Bus for multi-module

synchronization■■■■■ Dual 4X Serial Fabric Ports■■■■■ PCI 2.2 Interface

7150

Model

Model 7150 is a quad, high-speed data convertersuitable for connection as the HF or IF input of acommunications system. It features four 200 MHz,16-bit A/Ds supported by an array of data processingand transport resources idealy matched to the require-ments of high-performance systems. Model 7150 usesthe popular PMC format and supports the emergingVITA 42 XMC standard for switched fabric interfaces.

The Model 7150 architecture includes two Virtex-5FPGAs. The first FPGA is used primarily for signalprocessing while the second one is dedicated to boardinterfaces. All of the board’s data and control paths areaccessible by the FPGAs, enabling factory installedfunctions including data multiplexing, channel selection,data packing, gating, triggering and SDRAM memorycontrol.

Three independent 512 MB banks of DDR2SDRAM are available to the signal processing FPGA.Built-in memory functions include an A/D data transientcapture mode with pre- and post-triggering. All memorybanks can be easily accessed through the PCI-X interface.

A 9-channel DMA controller and 64 bit / 133 MHzPCI-X interface assures efficient transfers to and from themodule.

Two 4X switched serial ports, implemented with theXilinx Rocket I/O interfaces, connect the FPGA to theXMC connector with two 2.5 GB/sec data links to thecarrier board.

A dual bus system timing generator allows separateclocks, gates and synchronization signals for the A/Dconverters. It also supports large, multichannel applica-tions where the relative phases must be preserved.




24


Applications

4-Channel Software Radio Transceiver System

Figure 32

This system accepts four analog inputs frombaseband or IF signals with bandwidths up to about45 MHz and IF center frequencies up to 140 MHz.A total of 8 DDC channels are independently tunableacross the input band and can deliver downconvertedoutput signal bandwidths from audio up to 2.5 MHz.

Four analog outputs can deliver baseband or IFsignals with bandwidths up to about 45 MHz and IFcenter frequencies up to 100 MHz. The system supportsfour independent D/A channels or two upconvertedchannels with real or quadrature outputs.

Signal processing resources include the FreescaleMPC8641 AltiVec processor and an FX60 or FX100 onthe 4207, plus a VP-50 FPGA on each PMC module.

Using these on-board processing resources thispowerful system can process analog input data locallyand deliver it to the analog outputs. It can also be usedas a pre- and post-processing I/O front end for sendingand receiving data to other system boards connectedover the VMEbus or through switched fabric links usingthe VXS interface.


25


Applications

8-Channel 125 MHz Data Acquisition System

Figure 33

This system digitizes eight analog input signals withbandwidths up to about 60 MHz using four LTC2255125 MHz 14-bit A/D converters on each PMC module.These transformer-coupled inputs accommodate bothbaseband and IF signals at frequencies up to 140 MHz.

Two wideband analog outputs are generated by theone DAC5686 DUC (digital upconverter) on eachPMC module. Each DUC contains a mixer and localoscillator for frequency translation of baseband signalsto IF frequencies up to 140 MHz and higher. EachDUC also contains a 16-bit 500 MHz D/A converterthat delivers the analog output to a front panel coaxialconnector.

Signal processing resources on each PMC moduleinclude either the SX55 for high-performance DSPalgorithms or the LX100 for logic intensive algorithms,depending on the option ordered.

For large multichannel systems, the 7142 PMCscan be synchronized using the front panel sync/gateLVDS bus. In this way, up to 320 A/D channels can beclocked, triggered and gated synchronously using thePentek Model 9190 Clock and Sync Generator.


26


512-Channel Software Radio Recording System

Figure 34

Each Model 7140 PMC features the Xilinx Virtex-4XC2VP50 with a Pentek 256 Channel Digital Down-converter (DDC) IP Core 430. Each channel providesindependent tuning frequency with a global decimationfrom 1024 to 9984. Either one of the two 14-bit A/Dconverters operating at 100 MHz sample rate can feedthis core producing a range of output bandwidths from8 kHz to 80 kHz.

A dual 4-Gbit Fibre Channel copper interfaceallows wideband A/D data or DDC outputs from all512 channels to be recorded in real time to a RAID orJBOD disk array at aggregate rates up to 640 MB/sec.

Pentek’s SystemFlow® software presents an intuitivegraphical user interface (GUI) to set up the DDCchannels and recording mode. The GUI executes on aWindows host PC connected to the 4207 via Ethernet.

A SystemFlow signal viewer on the PC allowspreviewing of data prior to recording and viewing ofrecorded data files in both time and frequency domains.Files can be moved between the Fibre Channel disk andthe PC over Ethernet.

This system is ideal for downconverting andcapturing real time signal data from a very large numberof channels in an extremely compact, low cost system.


27


Applications

Dual-Channel 215 MHz VXS Recording System

Figure 35

The Model 6822 provides two 215 MHz 12-bit A/DConverters capable of digitizing two analog inputs withbandwidths to 100 MHz with a 215 MHz samplingrate. Two 128 MB SDRAMs, one for each FPGA,support large memory applications such as swingingbuffers, digital filters, DSP algorithms, and digital delaylines for tracking filters.

Complete gating and triggering functions supportpulsed signal acquisition for radar applications.

After data is buffered in SDRAM, it can be trans-ferred across two 4X VXS links, each operating at up to1.25 GB/sec.

The Model 4207 VXS ports accept data intoSDRAM buffers for recording onto the RAID or JBODdisk array at rates up to 640 MB/sec.

The duty cycle characteristic of pulsed radar signalsallows elastic memory buffering to average the peakrates to accommodate continuous real-time recording ofthe pulses.

This platform offers a wideband acquisition andrecording system ideal for radar and advanced commu-nication schemes.

RAID or JBOD Array

PENTEK Model 6822


28


Applications

16-Channel Beamforming System

Coninued onNext Page

Sync Bus Cable

To Next 4207

Fro

m Pre

vio

us

4207

VXS Backpla

ne

Figure 36


29


Applications

16-Channel Beamforming System - continued

An 8-channel 16-bit 200 MHz single-slot A/Dsubsystem can be created using two Model 7150PMC/XMC modules mounted on the Model 4207.Two of these subsystems can be joined together tocreate a 16-channel beamforming system.

Data from the first subsystem is beamformed usinglocal FPGA or PowerPC resources, and then sentthrough VXS to the second subsystem. Beamformeddata from the second subsystem is combined with thefirst, and then propagated through VXS to the nextsubsystem or else to the destination for display, analysisor storage.

Joining the sync/gate facilities of all four 7150PMC/XMC modules supports synchronous sampling,triggering and gating of all channels.

Each 4X VXS backplane link supports 1.25 GB/secof traffic between boards.

This modular system can be expanded to addi-tional channels simply by adding additional sub-systems.The VXS mesh backplane provides direct connectionbetween VXS card slots.

Alternate methods for delivering the finalbeamformed output signals include front panel gigabitEthernet to a network and Fibre Channel to a real-timedisk array for real-time recording.


30


Links

The following live links provide you with additional information about the Pentek Productsand presented in this handbook. Links are also provided to other handbooks or brochuresthat may be of interest in your development projects. Reference links give you the opportu-nity to obtain additional information on some of the subjects covered in this handbook.

Model Description Page

4207 MPC8641 PowerPC Processor with Virtex-4 FPGA - VME/VXS 16

6821 215 MHz, 12-bit A/D with Virtex-II Pro FPGAs - VME/VXS 17

6822 Dual 215 MHz, 12-bit A/D with Virtex-II Pro FPGAs - VME/VXS 18

6826 Dual 2 GHz, 10-bit A/D with Virtex-II FPGA - VME/VXS 19

7140 Multiband Digital Transceiver with Virtex-II Pro FPGAs - PMC/XMC 20

7141 Multiband Digital Transceiver with Virtex-II Pro FPGAs - PMC/XMC 21

7142 Multichannel Transceiver with Virtex-4 FPGAs - PMC/XMC 22

7140-430 GateFlow Tranaceiver with 256-Channel DDC Core - PMC/XMC 26

7150 Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC 23

Handbooks and Brochures

Click here Digital Receiver Handbook: Basics of Software Radio

Click here Putting FPGAs to Work for Software Radio

Click here Critical Techniques for High-Speed A/D Converters in Real-Time Systems

Click here High-Speed A/D Boards & Real-Time Systems Brochure

Click here Model 4207 MPC8641 PowerPC Processor Board Brochure

Reference Links

Click here VITA 41: VXS information (some of this may require membership in VITA)

Click here VITA 42: XMC information (some of this may require membership in VITA)

Click here MPC8641D Processor (www.freescale.com)

Click here Xilinx FPGA information (www.xilinx.com)

Click here DDR SDRAM information (www.micron.com)








http://pentek.com/products/Detail.cfm?Model=7140-430


http://pentek.com/deliver/TechDoc.cfm/HSADbroF.pdf?Filename=HSADbroF.pdf

http://pentek.com/deliver/TechDoc.cfm/4207_brochure.pdf?Filename=4207_brochure.pdf

http://www.pentek.com/go/iobrodrhb

http://www.pentek.com/go/iobrofpgahb

http://www.pentek.com/go/iobroadhb

http://www.vita.com

http://www.vita.com

http://www.freescale.com

http://www.xilinx.com

http://www.micron.com

high-speed switched serial fabrics improve system design · high-speed switched serial fabrics...

Documents