high speed, low power datapath design using multi ......corporates a 4t xor design and a static cmos...

International Journal of Scientific & Engineering Research, Volume 5, Issue 5, May-2014

ISSN 2229-5518

IJSER © 2014

http://www.ijser.org

High Speed, Low Power Datapath Design using Multi

Threshold Logic in 45nm Technology for Signal

Processing Application Suryasnata Tripathy, Sushanta K. Mandal

Abstract— The paper proposes a novel full adder architecture based on MVT (multi threshold voltage) design style for high speed and low

pow er arithmetic. The 14T topology is realized using pass transistor logic, static CMOS logic and transmission gate based logic; resulting in

small on chip area requirement, less pow er dissipation and small propagation delay. The paper also proposes a 4:2 compressor based

realization of 4-bit Vedic multiplier. The proposed architectures are designed and simulated in 45nm standard CMOS process technology

using Cadence Spectre environment. The full adder design achieves average pow er dissipation up to 64nW and propagation delay up to

58 pS for a pow er supply of 1 volt. The paper incorporates a circular convolution implementation of tw o 4-bit sequences to demonstrate the

eff iciency of the proposed datapath elements.

Index Terms— high speed, low power, full adder, CMOS, multi threshold logic, compressor, Vedic multiplier, pass transistor logic,

transmission gate based logic.

—————————— ——————————

1 INTRODUCTION

Bulk of the computation associated with a digital datapath for real time signal processing involves multiplication task. The latency associated with any multiplier unit is mostly contribut-ed by the adder assembly embedded within for adding the partial products. As the operand size increases, the number of partial products to be added also increases significantly, in accordance with a nonlinear relationship. With the increase in number of partial products, the adder assembly employed to add them becomes more and more bulky, resulting in large propagation delay and power consumption, literally making the multiplier unit almost unsuitable for modern day proces-sors. Thus there is a need of developing power aware adder and multiplier architectures capable of performing high speed arithmetic without consuming any unappreciable amount of power. Eminent researchers have been trying for several years to develop high speed low power full adder and multiplier architectures that would render fast arithmetic processing. The conventional static CMOS full adder [1], pass transistor logic based full adder [1] [16], transmission gate (TG) based adder [3] fail to provide the desired performance because of the high transistor count and high activity factor associated with them. Several modified architectures reported in literature succeed in providing appreciable performance at the cost of output swing, making the topologies unsuitable for cascading applications. The conventional array multiplier, carry save multiplier, Wal-lace tree multiplier and Booth multiplier have been studied extensively for years to increase the efficiency of such designs in terms of overall speed and power consumption, along with the total area requirement. Several research works intend to reduce the no of partial product addition stages required for a particular multiplier block to increase the efficiency, while some of the researchers have tried to decrease the number of Suryasnata Tripathy is currently pursuing his MTech in School of Electronics

Engineering, KIIT University, India. E-mail: [email protected] Sushanta K. Mandal is currently working as a professor in School of Electronics

Engineering, KIIT University, India. E-mail: [email protected].

nonzero partial products by implementing various encoding schemes. However the use of ancient Vedic Sutras (mathemati-cal formulae introduced by Vedas) to realize fast multiplication [5] [6] units has provided significant improvement in overall performance of the multiplier blocks. The use of parallel com-puting approach in Vedic multipliers [13] accounts for the overall improvement in performance. In this paper, a new full adder architecture for low power and high speed arithmetic is proposed. The 14T topology is developed with MVT (multi threshold voltage) logic for achieving a speed-power trade off by identifying the critical path. A 4×4 Vedic multiplier is also presented in this work which is realized using compressors. The performance analysis for the full adder is carried out with different power supply voltages and also at different process corners to validate the robustness of the design. A comparison of the performance of the proposed topology with the state-of-the-art is provided to highlight the effectiveness of the design. To demonstrate the effectiveness of the proposed datapath el-ements, a 4-bit circular convolution process is realized using the same. The rest of the paper is organised as follows. Section 2 presents a brief discussion about the full adder fundamentals and introduces the proposed full adder design. Section 3 pre-sents the compressor based 4-bit Vedic multiplier. Section 4 explains the circular convolution application. The simulation setup and detailed performance analysis is presented in section 5. Section 6 concludes the discussion.

2 FULL ADDER FUNDAMENTALS AND PROPOSED

ARCHITECTURE

A full adder unit is a conventional 3:2 compressor [16] that accepts three inputs and results in two distinct outputs. In case of a general adder configuration, two of the three inputs corre-spond to the same bit weight whereas the third input, desig-nated as the carry-in signal, ripples from the previous addition stage. The two outputs, namely sum and carry-out, are gener-

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International Journal of Scientific & Engineering Research Volume 5, Issue 5, May-2014

ISSN 2229-5518

IJSER © 2014


ated by following a series of Boolean arithmetic that conven-tionally involves XOR operation, AND operation and OR op-eration. The relationship among the inputs and outputs can be mathematically represented as:

Sum= A ^ B ^ Cin Carry-out= (A ^ B) .Cin | A . B

Where, A, B and Cin are the three inputs to the adder unit, sum and carry-out are the generated outputs. The symbols ̂ , . and | represent XOR, AND and OR operation respectively. The paper proposes a new full adder architecture for low pow-er and high speed arithmetic. The architecture is designed in 45 nm CMOS process technology in Cadence EDA tool. The 14T configuration, presented in Fig. 2 is based on a multiplexer based analogy for full adder operation. The sum logic realiza-tion is accomplished by a mux with Cin (the input carry from previous stage) being the selecting input. The multiplexer switches the XOR and XNOR outputs of the other two inputs to the sum terminal when Cin is 0 and 1 respectively. The mul-tiplexer topology used to realize the carry-out logic assumes A ^ B (where A and B are the two inputs to the full adder stage) output as the selecting input and switches either the carry-in value or either of the input signals to the output. The proposed architecture incorporates a 6T XOR-XNOR design [14] that in-corporates a 4T XOR design and a static cmos inverter to real-ize the coincidence logic. The XOR logic circuitry, presented in Fig. 1, provides a full swing output for all the input combina-tions of the two inputs A and B, except for the case when both the inputs are zero. In that situation, a |Vtp| rise dominates the output swing owing to the pass transistor design. However the topology is an effective one due to the compactness of the design and the fast operation speed. The 2:1 multiplexer cir-cuitry for realizing the carry-out is implemented with a TG based approach that results in rail-to-rail output swing. Also, the transmission gate based design yields a low resistance path that facilitates high speed arithmetic. The multiplexer unit used for sum logic realization is implemented using pass transistor logic along with two swing restoring nmos arrangements, as shown in Fig. 2. Because of the pass transistor based design, it is evident that the sum logic would suffer from threshold volt-age deficits for different input combinations. However, the presence of two swing restoring transistors ensures rail-to-ring output swing at the sum terminal. For the case when Cin is logic zero, A^B output is switched to the sum terminal using a pmos pass transistor. As pmos is known to pass good logic 1, the sum output assumes full voltage swing when A^B output is logic high. However, if A^B is logic 0, the sum logic is expected to have a non-ideal output swing because of the inability of the pmos transistor to pass good zero logic. This inconvenience is removed by the swing restoring nmos transistor which pulls down the sum logic to complete logic zero. Similarly, for the case, when Cin is 1, the nmos pass transistor is active and it switches the A XNOR B output to the sum terminal. Due to the inability of the nmos pass transistor to pass good logic 1, the sum terminal is expected to encounter a threshold voltage drop when A XNOR B becomes logic high. However this condition is resolved by the swing restoring pmos transistor which pulls up

the sum output to complete logic 1. Thus the two swing restor-ing transistors along with the pass transistor based multiplexer arrangement result in a sum logic that attains rail-to-rail volt-age swing.

fig. 1 6T XOR-XNOR circuitry [14]

The proposed design, presented in Fig. 2, is then modified us-ing MVT (multi threshold voltage) based design style for ob-taining optimized performance. The MVT design style incor-porates both high threshold and low threshold devices for achieving a speed power trade off. The low threshold devices account for high speed arithmetic by lowering the overdrive whereas the high threshold transistors ensure small leakage power, thereby reducing the overall power consumption. With the advent of submicron technology, the leakage power has become a significant contributor to the total power dissipation associated with any design and thus by reducing the effect of this power component, the high threshold devices actually con-tribute immensely towards total power reduction. The initial step for such a design is to identify the critical path of the to-pology. The concept of critical path varies from design to de-sign and it depends upon the designer’s perspective of perfor-mance. In most of the ripple carry adder arrangements, all the inputs are available at once and hence the main speed bottle-neck happens to be the rippling path of the carry signal. Thus in such a situation, the carry generation path becomes the criti-cal path. However, for a carry save adder arrangement, the concept of a critical path changes completely as for all the ad-der stages, the inputs arrive at different time instances. For the proposed adder architecture, the XOR-XNOR generation unit is considered to be the main source of latency as the adder cir-cuit is expected to be used in carry save arrangements perform-ing partial product addition in high speed multipliers.Thus this unit of the adder architecture is realized with low thresh-old devices to increase the overall propagation speed of the entire architecture. As the carry generation unit is implement-ed using a TG based multiplexer circuit driven by A XOR B and A XNOR B outputs, certain transistors are expected to wait for a longer instance till the driving input arrives, because of the inverter arrangement in the XOR-XNOR circuitry. Thus the transistors driven by A XNOR B output are modified to low threshold devices for compensating the above mentioned la-tency. The power overhead introduced by the use of these low threshold devices is compensated by using several high threshold devices.

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fig. 2 The proposed Full Adder Architecture

fig. 3 The proposed Full Adder Architecture with MVT Logic

3 4×4 MULTIPLIER ARCHITECTURE USING

COMPRESSORS

The 4-bit Vedic multiplier architecture proposed in [8] can be realized using 3:2 compressors (Full Adders) and 4:2 compres-sors. The compressor based topology, presented in Fig. 7, is a 238T design. The topology is based on Urdhva Tiryakbhyam (UT) Sutra of Vedic mathematics which is presented in Fig. 4. The vertical and crosswise lines present in Fig. 4 represent the generation of partial products by ANDing the corresponding operand bits, represented by the dots. The 4:2 compressor de-sign utilized in the realization of the multiplier topology is pre-sented in Fig. 5 and Fig. 6. The 4:2 Compressor block takes five

inputs and results in three outputs, as shown in Fig. 5(a). The four inputs, namely x1, x2, x3 and x4 and the sum output have the same weight, whereas the output carry is weighted one binary bit order higher. The input cin is the carry in signal rip-pled from the preceding module. The intermediate carry out signal, designated as Cout, is connected to the next compressor module as the carry in signal. The block diagram for the com-pressor architecture is presented in Fig. 5(b). The compressor architecture, shown in Fig. 6, is a 28T design based on multi threshold voltage logic. The main idea for the compressor ar-chitecture is presented in [12]. This paper contributes towards the realization of the topology using multi threshold logic for achieving improved performance. The utilization of high threshold and low threshold devices in the compressor design provide a trade-off between speed and power .The low thresh-old transistors on the critical path ensure less propagation de-lay whereas the high threshold devices make sure the power consumption stay within acceptable limits.

fig. 4 Vedic multiplication line diagram (4-bit)

Fig. 7 shows the 4-bit Vedic multiplier architecture realized using the proposed full adder and the 4:2 compressors. The chain of AND gates is used for parallel generation of the partial products for the multiplier. The AND gates used for the pur-pose are modified 5T designs as presented in [8]. The addition of the partial products is performed in accordance with the 4-bit Vedic multiplication line diagram presented earlier in the paper. The Half adder blocks used for the partial product addi-tion are 9T designs as presented in [8]. The inputs A and B in the figure are 4-bit vectors and the output P (P7 to P0) is an 8-bit vector. The abbreviations HA and FA represent a half adder and a full adder unit respectively.

fig. 5(a) 4:2 compressor

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fig. 5(b) 4:2 Compressor Block Diagram

Fig. 6 4:2 Compressor with MVT Logic

4 CIRCULAR CONVOLUTION

Circular convolution of two N-point finite sequences can be efficiently evaluated by using Vedic mathematical computation [4] [7]. The use of UT sutra for circular convolution yields fast arithmetic with reduction in hardware complexity and power consumption as compared to conventional methods. The UT sutra based circular convolution technique involving two 4 point sequences x(n) = {x0, x1, x2, x3} and h(n)= { h0, h1, h2, h3} is described in Fig. 8. and can be summarized as follows [4]. The partial products P0 to P6 are generated using the 4-bit Vedic multiplier. These terms yield the linear convolution of the two sequences [4]. To obtain the circular convolution output, several adder blocks are used to perform the required addition as indicated by the plus symbols in Fig. 8.

fig. 7 4-bit Vedic Multiplier with compressors

The final output y(n)= {y0, y1, y2, y3} can be represented as: y0= P0 + P4 (1) y1= P1 + P5 (2) y2= P2 + P6 (3) y3= P3 (4) The paper presents circular convolution of two 4-bit sequences using Vedic mathematics, however, the technique can be extended to larger values of N without the loss of generality.

fig. 8 Circular Convolution using Vedic Multiplier

5 SIMULATION RESULTS AND PERFORMANCE ANALYSIS

The proposed architectures are realized in 45 nm CMOS process technology using Cadence EDA tool. The performance analysis for the full adder topology is carried out with different power supply voltages and also at different process corners to validate the robustness of the design. The layout of the pr o-posed topology for realizing the post layout simulation is de-veloped using the Layout XL editor of the Cadence EDA tool. A comparison of the performance of the proposed full adder with the state-of-the-art is provided to highlight the effectiveness of the design. The results are tabulated in Table 1-4. Table 1 sum-marizes the performance of the 14T full adder architecture, shown in Fig. 2, for four different combinations of the transis-tors, based on the threshold voltages of the individual FETs. The letter L and H in the nomenclature indicate low threshold

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Table 1: Performance analysis of the 14T full adder architecture with a supply voltage of 1 volt

Table 2: Performance analysis of the proposed full adder archi-

tecture with different supply voltages

Table 3: Performance analysis of the proposed full adder archi-

tecture at different process corners

Table 4: Comparison of performance of the proposed full adder

with state-of-the-art

and high threshold condition for the devices, respectively. The first letter corresponds to the condition of the PFET and the second letter indicates the voltage threshold of the NFET. As evident from the tabulated data, the LH combination yields the best performance with respect to the propagation delay, at a

power supply of 1 volt. However, the power dissipation is at the minimum for the HH combination. The propagation delay and the power dissipation values associated with the proposed MVT based full adder architecture for different supply voltag-es are tabulated in Table 2. The propagation delay here indi-cates the delay between the carry-in and the carry-out signals. The propagation delay increases slowly as the power supply varies from 1 volt to 0.8 volt. The effect of reduction of supply voltage on the overall power dissipation is also demonstrated in Table 2. The overall impact of power supply reduction on the performance of the topology is presented in Fig. 9. In Table 3, a performance analysis of the adder architecture is presented at the five different process corners to validate the robustness of the topology. The letters FF (fast-fast), FS (fast-slow), SS (slow-slow), SF (slow-fast) and TT represent the five possible process corners associated with CMOS process technology, where the first letter indicates the condition of the PFET and the second letter indicates that of the NFET. A comparative performace analysis between the proposed full adder design and the state-of-the-art is presented in Table 4. Fig. 9 and Fig. 10 summarize the above discussion. The performance of the 4-bit Vedic multiplier with compressors is tabulated in Table 5. The use of 4:2 compressors and multi threshold logic results in improved performance for the multiplier architecture. The cir-cular convolution using Vedic mathematics is realized using two different multiplier topologies; first with a Vedic multiplier [8] that uses 2-bit multiplier blocks and several carry save ad-der arrangements, and later by using the proposed compressor based topology. The comparative performance analysis is pre-sented in Table 6. The McCMOS based technique, presented in [4], definitely performs a much faster arithmetic compared to the proposed multiplier based approach. However, the power consumption associated with the proposed approach is signifi-cantly improved as compared to the McCMOS technique.

fig. 9 Performance analysis of the proposed Full adder at

different supply voltages

fig. 10 Performance Comparison of the proposed full adder

architecture with the state-of-the-art

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Table 5: Performance analysis of the 4-bit Vedic multiplier

Table 6: Performance analysis of the Circular Convolution ap-

proach and comparison with state-of-the-art

6 CONCLUSION

The paper presents a novel architecture for 1-bit full adder

based on MVT design style that exhibit appreciable perfor-

mance with respect to overall propagation delay, on chip area

requirement and average power dissipation. The topology is

realized in 45 nm technology using the Cadence EDA tool, vir-

tuoso environment. The paper also proposes a 4-bit Vedic mul-

tiplier architecture using 4:2 compressors. To demonstrate the

usefulness of the proposed datapath elements in signal pr o-

cessing applications, circular convolution of two 4-bit sequenc-

es is also presented in the paper. The simulation results ob-

tained are tabulated above to support the claim of the effec-

tiveness of the designs. A corner analysis is performed at the

five different process corners to demonstrate the robustness of

the full adder architecture. The effect of power supply varia-

tion on the propagation speed and power dissipation parame-

ters of the proposed full adder is also analyzed. The compara-

tive analysis presented in the paper demonstrates the effec-

tiveness of the proposed architectures.

REFERENCES

[1] R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS

versus pass-transistor logic,” IEEE J. Solid-State Circuits, vol. 32, pp.

1079-1090, July 1997.

[2] S. Issam, A. Khater, A. Bellaouar and M. I. Elmasry, “Circuit

techniques for CMOS low-power high performance multipliers,” IEEE

J. Solid-State Circuit, vol. 31, pp. 1535-1544, Oct. 1996.

[3] N. Weste and K. Eshragian, “Principles of CMOS VLSI Design: A

System Perspective” , Addison-Wesley, 1993.

[4] Jubin Hazra, “ An efficient design technique of circular convolution

circuit using Vedic Mathematics and McCMOS technique”,

International conference on Computer Communication and

Informatics, Coimbatore, January 10-12, 2012.

[5] Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim, Yong

Beom Cho, “ Multiplier design based on ancient Indian Vedic

mathematics”, IEEE International SoC design conference, 2008.

[6] Parth Mehta, Dhanashri Gawali, “ Conventional versus Vedic

mathematical method for hardware implemetation of a multiplier”,

IEEE 2009 International conference on advances in computing, control

and telecommunication technologies.

[7] John W. Pierre, “ A novel method for calculating the convolution sum

of two finite length sequences”, IEEE transactions on Education, vol.

39, No. 1, February 1996, pp. 77-80.

[8] Suryasnata Tripathy, LB Omprakash, B S Patro, Sushanta K Mandal,

“Low Power, High Speed Multiplier Architectures using Vedic

Mathematics In 45nm Technology”, IEEE transactions on VLSI

systems, January 2014. Submitted for publication.

[9] Raju Gupta, Satya Prakash Pandey and Shyam Akashe, “Comparative

Analysis and Optimization of Active Power and Delay of 1-Bit Full

Adder at 45 nm Technology,” .IEEE Students Conference on

Engineering and Systems (SCES) , pp.1-5, 12-14 April 2013.

[10] Raj Johri, Raghvendra Singh, Satya Prakash Pandey, Shyam Akashe

,“Comparative analysis of 10T and 14T full adder at 45 nm

technology”,2nd IEEE International Conference on Parallel

Distributed and Grid Computing (PDGC), pp.833-837, 6-8 Dec. 2012.

[11] Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan

Chatterjee, C. K. Sarkar, “Design and Analysis of a Robust, High

Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell”, IEEE

International Symposium on Electronic System Design (ISED),

pp.130-134, 19-22 Dec.2012.

[12] Chip Hong Chang, Jiangmin Gu, Mingyan Zhang, “Ultra low voltage

low power CMOS 4-2 and 5-2 compressors for fasr arithmetic

circuits”, IEEE Transactions on Circuits and Systems—I: regular

papers, vol. 51, no. 10, october 2004.

[13] Swami Bharati Krisna Tirthaji Maharaja, “Vedic mathematics”,

original edition, Motilal Banarasidass publishers.

[14] Phuong Thi Yen, Noor Faizah Zainul Abidin, Azrul Bin Ghazali,

“Performance analysis of full adder (FA) cells,” IEEE Symposium on

Computers and Informatics (ISCI) , pp.141-146, 20-23 March 2011.

[15] Suryasnata Tripathy, LB Omprakash, B S Patro, Sushanta K. Mandal,

“Low power, High Speed Full Adder Architectures in 45 nm

Technology”, International conference on VLSI and Signal processing,

IIT Kharagpur, India, 10-12 January, 2014.

[16] J. M. Rabaey, A. Chandrakasan and B. Nikolic , “ Digital integrated

circuits-A design perspective”, second edition, PHI Learning Pvt. Ltd.

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