high-speed electrical...
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EE290C - Spring 2004Advanced Topics in Circuit Design
High-Speed Electrical Interfaces
Borivoje NikolicJared Zerbe
Tu-Th 4 – 5:30pm531 Cory
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Practical Information
Instructors: Borivoje Nikolic
570 Cory Hall , 3-9297, bora@eecsOffice hours: M 11am-12pm; Th 1:30-2:30pm
Jared [email protected] hours: after the lecture
Guest lectures: Martin Graham, Vladimir Stojanovic, Ben ChiaReader: Socrates Vamvakos, sokratis@eecsAdmin: Rosita Alvarez-Croft
201 Cory Hall, 643-8167, rosita@eecs
Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/ee290c_s04
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Class Organization
4 (+/-) assignments1 term-long design project
Midterm reportReport and presentations last week of classes
Presentation on a link paper from ISSCC’04Quiz on the course materialNo final exam
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Class Material
Textbook: W.J. Dally, J.W. Poulton, “Digital Systems Engineering,” Cambridge University Press, 1998. List of background material available on web-siteSelected papers will be made available on web-site
Linked from IEEExplore and other resourcesNeed to be on campus to access, or use library proxy (check http://library.berkeley.edu)
Class-notes on web-site
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Other Books
Other reference books:H. Johnson, M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice-Hall, 1993.S.H. Hall, G.W. Hall, J. A. McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, Wiley, 2000.B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2002
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Sources
IEEE Journal of Solid-State Circuits (JSSC)IEEE International Solid-State Circuits Conference (ISSCC)Symposium on VLSI Circuits (VLSI)Other conferences and journals
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Lecture Videos
Lectures are videotapedPlease speak clearly when asking questions
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Class Topics
The course covers the system and design issues relevant to high-speed electrical (and optical, if time permits) signaling. We start with the basics of channel properties, modeling, measurements, and communications techniques. Circuit design of main components is covered in detail. The system design issues such as planning and budgeting are presented. A large portion of the class is devoted to case studies that include the multi-Gb/s serial and parallel chip-to-chip interfaces, Gigabit and 10-Gigabit Ethernet over copper, VDSL (and possibly 10Gig optical).
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Class Topics1.Channels
Physical Components (PCBs, connectors, vias, cables)Modeling (loss, reflections, crosstalk, …)Practical channel measurements(Optical/fiber issues)
2.Communication techniquesEqualization –receive, transmit, DFEModulation techniques – PAM, QAMCodingAdaptation
3.ComponentsTransmittersReceiversPLL/DLLClock and data recoveryEqualizersViterbi decodersDecision-feedback equalizers (DFE)
4.System tradeoffsSystem clockingSerial/parallel power & complexity
5.BudgetingBER analysis, planningBER Measurement
6.Forward Error CorrectionParityReed-SolomonLow-density parity check (LDPC) codes
7.Case studiesXAUI, PCI ExpressGigabit Ethernet/ 10GbEthernetPRML read channelVDSL(10G optical)
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Project
Design of a High-Speed LinkFrom a channel specification to building a transcieverGroups of about 4 students
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Tools
MatlabHSPICE
You need an account on cory.eecs
0.18µm CMOS device models (TSMC/MOSIS)And predictive sub-100nm models
Other tools, schematic or layout editors are optionalCadence, Synopsys, available on mingus.eecs
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Presentations
You will be required to go to ISSCC’04February 14-19, San Francisco Marriott Hotel
No lectures that weekClass presentation on link papers from ISSCC
Critical review
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Grading
Project 60%Homeworks 20%Presentation 10%Quiz 10%
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Suggested Reading
Chapter 1Chapter 3, Sections 3.1, 3.2, 3.3, 3.4Review wires, transmission lines
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Background
Chip-2-ChipCablesSingle connectorBackplanesEthernet
Increasingcomplexity
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What Makes a Link?
Signaling: sending and receiving the information
Clocking: Determining which bit is which
RxTx
RTERM
Channel
RTERM
tbit /2
1 0 0 01 01
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Spanning A Broad Space
Inverters.........to……..DSL modemMetrics
SpeedLatencyElectrical environmentPower & areaVolume
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Applications
Chip-to-chip signalingComputers, games: SDRAM (DDR, DDR2) 100-400MHz, RDRAM 800-1600MHz, XDR DRAM 3.2-6.4GHz
Board-to-board signaling:Computers: Peripherals - PCI (66-133-400MHz), - Infiniband(2.5Gb/s)
Networks: LAN: Fast Ethernet, Gigabit Ethernet, 10G Ethernet, opticalWAN: OC-12 (625Mb/s), OC-192 (12.5Gb/s)Routers: 625Mb/s – 2.5Gb/s
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Example 1: Router Backplane
Distributed architecture with crossbar switch fabric
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Example 1: Router
OC-192 Line Card
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The Need for Speed
Passive backlpane is a common interconnect architecture:
networking routers, LAN switches, telecom equipments blade servers/ parallel computers
Number of slots limited by geometry (standard racks), power, airflow, etc.
Fastest routers use up to 16 line cards
T1 ? DS3 ? OC12 ? OC48 ? OC192 ? OC7681Mb/s ? … … ? 40Gb/s
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Serial Link Signaling Over Backplanes
At low speeds (<~3Gb/s) channel was not a problemLossless transmission line
Speed limited by electronics
serdes
BackplaneLinecard Linecard
serdes
Signal at Tx Signal at Rx
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Backplanes Today
At 10Gb/s almost no detectable signal arrives to the receiver
serdes
BackplaneLinecard Linecard
serdes
Signal at Tx Signal at Rx
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SI drives Si above 3Gb/s
What’s your perspective? 3G? 6G? 10G?We must understand much more about the problem to operate above 3Gb/s
1.00E-03
1.00E-02
1.00E-01
1.00E+00
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Frequency (GHz)
1.00E-03
1.00E-02
1.00E-01
1.00E+00
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Frequency (GHz)1.00E-03
1.00E-02
1.00E-01
1.00E+00
0.0 1.0 2.0 3.0 4.0 5.0
Frequency (GHz)
3G view 6G view 10G view
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The Backplane Environment
The problem is there are many sources of Z…and thus many possible sources of reflections
Back plane connector
Line card trace
Package
On-chip parasitic (termination resistance and device loading capacitance)
Line card via
Back plane trace
Backplane via
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Band-Limited Communications
Solutions are known:Equalize channelMultiple bits per symbolAllow ISI (partial response); Viterbi, decision feedback equalizerOFDMWaterfill,…
Key challenge: how to do some of this at extreme speeds or in extreme channels?
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Example 2: Gb/s Ethernet
1000BaseT (1Gb/s Ethernet is widespread)CAT-5 cable4 x 250Mb/s2 bits/symbol, PAM-5125MS/s per TPLoss + NEXT No FEXT Cancellation
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Cable Capacity (CAT6 / Class D)
Source: Avaya/ IEEE802.3 10GT group
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10Gb/s Ethernet
Full-duplex echo cancellerFull-duplex echo canceller
833Mbaud, ~450MHz BW125Mbaud, ~80MHz BW
FEXT Cancellation requiredNo FEXT cancellation
8-state trellis over 4 pairs8-state trellis over 4 pairs
10-level PAM (3 b/symbol)5-level PAM (2b/symbol)
10GBase-T1000Base-T
Throughput = 4pairs x 833Mbaud x 3b/baud = 10Gb/s
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Digital Baseband Transceiver
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Class Schedule1.Introduction (0.5 weeks)2.Channels (~1 week)
Physical components and modelingPractical channel measurements
3.Communication techniques (1 week)Equalization, modulation techniques, codin, adaptation
4.Components (1.5 weeks)Transmitters, Receivers, PLLs/DLLsClock and data recovery
5.ISSCC (2 weeks)Presentations
6.Components, continued, (2 weeks)EqualizersViterbi decodersDecision-feedback equalizers (DFE)
7.Midterm reviews (0.5 weeks)
8. Forward Error Correction (1 week)Parity, Reed-SolomonLow-density parity check (LDPC) codes
Spring Break8. System tradeoffs (0.5 weeks)
System clockingSerial/parallel power & complexity
9. Budgeting (1 week)BER analysis, planningBER Measurement
10. Case studies (3 weeks)XAUI, PCI ExpressGigabit Ethernet/ 10GbEthernetPRML read channelVDSL(10G optical)
11. Project presentations (1 week)