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Te c h n o l o g y W h i t e P a p e r

High-per formance Element Processing Architecture for Open Standards Radar Systems

Introduction

This paper will describe High-performance Element Processing Architecture as a basis for large array radar systems, enabling system designers to increase levels of digitization by using open standards based hardware.

Traditionally, the vast majority of deployed military radar systems employ electronically scanned phased array (ESA) radar technology, comprised of 100s to 10,000s of transmit and receive (T/R) elements. These ESA-based radar systems vary in implementation, but typically the elements are clustered to create a beamform. The resulting analog signal is then digitized. The next step involves Digital Beamformers (DBFs) that aggregate the digitized signals and then, via various mathematical techniques, generate a final beamformed image. This final image is then sent to target computers for various radar requirements. The initial step of digitizing the analog signal may soon be obviated by the availability of new analog-digital converters (ADCs); high-bandwidth, low latency networks; and significant improvements to digital signal processors (DSPs), which can be used to provide complete digitization at the element level. The result will be a new era of digital array radars (DARs). This new level of digitization will allow the modification of system capabilities by simply changing the system software, which is difficult in the case of analog, ESA-based radars.

One of the largest hurdles to the adoption of DARs faced by today’s military systems integrators is the significant challenge of scaling their programs from traditional systolic DBF designs to fully parallel DBFs. New open standard commercial off-the-shelf (COTS) OpenVPX™-based systems, with their novel approach to backplane interconnection, can provide system designers with the significant architecture flexibility they require to quickly and easily migrate current ESA radar to DAR.

Radar is commonly used to locate, track, and identify objects. These tasks are accomplished by emitting radio waves and capturing the return signal by some type of sensor. This process has evolved from the single emitters used in early radar, to the multiple sensors deployed in an array that we see today. Contemporary sensor arrays feature transmit and receive (TR) elements. The process of aggregating the TR elements together is beamforming. In the early days of radar, beamforming was entirely an analog process. Now, technology advancements including new high-speed, low-noise, large bandwidth ADCs; high-speed, large bandwidth, low latency networks; and new high-speed DSPs promise to rapidly increase the digitization of radar systems. The advantages that DAR provides include “a number of advanced spatial processing features such as adaptive digital beamforming, adaptive angle estimation and spacetime processing against cluster.” (Tarran, 2008). All of these features have the potential to significantly increase the capability and usability of radar systems, while improving total cost of ownership, with improved reliability.

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An example of a state-of-the art radar array is shown in Figure 1. In this model the TRs are channelized and grouped to create a multiplexed beam. The multiplexed beams are then digitized. Next, these clusters are digitally beamformed so that the radar back-end processor can track, locate and target, or form a radar image. (Mark Weber, 2005). The concept of digitizing to the TR is illustrated in Figure 2. In this stage, digitizing is brought to each TR array, making no analog clustering or beamforming necessary. The Real Time Beamformer (RTB) can be realized using fully parallel or systolic designs.

Figure 1: Traditional ESA Radars

Figure 2: DARS

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A fully digital DBF design, as shown in Figure 3, would benefit from a network of M connections of TRs to N connections of signal processors. A systolic DBF would benefit from a sensor streaming network such that digitized analog signals are beamformed in a serial stream, as in Figure 4 (Mark Weber, 2005).

Figure 3: Fully Parallel DBF Design

Figure 4: Block Diagram of a Systolic DBF Design

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Creating a DAR can be difficult, depending on the number of TR elements, the bandwidth and bit-width that need digitizing, and the enormous number of calculations required. Fortunately, the commercial market for cell phones (ADCs), HD television (network bandwidth), and computer games (DSPs) – combined with Moore’s Law - are helping to increase the amount of digitization possible every year. The downside of this rate of technological change has been the burden placed on system designers to create the new boards and systems (backplane and chassis) needed for each year’s new and improved radar systems. A better approach to speed and simplify system integration is to design the DAR using OpenVPX-based COTS boards, which lowers the costs of technology improvements and eliminates the need to remove the installed chassis or system for repairs and upgrades.

OpenVPX

VPX (VITA 46) is a new COTS board standard from the VITA standards body (www.vita.com). The members of VITA created VPX to address the need to connect high-speed fabrics such as Serial RapidIO® (sRIO), Gigabit Ethernet (GigE), PCI Express® (PCIe) and others between two or more 6U or 3U Eurocard modules, targeted for the military and aerospace (Mil/Aero) markets. OpenVPX is a system definition standard, created by an independent committee chartered to accelerate the VPX standard, with recommendations and specifications at the system level. It is now overseen by the VITA 65 working group. OpenVPX optimizes vendor interoperability by defining a process for module, backplane and chassis compatibility. The standard also specifies a set of development systems. This promises to eliminate the problem of individual specification groups writing “dot” specifications that would conflict with others. OpenVPX ensures that utility plane pin assignments will not interfere with mezzanine input and output (I/O), control plane pin assignments, or newer VITA specifications, making it easier for multiple board vendors to create interoperable modules and systems.

OpenVPX defines four profile types: slot, module, backplane and chassis. Because interoperability starts at the module level, the fundamental profile is the slot profile. The slot profile has basic definitions of planes (type, number, and size) and user-defined pins. A backplane profile defines how the slot profiles are connected. Chassis profiles add mechanical specifications, input power, and slot number to specify a chassis. Finally, the module profile defines how module vendors apply specific fabrics to the slot profiles, as well as definitions of fundamental module characteristics. Using these four OpenVPX profiles, integrators can incorporate different VPX vendor modules, backplanes, and chassis into a system.

Fabric Type for Planes

Volt Type

Management Bus

Air & Conduction-cooling Rules

PIN Definitions

Plane Sizes

Plane Options

User Defined PINs

RTM PINs

Slot Count

Module Pitch (HP)

Cooling Type

Power Provided

Chassis Manager

Pipe Mapping to PINs

Fabric Connection Requirements (transmit/receive)

Upstream/downstream

Slot-to-Slot Definitions

ModuleProfile

Chassis Profile

SlotProfile

Backplane Profile

Figure 5: OpenVPX Profiles

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Fundamental to this system definition approach is how pin connections are defined. In OpenVPX, a pipe comprises connections made up of differential pairs. For example, an Ultra-Thin Pipe (UTP) is two differential pairs or four connections on a VPX Multi-Gig connector. A Thin Pipe (TP) is four differential pairs and a Fat Pipe (FP) is eight differential pairs. FP grouping expands to Double Fat Pipe (DFP), Quad Fat Pipe (QFP), and Octa Fat Pipe (OFP) to describe the largest bandwidth plane needed.

The plane is the type of communication that uses pipes. For example, based on the profile definition, if a plane has 1.0 Generation PCIe fabric on an UTP this would equal one lane (x1) of PCIe at 2.5 Gigabits/s duplex. Alternatively, using Ethernet, UTP could be 1000Base-BX, TP would be 1000Base-T, and a FP would be 10 GBase-K4 or XAUI. In OpenVPX, planes are defined as interoperable data connections between modules.

Pipe Ultra Thin(UTP)

Thin(TP)

Fat(FP)

Double Fat(DFP)

Quad Fat(QFP)

Octa Fat(OFP)

Lane 1 2 4 8 16 32

Differential Pairs 2 4 8 16 32 64

Connections/Pins 4 8 16 32 64 128

Ethernet 1000 Base-BX 1000 Base-T 10G Base-K4 (XAUI) 2x 10GBase - -

PCIe x1 x2 x4 x8 x16 x32

PCIe Gen 1 (Gb/s) 2.5 5 10 20 40 80

PCIe Gen 2 (Gb/s) 5 10 20 40 80 160

Table 1: Pipe Definitions

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Planes and User I/O

OpenVPX also makes a distinction between planes and user-defined pins. Planes are wafer pins routed through the backplane to other wafer pins. For example, if a backplane topology calls for one FP routed to another slot, then that connection pipe is a plane (see Figure 6). User defined wafer pins connect through the backplane to the rear-transition module (RTM). There is no slot-to-slot connection of these pins. The VPX module developer could use these user-defined pins for any purpose without worrying about interoperability with other modules. Fabric connections that are not part of a plane have no connection to another slot or to the RTM. With this type of system-level specification, OpenVPX defines interoperability at the mechanical, module, and the backplane level.

Figure 6: Simple 3U 2-slot Example

For example, in Figure 7 a simple two-slot backplane is able to connect two boards with one DFP interconnect. A three-slot backplane can connect three VPX modules with slot 1’s FP A connected to slot 2’s FP A, and slot 1’s FP B connected to slot 3’s FP A.

Figure 7: 3U 2-slot and 3-slot Example

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One type of OpenVPX backplane profile is the 6U 16-slot backplane, which is shown in Figure 8. This 6U 16-slot profile exemplifies the expansion plane. Also shown is the utility plane, which contains a set of power, ground, and utility signals bussed between all of the slots. The control plane is where user applications would coordinate utility plane information between blades for reliability, availability, and serviceability functions. The data plane consists of the typical high-bandwidth, low latency pipes that are specified for large data movements at a system level. Based on which profile is specified, each one of these planes can be optimized for application requirements. Radar systems require low latency high-bandwidth connections at the data plane. Meshed and centrally switched architectures each have corresponding advantages and disadvantages, depending on what radar function will be instantiated by which COTS boards. However, beamforming can benefit by data streaming. The expansion bus maps this data streaming concept to OpenVPX.

Figure 8: 16-slot OpenVPXVPX

1

Expan.Plane

DataPlane

Ctl.Plane

IPMC

Dedicated x8 Connection with Adjacent SlotsLow-Latency

High-Bandwidth

Dedicated x4 Connection with

All SlotsMid-Latency

High-Bandwidth(some sensor

blocking)

Dedicated x1 Connection with

All SlotsHigh-Latency

High-Bandwidth

SerialInter-Connect

for IPMICLow-Latency

Low-Bandwidth

VPX2

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX3

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX4

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX5

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX6

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX7

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX8

DataSwitch

Ctl.Switch

ChMC

VPX9

DataSwitch

Ctl.Switch

ChMC

VPX10

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX11

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX12

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX13

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX14

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DataPlane

Ctl.Plane

IPMC

VPX15

Expan.Plane

DataPlane

Ctl.Plane

IPMC

VPX16

Expan.Plane

DataPlane

Ctl.Plane

IPMC

}

}

}

}

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Combining OpenVPX and COTS to Make DARs

The ideal method for improving the scalability, flexibility and expandability of radar systems is to use OpenVPX-based COTS boards. This approach ensures that the system designer can improve the radar’s digitization with the most advanced COTS board available at the time.

The following example employs COTS in a DAR system, using the Curtiss-Wright CHAMP-AV6 DSP engine, 5xx series FMC cards, an HPE720 card and a future sRIO switch card, all integrated in an OpenVPX chassis with the backplane profile shown in Figure 5. The CHAMP-AV6 is a COTS VPX board designed to comply with the OpenVPX standard. The CHAMP-AV6 has generous amounts of sRIO data plane bandwidth (four FP of sRIO capable of 1 GB/s duplex bandwidth) and DSP functionality (four Dual-core MPC8641 at 1 GHz or 64 GFLOPs).

Figure 9: CHAMP-AV6

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The HPE720, shown in Figure 10, is an FMC- (FPGA Mezzanine Card) enabled FPGA board with two Xilinx® Virtex®-5 FPGAs. While the HPE720 has similar data plane capability to the CHAMP-AV6, it adds an x8 RocketIO® expansion plane connection.

Figure 10: HPE720

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Curtiss-Wright also offers multiple FMC mezzanines which have ADC and DAC capability of one or two channels of 500 mega sample of analog data input or output.

To simplify the system concepts, the CHAMP-AV6 and HPE720 are broken down into fundamental dataflow diagrams.

Figure 11: CHAMP-AV6 Dataflow

Figure 12: HPE720 Dataflow

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Connecting two HPE720s via the expansion plane to beamform in a classic systolic system is shown below.

Figure 13: Connecting FPGA Resources in Systolic Fashion

Scaling this system with multiple TR elements could be achieved by interconnecting the HPE720’s sRIO to a central sRIO fabric switch. An example follows:

Figure 14: Four HPE720s Connected

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In this example, the systolic beamform is done in series, where the final digital beamform of the resultant beams is handled by the Power Architecture® processors connected to the HPE720s. If the processors on the HPE720 do not have sufficient processing capability, one or more CHAMP-AV6s can be added to the switched fabric to increase the processing capability.

Figure 15: Four HPE720s with One CHAMP-AV6

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Figure 16 shows a data flow diagram that a system designer could use to create an all digital beamformer.

Figure 16: Fully Parallel DBF Design

By combining these data flows into one or many chassis, the systems integrator can mix the various COTS boards for different levels of digitization. One of the key advantages of the COTS OpenVPX approach to building DARs is that these variant designs can be realized without changing the backplane. Even better, variant changes can be made without moving the boards to different locations, but rather by making a change in software in the processors and VHDL code in the FPGAs.

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Conclusion

The advent of OpenVPX and its flexible and scalable architecture now makes it possible for military system integrators to improve total cost of ownership (TCO) of radar systems, by using COTS open standard boards and chassis. Implementing ESA radar systems on this new system standard leverages the embedded community, eliminating the high cost of in-house designs or use of third-party proprietary system offerings. COTS-based OpenVPX systems meet most mission needs and offer a path to improved size, weight and power (SWaP) via simple module change. This leverages Moore’s law so that the same mission may improve with time by simply changing the type of spares used in the deployed system – enabling technology refresh by sparing. Furthermore, system designers can readily change mission requirements by reconfiguring data flow on these new modules to achieve higher levels of digitization. This makes it possible to improve mission capability over time without having to drastically change the system backplane. Therefore, TCO, SWaP-optimized technologies refresh and mission upgrade by sparing is now practical by deploying OpenVPX-based systems.

Works CitedMark Weber, J. C. (2005). Multi-Function Phased Array Radar for U.S. Civil-Sector Surveillance Needs. Retrieved from American Meteorological Society:http://ams.confex.com/ams/32Rad11Meso/techprogram/paper_96905.htmTarran, C. (2008). Advances in affordable Digital Array Radar. Retrieved 2010, from Roke Manor Research Limited, Papers:http://www.roke.co.uk/resources/papers/Advances_in_affordable_Digital_Array_Radar.pdf

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