high-level aging estimation for fpga-mapped designs xdl power file xdlrc file temperature per node...
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KIT – University of the State of Baden-Wuerttemberg and
National Research Center of the Helmholtz Association
Institute of Computer Science and Engineering – Chair of Dependable Nano Computing (CDNC)
www.kit.edu
High-Level Aging Estimation for FPGA-Mapped Designs
Abdulazim Amouri and Mehdi Tahoori
FPL 2012 Oslo, Norway
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
2
Purpose
Introduce a high-level yet device-level relevant aging estimation model
Suitable for FPGA architectures
Estimates the application information (usage)
In addition to device-level information
Build an FPGA aging estimation tool
Based on the high-level model
Infer the necessary information from the design tools of the FPGA
Can be used directly by FPGA users
Without the need for device-level details
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
3
Outline
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Motivation
Aging model abstraction
FPGA aging estimation tool
Experimental results
Conclusion
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
4
Outline
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Motivation
Aging model abstraction
FPGA aging estimation tool
Experimental results
Conclusion
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
5
FPGAs and Technology Scaling
Why scaling down The need for circuits that are:
High-performance, Low-power-consumption, Portable and Low cost
FPGAs are in the front line to benefit
High volume, regular, and high scalable structure
High performance demands for digital and mixed-mode analog circuits
Examples of state-of-the-art FPGAs:
Xilinx Virtex-7
28nm - based process technology
Up to 2M logic cells
600+ MHz operating frequency
However downscaling comes with reliability challenges
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Altera Stratix-V
28nm - based process technology
Up to 1.19M logic elements
600+ MHz operating frequency
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
6
Reliability challenges of downscaling: Aging
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
BTI: Bias Temperature Instability
Negative BTI (NBTI) affects PMOS
Positive BTI (PBTI) affects NMOS
Appears in high-κ / metal gate materials
HCI: Hot Carrier Injection
Main effects:
Increase the threshold voltage (Vth)
Decrease the carrier mobility
Slow the switching speed
The combination of these effects is
usually called (transistor aging)
Time
Fa
ilure
ra
te
BTI
HCI
Infant
Mortality Life time Wear-out
weeks years
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
7
Device-Level Aging Models
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Main factors affecting ∆Vth induced by BTI and HCI:
BTI: ∆Vth depends on
t : time (circuit age in seconds)
Y : duty cycle (the ratio of the stress time to the total time)
T : temperature (Kelvin)
HCI: ∆Vth depends on
t : time (circuit age in seconds)
α : activity (number of activations in one cycle)
f: operational frequency. The factor α x f is known as the activity rate (AR)
T: temperature (Kelvin)
[Noda 2010, Wang 2010]
[Bravaix 2009,Takeda 1983]
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
8
FPGA Users and Aging Estimation
FPGA users cannot use device-level aging models
Aging also depends on the mapped design, resource usage
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
FPGA Aging Model (BTI, HCI)
Application (Gate level netlist)
Physical Design (Which resources used
by mapping)
FPGA device information ( Circuit-level information of
slices, LUTs, …etc)
FPGA Lib info
Overall ∆delay after x years for the mapped circuit
Available Partially
available Vague
(mostly proprietary)
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
9
Outline
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Motivation
Aging model abstraction
FPGA aging estimation tool
Experimental results
Conclusion
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
10
Available information from the FPGA tools
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
All information is provided at node level
One node (black box circuit) can be
LUT
Slice flip flop
Routing path through switch matrices
…
Information include:
Delay of paths inside a node (Timing tool)
Node switching activity (Power tool)
Node dynamic power (Power tool)
User design (Gate level netlist)
FP
GA
mappin
g
Node
a
Node
b
Node
c
Node
d
Node
e
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
11
Different sub-circuits (nodes) in the FPGA
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Information is available at nodes’ input and output
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
12
Aging Model Abstraction (1)
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Each path through the node is represented by a chain of blocks
Each block contains an inverter
To consider the effect on both NMOS and PMOS type of transistors
Two adjustment steps:
First (emulate the delay)
# of blocks = path delay / delay of one block
The delay of one block depends on the technology node used
SPout SPi
Block0 Block1 Blockm-1
Pathi
Node
SP0
SP1
SPn
SPout
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
13
Aging Model Abstraction (2)
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
elsem
SPSPjSP
SPSPm
SPSPjSP
SPiout
i
iout
iout
i
j
,1
*
,1
*j= 1,2,…,m-1
SPout SPi
Block0 Block1 Blockm-1
Pathi
Node
SP0
SP1
SPn
SPout
Information is available at nodes’ input and output
Second (estimate internal details): linearization for estimating internal
Signal probability (SP) for BTI estimation, Y = 1-SP (NBTI) , Y = SP (PBTI)
Activity rate (AR) for HCI estimation
ARi ARout AR1 AR2 ARm-1
SP1 SP2 SPm-1
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
14
Outline
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Motivation
Aging model abstraction
FPGA aging estimation tool
Experimental results
Conclusion
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
15
FPGA Aging Estimation Tool: Overview
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Usag
e
Aging Estimation ( HCI , BTI )
Nodes Extraction
Timing
Report
1 . Paths
2 . Nodes
3 . Pre - aging
delays
Temperature Profile
Calculation
Power
Report XDL
file
XDLRC
file
Temperature
Per Node
Activity Rates Calculation
Power
Report
Activity
Rates
Signal Probabilities
Calculation
Logic
Simulation
( VCD file )
Signal
Probabilities
( Duty cycle )
1. Delay Degradation 2. Life time change
User Design
FPGA Tools
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
16
Temperature Profile Calculation (1)
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Floorplan generation
Die dimensions
Chip resources (XDLRC file)
X * Y number of tiles
Group each set of tiles in one blocks
Power trace
Using power report of the design
Needs activity file from logic
simulator
Dynamic power
Find physical location for each
component
Assign component’s power to
respective blocks
Leakage power
Given as one value for whole FPGA HotSpot
Chip
Resources
(XDLRC file)
Floorplan Creation
0 1 2 ...
k
...
...
Block i =
n x m Tiles
Die
Dimensions Power
Report
Circuit
Description
(XDL file)
Power Distribution
Block Power
Power Extraction
Node Power Leakage
Power
Dynamic
Power
0 1 2
k
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
17
Temperature Profile Calculation (2)
Leakage Power
Equaly-distributed
Not accurate (thermal camera)
Leakage Distribution Model
Based on leakage-temperature loop
Original leakage redistributed
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
HotSpot
Temperature Distribution Model
Block Power 0 1 2
k
Block Temp . 0 1 2
k
Original
Leakage
XDL
File
XDLRC
File
Node Temp. 0 1 2
k
Per-node Temperature Calculation
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
18
FPGA Aging Estimation Tool: Overview
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Usag
e
Aging Estimation ( HCI , BTI )
Nodes Extraction
Timing
Report
1 . Paths
2 . Nodes
3 . Pre - aging
delays
Temperature Profile
Calculation
Power
Report XDL
file
XDLRC
file
Temperature
Per Node
Activity Rates Calculation
Power
Report
Activity
Rates
Signal Probabilities
Calculation
Logic
Simulation
( VCD file )
Signal
Probabilities
( Duty cycle )
1. Delay Degradation 2. Life time change
User Design
FPGA Tools
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
19
Aging Estimation
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Finding the amount of change in node’s delay due
to aging (Δdnode(BTI) and Δdnode(HCI) )
Calculating, for each node, the new delay due to
aging (d0node + Δdnode)
Finding the aged-circuit critical path’s delay
(d~critical), and compare it to the fresh-circuit critical
path’s delay (dcritical)
The performance degradation due to aging
Step 1
Step 2
Step 3
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
20
Outline
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Motivation
Aging model abstraction
FPGA aging estimation tool
Experimental results
Validation of the proposed abstraction
Validation of the thermal model
Tool usage: Case Study
Conclusion
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
21
Validation of the Proposed Abstraction
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
HSPICE simulation
Abstracted model
HSPICE simulation for different types of node
More than 90% match in the trend
Example 2-input LUT:
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
22
Outline
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Motivation
Aging model abstraction
FPGA aging estimation tool
Experimental results
Validation of the proposed abstraction
Validation of the thermal model
Tool usage: Case Study
Conclusion
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
23
Thermal Model Validation (1)
A thermal (infrared) camera is used
Accuracy ±1 °C
Attached to Virtex-5 vlx110t FPGA
After removing the packaging (no heatsink, no heatspreader)
Two circuits under test:
8-bit FIR filter at 150 MHz
128-bit AES encoder at 300 MHz
Do a comparison between:
The Thermal Model and
The Thermal Camera
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
24
Thermal Model Validation (2)
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
AES
Encoder
FIR
Filter
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
25
Outline
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Motivation
Aging model abstraction
FPGA aging estimation tool
Experimental results
Validation of the proposed abstraction
Validation of the thermal model
Tool usage: Case Study
Conclusion
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
26
Case Study: Influence of Mapping and
Optimization Algorithms (1)
Three cases:
(1) Area optimization, (2) Speed optimization
(3) Force placement with speed optimization
Different ITC’99 test bench circuits in addition to an FIR filter
Virtex6-vlx75t (fit all the circuits)
Mapped only to LUTs and flip-flops for fair comparison
10000 vectors are tested for each experiment to calculate
Signal Probabilities (SP), Signal Activities (AR)
Worst case NBTI and HCI is set
For SP = 1 (PMOS transistors always ON worst case NBTI)
For AR = 500 MHz (maximum frequency worst case HCI)
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
27
Case Study: Influence of Mapping and
Optimization Algorithms (2)
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
0%
5%
10%
15%
b04b05b11b12b14FIR Filter
No
rmalized
∆Delay
NBTI
0%
5%
10%
15%
b04b05b11b12b14FIR Filter
No
rmalized
∆Delay
HCI
Speed optimized Forced placement Area optimized
Worst
Case
Worst
Case
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
28
Lifetime Enhancement
A small change in the degradation rate has a significant effect on the
lifetime
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
29
Lifetime Enhancement Compared to Worst Case
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
0%
100%
200%
300%
b04b05b11b12b14FIR Filter
No
rmalized
L
ifeti
me
NBTI
0%
100%
200%
300%
b04b05b11b12b14FIR Filter
No
rmalized
L
ifeti
me
HCI
Speed optimized Forced placement Area optimized
10x
Worst Case
Worst Case
2x
3x
2x
3x
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
30
Outline
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Motivation
Aging model abstraction
FPGA aging estimation tool
Experimental results
Validation of the proposed abstraction
Validation of the thermal model
Tool usage: Case Study
Conclusion
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
31
Conclusion
Transistor aging is a major reliability issue. Mainly due to
Bias Temperature Instability (BTI)
Hot Carrier Injection (HCI)
Accurate aging estimation requires
Device info, used resources (mapping), and user application (workload)
Developed an FPGA aging estimation tool
Can be used directly by FPGA end-users
Infers device info from FPGA reports (timing, power, etc.)
Considers mapping and user application
Aging of FPGA depends on:
(1) The target FPGA chip (2) the application and (3) how it is mapped
Abdulazim Amouri – High-Level Aging Estimation for FPGA-Mapped Designs 13.09.2012
Chair of Dependable Nano Computing (CDNC)
Institute of Computer Science and Engineering
32
References
[Noda 2010]: M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, and Y. Miura, “On
estimation of NBTI-induced delay degradation,” in Test Symposium (ETS), 2010 15th
IEEE European, May 2010, pp. 107 –111.
[Wang 2010]: W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, and Y. Cao, “The
impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis,” Very
Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, no. 2, pp. 173 –
183, 2010.
[Takeda 1983]: E. Takeda and N. Suzuki, “An empirical model for device degradation due
to hot-carrier injection,” Electron Device Letters, IEEE, vol. 4, no. 4, pp. 111 – 113, Apr.
1983.
[Bravaix 2009]: A. Bravaix, C. Guerin, V. Huard, D. Roy, J. Roux, and E. Vincent, “Hot-
carrier acceleration factors for low power management in dc-ac stressed 40nm nmos
node at high temperature,” in Reliability Physics Symposium, 2009 IEEE International.
IEEE, 2009, pp. 531–548.
[Kiamehr FPT 2012]: S. Kiamehr, A. Amouri, and M. Tahoori, “Investigation of NBTI and
PBTI induced aging in different LUT implementations,” in Field-Programmable
Technology (FPT), 2011 International Conference on. IEEE, 2011, pp. 1–8.
Abdulazim Amouri – Reliable Reconfigurable Systems 13.09.2012