high efficiency ibc solar cell with oxide-nitride-oxide passivation · 2019. 12. 20. · teng choon...
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High efficiency IBC solar cell
with Oxide-Nitride-Oxide passivation
Teng Choon Kho
August 2019
A thesis submitted for the degree of Doctor of Philosophy
of the Australian National University
I certify that this thesis does not incorporate without acknowledgement any material submitted
for a degree or diploma in any university and that, to the best of my knowledge, it does not
contain any material previously published or written by another person except where due
reference is made in the text. The work in this thesis is my own, except for the contributions
made by others as described in the Acknowledgements.
Declaration
I would like to express my deepest gratitude to all my supervisors who they possess one the
brightest minds in solar, Prof. Andrew Blakers, Dr Kean Fong, Dr Matthew Stocks and Dr
Evan Franklin. They mentored and provided me with the opportunity to explore, learn and
fabricate high-efficiency silicon solar cells.
I would also like to express my undying appreciation and respect to rock star mentor Dr Keith
McIntosh, who initially inspired me in research way back in 2008. I’m humbled by his
knowledge and willingness to guide me in many different aspects of life.
I’m privileged to have been able to work with others within the department. I’m thankful to
have constant impromptu discussions Prof. Dan MacDonald and Prof. Andres Cuevas. The
laboratory wouldn’t be operational without the support from Christian Samundsett, Nina De
Caritat, Mark Saunders, James Cotsell, Bruce Condon, Maureen Brauers.
I would like to further thank Dr Fouad Karouta and Dr Kaushal Vora for allowing and assisting
me in using the equipment at the ANFF ACT Nodes.
The journey of completing this thesis would not be completed without thanking the ridiculous
jolly group of friends, Dr Pheng Phang, Dr Er-Chien Wang, Dr Kelvin Sio, Dr Di Yan, Dr
James Bullock, Dr Teck Kong, Dr Chog Barugkin, Dr Tom Ratcliff, Ingrid Haedrich, Dr Soe
Zin and Dr Nicholas Grant.
I would like to thank my immediate and extended family member and friends for supporting
me. To my papa and mama, both my sisters Sue Ann and Jey Vonn, three of my childhood
friends in Malaysia (Chung Lern Lee, Kim Zen Fang and Hui Ni Tan) and especially my
dependable wife Swee Wah Yap, who she had to endure and supported me throughout this.
This thesis has been externally reviewed by The Expert Editors following the Australian
standards for editing practice.
Acknowledgements
Symbol Description
Al Aluminium
Al2O3 Aluminium oxide
ALD Atomic layer deposition
Alneal FGA with presence of aluminium
ANU The Australian National University
ARC Anti-reflection coating
BBr3 Boron tribromide
BSF Back surface field
BSG Boronsilicate glass
CC Corona charge
CSIRO Commonwealth Scientific and Research Organisation
C-V Capacitance-voltage
Cz Czochralski
DLTS Deep-level transient spectroscopy
Eq Equation
EQE External quantum efficiency
ESR Electron spin resonance
FCA Free carrier absorption
FGA Forming Gas annealing
FSF Front surface field
FZ Float Zone
g value Lande Splitting factor
HF Hydrofluoric acid
HMDS Hexamethyldisilazane
IBC Interdigitated back contact
IQE Internal quantum efficiency
I-V Current-voltage
LPCVD Low pressure chemical vapour deposition
m Local ideality factor
N/Si Nitrogen/silicon ratio
ONO SiO2-SiNx-SiOx dielectric stack
PECVD Plasma enhanced chemical vapour deposition
PL Photoluminescence
POA Post-oxidation annealing
List of abbreviations
POCl3 Phosphoryl chloride
PSG Phosphosilicate glass
PV Photovoltaics
Rantex Random texture
RCA Radio Chemical America
Si3N4 Silicon nitride
SiNx Amorphous silicon nitride
SiO2 Thermal silicon oxide
SiOx Amorphous silicon oxide
TMA Trimethylaluminum
TMAH Tetramethylammonium hydroxide
TOPcon Tunnel oxide passivated contact
Symbol Description Unit
capture cross section of electrons cm2
capture cross section of holes cm2
µn Mobility of electron cm2/Vs
µp Mobility of holes cm2/Vs
Dit Interface states density eV-1.cm-2
EC Energy level of conduction band eV
EV Energy level of valance band eV
FF Fill factor %
fO Recombination ratio between 111 to 100 orientation
fV Recombination ratio between area corrected rantex to 111 orientation
G Photogeneration rate m-3
J0 Saturation current fA/cm2
J0e Emitter saturation current fA/cm2
J0s Surface saturation current fA/cm2
Jsc Short circuit current mA/cm2
k Extinction coefficient
kT Boltzmann constant (k) with temperature in kelvin eV
LD Debye length m
n Refractive index
n Electron concentration cm-3
n0 Thermal equilibrium of electron density cm-3
NA Acceptor dopants in substrate cm-3
NC Effective densities of states in the conduction band cm-3
ND Donor dopants in substrate cm-3
ni Intrinsic carrier concentration cm-3
NV Effective densities of states in the valance band cm-3
nλ Refractive index at λ
nλ Refractive index at define wavelength
p Holes concentration cm-3
p0 Thermal equilibrium of hole density cm-3
Qeff Effective charge cm-2
Qox Charges in oxide cm-2
Rseries Series resistance Ω/cm2
List of symbols
Rshunt Shunt resistance Ω/cm2
Seff Effective surface recombination velocity cm/s
Seff.UL Upper limit of effective surface recombination velocity, assuming infinite bulk
lifetime
cm/s
VFB Flatband voltage V
Voc Open circuit voltage mV
w Thickness of substrate µm
α Absorption coefficient cm-1
∆n Excess carrier density cm-3
σ Conductivity S/m
τbulk Effective lifetime of bulk s
τeff Effective lifetime s
τeff.max Maximum effective lifetime across measured injection level s
τeff_1015 Effective lifetime at injection level of 1015 cm-3 s
τSRH Shockley-Read-Hall lifetime S
τsurface Effective lifetime of surface S
Abstract
This thesis considers the optimisation of an SiO2-SiNx-SiOx (ONO) dielectric coating for
silicon solar cells comprising thermal SiO2, plasma-enhanced chemical vapour deposition
PECVD SiNx and SiOx, together with the development and fabrication of high efficiency
interdigitated back contact (IBC) silicon solar cells.
The three-layer ONO dielectric stack provides excellent surface passivation and anti-reflection
properties. The initial thermal SiO2 layer provides chemical surface passivation. The second
layer of the PECVD SiNx hydrogenates the underlying thermal SiO2 and provides a field-effect
passivation with positive charges. The third layer of the PECVD SiOx improves the overall
anti-reflection coating (ARC) of an ONO stack in air. Positive corona charging of the ONO
stack further improves the surface passivation, and annealing at 400 ˚C traps the charges and
renders it stable for at least two years. An optimised ONO stack for surface passivation for
crystalline silicon has achieved effective lifetimes above previous parameterised Auger limits.
The n-type wafers with resistivities of 0.5, 1.07, 1.77 and 100 Ω.cm achieved lifetimes of 3.7,
15.1, 25.5 and 170 ms, respectively.
The surface passivation of an ONO stack was fine-tuned for both phosphorus and boron
diffusions for integration into IBC silicon solar cells. A large contribution of positive charges
within the stack was mainly from the thermal SiO2 and PECVD SiNx. Post-oxidation annealing
(POA) of the thermal SiO2 and high SiNx refractive index reduced the overall positive charge
of the ONO stack. A lower positive charge improved the passivation on the boron diffused
surface while retaining excellent passivation on the phosphorus diffused surface.
The cell design and fabrication processes for IBC silicon solar cells were improved from
previous fabrication processes at the Australian National University (ANU) by utilising ONO
surface passivation. The refinement for IBC silicon solar cell design was based on detailed
simulations. The improvements to the cell processing included permanently eliminating low
bulk lifetime defects on high resistivity n-type float zone (FZ) wafers, gettering of
contaminants, and consistent texturing results. Implementing optimised ONO stacks for surface
passivation and an ARC onto the IBC silicon solar cell achieved a certified efficiency of 25.0
± 0.6%. Non-ideal recombination contributed to a relatively low fill factor for the champion
cell, and disregarding the non-ideal recombination in the simulation results revealed that an
efficiency of 25.2% is achievable.
Contents
1. Introduction .................................................................................................................. 1
1.1 Motivation ........................................................................................................... 1
1.2 Outline and highlights ......................................................................................... 2
2. Review of surface passivation ..................................................................................... 5
2.1 Introduction ....................................................................................................... 5
2.2 Thermal silicon oxide ......................................................................................... 6
2.2.1 Thermal oxide charges ........................................................................... 8
2.2.2 Growth and optical properties of thermal oxide .................................... 9
2.2.3 Surface passivation of thermal oxide ..................................................... 9
2.3 Plasma-enhanced chemical vapour deposition of silicon nitride ..................... 10
2.3.1 PECVD silicon nitride charges ............................................................ 12
2.3.2 Optics of PECVD silicon nitride.......................................................... 13
2.3.3 Surface passivation of PECVD silicon nitride ..................................... 14
2.4 Atomic layer deposition of aluminium oxide .................................................. 15
2.4.1 ALD aluminium oxide charges ............................................................ 16
2.4.2 Optics of ALD aluminium oxide ......................................................... 16
2.4.3 Surface passivation of ALD aluminium oxide..................................... 17
2.5 Doped polysilicon passivated contacts ............................................................ 17
2.5.1 Optics of polysilicon ............................................................................ 18
2.5.2 Passivation and contact resistivity of doped polysilicon ..................... 18
2.6 Electret ............................................................................................................. 19
2.6.1 Corona charging of silicon oxide and silicon nitride electret .............. 20
2.6.2 Surface passivation of corona charged silicon oxide ........................... 21
2.7 Chapter summary ............................................................................................. 22
3. Characterisation methods ......................................................................................... 24
3.1 Photoconductance measurement and recombination mechanism in solar cell . 24
3.1.1 Bulk recombination .............................................................................. 25
3.1.2 Surface recombination ......................................................................... 27
3.1.3 Emitter recombination model .............................................................. 28
3.2 Capacitance-voltage measurement.................................................................... 29
3.3 Current-voltage measurement ........................................................................... 31
4. ONO: Growth and deposition conditions ................................................................ 35
4.1 Introduction ..................................................................................................... 35
4.2 ONO baseline procedure ................................................................................... 35
4.3 Thermal oxide growth conditions for an ONO stack ........................................ 36
4.3.1 The effect of varying the thermal oxide thickness ............................... 37
4.3.2 The effect of post-oxidation annealing of thermal oxide ..................... 39
4.4 Deposition conditions of PECVD for ONO stack ............................................ 41
4.4.1 PECVD dielectric stack on thermal oxide ........................................... 45
4.4.2 Deposition conditions of PECVD SiNx in ONO stack ........................ 47
4.4.3 Deposition conditions of PECVD SiOx in ONO stack ....................... 56
4.5 Impact of corona charging and annealing on ONO stack ................................. 59
4.6 ONO surface passivation on various wafer resistivities and surfaces .............. 62
4.7 Chapter summary .............................................................................................. 64
5. Passivation of ONO on diffused surfaces ................................................................. 66
5.1 Introduction ..................................................................................................... 66
5.2 ONO baseline procedure on diffused surfaces .................................................. 66
5.3 Surface passivation of ONO stack on phosphorus and boron diffusion ........... 67
5.4 Thermal oxide growth conditions in an ONO stack on diffused surfaces ........ 69
5.4.1 The effect of varying thermal oxide thickness on diffused surfaces ... 70
5.4.2 The effect of post-oxidation annealing of thermal oxide on diffused
surface .................................................................................................. 73
5.5 Deposition conditions for PECVD SiNx of the ONO stack on diffused surfaces
........................................................................................................................... 76
5.6 Impact of corona charging and annealing on diffused surfaces with ONO stack
........................................................................................................................... 79
5.7 Chapter summary .............................................................................................. 81
6. Simulation of ONO IBC solar cells .......................................................................... 83
6.1 Introduction ....................................................................................................... 83
6.2 Optical losses .................................................................................................... 83
6.2.1 OPAL2 simulation inputs .................................................................... 84
6.2.2 Simulation of ONO with OPAL2 ........................................................ 87
6.2.3 Free carrier absorption ......................................................................... 90
6.2.4 Simulation of FCA with SunSolve ...................................................... 91
6.3 Recombination losses of ONO IBC solar cell .................................................. 92
6.3.1 Simulation for front and rear surface recombinations with phosphorus
surface field .......................................................................................... 94
6.3.2 Simulation for rear boron-doped emitter ............................................. 99
6.3.3 Simulation for rear phosphorus-doped contact region ....................... 101
6.3.4 Simulation of different pitch sizes for the ONO IBC solar cell ......... 102
6.3.5 Simulation of bulk lifetime, resistivity and edge recombination ....... 104
6.3.6 Simulation of series and shunt resistance .......................................... 106
6.4 Chapter summary ............................................................................................ 109
7. Fabrication and analysis of ONO IBC solar cells ................................................. 110
7.1 Introduction ..................................................................................................... 110
7.2 Fabrication sequence ....................................................................................... 110
7.2.1 Chemical cleaning .............................................................................. 111
7.2.2 Pre-oxidation of wafers ...................................................................... 113
7.2.3 Gettering ............................................................................................ 114
7.2.4 Masking layer..................................................................................... 115
7.2.5 Photolithography pattering................................................................. 116
7.2.6 Diffusion process ............................................................................... 117
7.2.7 Texturing ............................................................................................ 118
7.2.8 Metal contact and fingers patterning .................................................. 120
7.3 Improvements to the ONO IBC solar cells fabrication process ...................... 121
7.3.1 Boron-rich layer gettering .................................................................. 121
7.3.2 Surface passivation on IBC solar cell ................................................ 124
7.3.3 Positive corona charging on the front surface of ONO IBC solar cells
............................................................................................................ 132
7.3.4 Lift-off metallisation on ONO IBC solar cell .................................... 138
7.4 ONO IBC cell with certified conversion efficiency of 25% ........................... 144
7.5 Chapter summary ............................................................................................ 147
8. Conclusion ................................................................................................................ 148
Appendix ......................................................................................................................... 152
List of publication .......................................................................................................... 158
Bibliography ......................................................................................................................... 159
1
Chapter 1
1.1 Motivation
Photovoltaics have been growing exponentially for more than the last quarter century [1]. There
has been significant growth over the last decade worldwide, with China leading the way. This
growth was accelerated by government policies and incentives to increase reliability and reduce
the costs of renewable energy.
Advancements in manufacturing processes have drastically reduced the costs of photovoltaics
(PV) [2]. As of 2017, silicon wafer-based technologies accounted for 95% of the total PV
industry [3]. The improved efficiency of silicon solar cells leverages cost reductions across the
entire PV value chain.
1980 1990 2000 20100
10
20
30
40
50
60
70
80
US
D p
er
wa
tt (
$/W
)
Year
Fig 1.1: (a) Global growth of PV capacity with regional shares [4-8]. (b) Price in USD per watt of crystalline-silicon modules [9, 10].
Interdigitated back contact (IBC) solar cells are capable of achieving high efficiencies.
Traditional front contact cells reflect a portion of light from the front contact metallised fingers
and busbar, whereas IBC solar cells avoid shading losses by having all the contacts at the rear.
The highest efficiency IBC silicon solar cell reported to date of a single crystal and
0
100
200
300
400
500
600
0
100
200
300
400
500
600
2012 2013 2014 2015 2016 2017 2018
Glo
bal g
row
th o
f cum
ula
tive
PV
(G
W)
Year
Others
China
APAC
America
Europe
2018 Global Estimate
Introduction
$76.67
(1977)
$0.30 (2015)
(a) (b)
2
heterojunction structure under one sun are 26.1% (cell area size of 4 cm2) [11, 12] and 26.6%
(cell area of 79 cm2) respectively [12, 13].
The highest independently certified efficiency for an IBC solar cell fabricated at the Australian
National University (ANU) prior to this work was 24.4% (cell area size of 4 cm2), with an open
circuit voltage (Voc) of 703 ± 3.5 mV, a short circuit current (Jsc) of 42 ± 1 mA/cm2 and a fill
factor (FF) of 82.7 ± 0.8% [14]. The cell was fabricated from a moderate-resistivity (1 Ω.cm)
n-type wafer, with a sheet boron emitter, localized phosphorus contact dots, front surface
passivation with PECVD SiNx-SiOx stack and rear surface passivation from a thermal SiO2 and
LPCVD Si3N4 stack.
Developing a high-efficiency IBC solar cell requires a high bulk lifetime, excellent surface
passivation, low contact recombination, low contact resistivity, optimised emitter collection
geometry, an excellent anti-reflection coating (ARC) and, ideally, minimal edge recombination
losses [13-15]. This thesis presents the development of excellent surface passivation and ARC
using a thermal SiO2 and PECVD SiNx-SiOx (ONO) stack integrated into IBC solar cells. The
surface passivation of the ONO was studied on both undiffused and diffused surfaces. The data
obtained for the ONO surface passivation was modelled and simulated with the simulation
package Quokka3 [16]. The cell design was based on the simulation results and the fabrication
sequence of the IBC solar cell was established from a previous ANU IBC process with
additional refinements to maintain a high bulk lifetime and achieve repeatable uniform random
texturing (rantex) processes [14]. The champion cell in this work achieved an independently
certified efficiency of 25.0 ± 0.6%, with a Voc of 717 ± 1 mV, a Jsc of 42.9 ± 0.8 mA/cm2 and
a FF of 81.1 ± 1.9%, setting a new ANU record for a single crystal silicon solar cell.
1.2 Outline and highlights
Chapter 2 reviews the various surface passivation methods commonly used in silicon solar cells.
Each of the reviewed surface passivation techniques is discussed in detail with respect to the
chemical bonding, dielectric charges and optical properties. The thermal SiO2, PECVD SiNx,
and atomic layer deposition (ALD) Al2O3 surface passivation dielectrics were evaluated and
compared with optimised surface passivations achieved at ANU.
3
Chapter 3 introduces the measurement techniques used to calculate and measure the surface
recombination and effective lifetime, charge density in dielectrics, cell efficiency and shunt
and series resistances.
Chapter 4 presents an extensive study of the ONO structure, which consists of a thermal SiO2,
PECVD SiNx and PECVD SiOx stack. The dependence of the dielectric stack on the growth
conditions were systematically investigated on an undiffused planar and rantex surface of n-
type high resistivity (100 Ω.cm) wafers. The effects of the growth conditions of the thermal
SiO2 on the ONO surface passivation were explored with different thermal SiO2 thicknesses
and post-oxidation annealing (POA) with N2. The deposition conditions for the SiNx were
investigated, including the deposition temperature, SiH4 and NH3 gas flow ratio and chamber
pressure. The deposition conditions for the PECVD SiOx layer were investigated by varying
the deposition temperature and gas ratio. The surface passivation of the ONO stack was further
enhanced using corona charging and annealing to improve the charge stability. Based on these
studies, the fine-tuned ONO dielectric stack achieved lifetimes above the parameterised Auger
limits on n-type 0.50, 1.07 and 1.50 Ω.cm wafers [17].
Chapter 5 reviews the ONO structure on diffused surfaces. The dependence of the thermal SiO2
and PECVD SiNx deposition conditions were investigated on boron and phosphorus diffused
planar wafers as well as on phosphorus-diffused rantex wafers. The growth conditions were
varied for the thermal SiO2 layer, including the thermal SiO2 thickness and the duration of the
POA in N2. The deposition conditions for the PECVD SiNx were varied with different SiH4
and NH3 gas flow ratios. The ONO provides excellent chemical surface passivation and
achieved a J0e of 0.5 fA/cm2 and 1.9 fA/cm2 on a light phosphorus diffused planar (520 Ω/)
and rantex surface (610 Ω/) respectively, and 4.8 fA/cm2 on the light boron diffused planar
surface (154 Ω/) after corona charging.
Chapter 6 investigates the different losses for an IBC solar cell using the simulation package
Quokka3, the optical simulator OPAL2, the emitter modelling EDNA2 and the ray tracer
simulator SunSolve [16, 18, 19]. The optical simulation included varying the thicknesses of the
thermal SiO2, PECVD SiNx and SiOx. The device simulation conditions included the surface,
bulk and emitter recombination, various optical losses, contact resistivity, series and shunt
resistances and edge recombination. The obtained simulated results were applied to the cell
fabrication process.
4
Chapter 7 employs the simulation results from Chapter 6 in the IBC solar cell design while
considering fabrication limitations. The fabrication process was improved from the previous
ANU IBC process by introducing boron rich layer (BRL) gettering and improving the texturing
consistency [14]. Three different aspects of IBC solar cells were investigated: surface
passivation, corona charging and annealing and rear metallisation of the cell.
Chapter 8 summarises the key finding from each chapter.
5
Chapter 2
Review of surface passivation
2.1 Introduction
Surface recombination remains one of the limiting factors in developing high-efficiency solar
cells. Termination of bonds at the surface of the atomic lattice of a semiconductor causes highly
active recombination sites for electron and hole carriers. The termination of bonds which are
left unbound to any other bonds are known as ‘dangling bonds,’ and the recombination sites at
the surface are commonly referred to as either ‘surface’ or ‘interface’ states. These dangling
bonds allow the recombination of generated carriers within the semiconductor, which reduces
the solar cell efficiency.
In PV, surface passivation is defined as a reduction of recombination events at the surface.
There are two common ways to achieve surface passivation: i) reducing the dangling bonds on
the surface (chemical passivation), and ii) reducing the carrier concentration of one type
(electrons or holes) of free charge carriers at the surface (field-effect passivation).
The ideal chemical surface passivation would be to have chemical bonding at all the surface
dangling bonds of the semiconductor to deactivate the surface recombination sites. Chemical
passivation can be achieved by establishing covalent bonding onto the surface. Dielectric
materials with a bandgap larger than the semiconductor are generally used for surface
passivation, such as thermal SiO2 on silicon. However, due to lattice mismatch of dielectrics
and semiconductors, not all of the dangling bonds are passivated. These additional
unpassivated dangling bonds can be further reduced by subjecting them to additional hydrogen
at the interface using a forming gas annealing (FGA) or hydrogen plasma process.
Field-effect passivation can be achieved by either introducing an external field to repel specific
carriers or doping to limit the recombination of specific carriers at the surface. The
conventional method of creating field-effect passivation is to dope the near-surface regions
with dopants such as phosphorus, boron or Al. The diffused region creates an electric field and
chemical potential within the semiconductor to suppress specific carrier recombination at the
surface [20]. Alternatively, an electric field can be attained by depositing a dielectric layer with
inbuilt charges or charges deposited onto the dielectric surfaces through corona charging. With
6
sufficient charges, the surface recombination can be reduced by either accumulation or
inversion of the carriers at the surface of an undiffused wafer.
Incorporating both these passivation mechanisms (chemical and field-effect passivation)
simultaneously can significantly reduce surface recombination. Dielectrics such as Al2O3 and
SiNx have been shown to provide both excellent chemical and field-effect passivation with
effective surface recombination velocity (Seff) of <1 cm/s [21].
In the following sections, the growth conditions, characterised defects, optical properties and
chemical and field-effect passivation of the dielectric layers are reviewed.
2.2 Thermal silicon oxide
Thermal oxidation has long been regarded as a reliable passivation method in both the
electronics and PV industries. Atalla et al. in the late 1950s were the first to report surface
passivation with thermal SiO2 on p-n junction diodes [22]. Progressive improvements of silicon
semiconductor materials similarly improved the understanding of silicon PV. By late 1970, the
first silicon solar cells passivated with thermal SiO2 achieved efficiencies of nearly 17%, and
by mid-1980s, Blakers et al. managed to develop a solar cell with an efficiency of 20% by
passivating the cell via thermal oxidation [23, 24].
Thermal SiO2 is normally grown in high-temperature quartz furnaces, from 600 to 1100 C [25,
26], in the presence of O2 or steam. Oxygen atoms diffuse through the silicon lattice and
chemically react at the silicon surface to form thermal SiO2. With steam, the oxide growth is
five to ten times faster due to the formation of hydroxide ions (OH-) from the water, which
diffuses faster through the oxide layer as compared with O2 [27, 28]. POA is normally
performed after oxidation with an inert gas (N2 or Ar) at temperatures between 950 and 1200 °C
to reduce charges within the oxide [29, 30].
Thermally grown SiO2 structures are generally assumed to be amorphous [31, 32]. However,
Takahashi et al. and Munkholm et al. have shown that the SiO2 could maintain an epitaxial
relation with the silicon substrate on 001 wafers [33, 34]. During thermal oxidation,
differences in the bond lengths of the crystalline silicon and thermal SiO2 induce stresses at the
Si-SiO2 interface. The local relaxation of the stress at the interface may cause dangling bond
defects that are defined as Pb centres [35-40], which are commonly characterised via electron
spin resonance (ESR). Early work by Poindexter et al. described single defect as Pb on a 111
7
orientated wafer with dangling bonds as an sp3[111] hybrid (ᵒSi≡Si3) [41]. Poindexter et al. later
reported a 100 oriented wafer that exhibited two defect types, defined as Pb0 and Pb1 [41].
Although the Pb and Pb0 defects were reported to be nearly identical, there is still ambiguity
around the Pb1 defect [36]. Stesmans et al. suggested that the Pb1 defect is electrically inactive
[42]; however, Campbell et al. reported that the defect was active within the silicon bandgap
[43]. It has been observed from various studies that the Pb centres of 100 orientation are
smaller compared with the 111 orientated wafer [41, 42, 44]. Studies regarding these Pb
centres with ESR can be further correlated to interface state densities.
Interface traps due to dangling bonds that lie between the semiconductor and the passivating
dielectric can be quantified in terms of the interface states densities (Dit). The Dit for Si-SiO2
was first reported by Terman in the early 1960s using a metal oxide silicon (MOS) structure
with capacitance-voltage (C-V) measurements [45]. The measured Pb centres and Dit for
different levels of wafer doping, orientation and resistivity from various publications are
plotted in Figure 2.1 [46-48]. It is observed that the overall measured Pb centre densities are
correlated relatively linearly with Dit. Similarly, 100 wafers were reported to have a lower
Dit compared with 111 orientated wafers at the Si-SiO2 interface [49]. The introduction of
FGA, which is normally a mixture of 5% H2 and 95% N2 or Ar at temperatures from 400–
450 °C, has been shown to reduce active Pb centres and similarly lower the midgap Dit [30, 50-
52].
0 5 10 15 20 25 300
5
10
15
20
25
30
Mikawa et al. P 111 N
2
Yong et al. N 100 N
2
Poindexter et al. N 111 N
2
P 100 N2
P 111 N2
P 100 O2
P 111 O2
N 100 O2
N 111 O2
N 111 FGA
Pb s
pin
con
cen
tratio
n (
10
11/c
m2)
Midgap Dit (1011
/eV.cm2)
Fig 2.1: Correlation between the Pb defects and the interface state densities with different wafer orientations, doping and annealing processes [46-48].
8
2.2.1 Thermal oxide charges
It has been known since 1970 that thermal SiO2 introduces fixed positive charges at the Si-
SiO2 interface [53]. After nearly half a century, the origin and nature of these charges remain
debated [54-56]. Thermal SiO2 has been observed to contain mostly positive charges, which
can be classified as mobile ion charges, fixed oxide charges, trapped oxide charges or interface
charges. The formation of these charges is dependent on the oxidation temperature, wafer
orientation, POA and ion contamination species [30, 53, 55, 56]. The work performed by Cheng
et al. (plotted in Figure 2.2a) shows that the charges within the oxide reduce as the oxidation
temperature increases [53]. Moreover, Deal et al. and Razouk et al. reported that thermally
grown SiO2 on 111 orientated wafers has more positive charges within the thermal SiO2 as
compared with 100 orientated wafers [30, 56]. Further studies performed by Razouk et al.
concluded that thermal SiO2 not subjected to any POA with N2 and Ar has slightly more
positive charges [30]. Furthermore, Lamb et al. revealed that annealing in inert gases at
temperatures up to 1200 °C reduces the positive oxide charges, as plotted in Figure 2.2b [53,
57].
400 600 800 1000 1200 1400
2
4
6
8
10
12
600 800 1000 1200 1400
5
10
15
20
SiO
2 Q
eff (1
011 c
m-2)
Oxidation Temperature (°C)
Dry P 1.1 Ω.cm
Dry N 0.4 Ω.cm
Wet P 1.1 Ω.cm
Wet N 0.4 Ω.cm
(a) (b)
Annealing Gas
He
Ar
N2
SiO
2 Q
eff (
10
11 c
m-2)
Annealing Temperature (°C) Fig 2.2: (a) SiO2 charges with different oxidation temperatures for dry and wet oxidation [53]. (b) Correlation of thermal SiO2 charges with post-annealing temperatures of the inert gases [53, 57].
2.2.2 Growth and optical properties of thermal oxide
The growth of thermal SiO2 on a wafer depends on various factors including the furnace
temperature, pressure, gasses, humidity, the orientation of the wafer and the doping
concentration.
9
The Deal-Grove model, also known as the linear-parabolic oxide growth model, is commonly
used to estimate the thermal SiO2 growth under different furnace conditions [58]. The initial
oxide has a linear growth rate, and after reaching a certain thickness, the growth transitions to
a diffusion-limited parabolic growth. The Deal-Grove model was introduced in 1965 and is
well established for thermal SiO2 thicknesses above 30 nm. However, it has been
experimentally observed that the oxidation rate is much faster at the initial stages of oxidation
and for thin oxides under 30 nm. Various groups have proposed solutions for the limitations of
the Deal-Grove model by suggesting a second parallel oxidation reaction model [59], by fitting
thermal SiO2 experimental growth data to a power function [60] or by including a second term
in the Deal-Grove model [61].
The refractive index describes a change in the speed of light from one medium to another with
attenuation given by the complex value. The real component (i.e., refractive index), n, describes
the light velocity and the imaginary component (i.e., the extinction coefficient), k, describes
how the light is absorbed and scattered. The refractive index of thermal SiO2 has been well
characterized. At 632 nm, thermal SiO2 typically has a refractive index (n632) of ~1.45, which
is lower in comparison to α-quartz at ~1.53, while the k for thermal SiO2 has been measured to
be ~0 from 400–2000 nm [62, 63].
2.2.3 Surface passivation of thermal oxide
The first known silicon solar cell reported with thermal SiO2 surface passivation from the late
1970s achieved a Voc of 620 mV [24]. The improved development and understanding of the
thermal SiO2 surface passivation through the years has led to an increased Voc to above 700
mV [64]. These improvements have been achieved via hydrogenation and corona charging to
reduce the Dit and enhance the field-effect passivation, respectively [65, 66].
A variety of methods have been used to hydrogenate the interface of thermal SiO2-Si for solar
cells, such as FGA, alneal (annealing in the presence of Al) and plasma hydrogen. As
mentioned in Chapter 2.1, FGA is typically performed at 400–450 ˚C to reduce the defects of
Si-SiO2 through molecular hydrogenation. Thanh et al. showed that thermal SiO2 with a
thickness of 73 nm could reach a Dit as low as 1.2 × 1010 eV-1cm-2 [67]. Atomic hydrogenation
through alneal process or plasma hydrogenation typically reduces the Dit to be approximately
1010 eV-1cm-2 for thin thermal SiO2 layers [21, 68, 69].
10
10-1 100 101 102
10-1
100
101
102
Seff U
L (
cm
/s)
Si wafer resistivity (Ω.cm)
Thermal SiO2
P-type 100
N-type 100
N-type 100 - this work
N-type rantex - this work
Fig 2.3: Compilation of silicon oxide passivation wafers with various resistivities from the literature (transparent symbols) [64, 69-72] compared with the thermal SiO2 performed for this work (filled symbols).
The Seff concept introduced in the early 1990s was to describe surface recombination at specific
injection levels [73]. In this section, a comparison between the upper limit surface
recombination velocity (Seff.UL) for hydrogenated thermal SiO2 obtained from literature
together with FGA thermal SiO2 performed at the ANU on undiffused wafers, are plotted in
Figure 2.3 [64, 69-72]. The Seff.UL assumes negligible bulk recombination with effective
lifetime (τeff) reported at carrier injections between 1013 and 1016 cm-3.
2.3 Plasma-enhanced chemical vapour deposition of silicon nitride
Plasma-enhanced chemical vapour deposition (PECVD) was invented by Stirling and Swann
in 1965 [74]. More recently, PECVD technology in the silicon PV industry has achieved
remarkable surface passivation with advancements in plasma reactor configurations.
There are three common types of PECVD reactor configurations used in the PV industry: direct,
remote and dual mode. In the direct PECVD reactor, all the reactant gases are excited while
the substrate is exposed to the plasma. In the remote PECVD reactor, only one of the reactant
gasses is excited, and the plasma is spatially separated from the substrate. In the dual mode
PECVD, the gas is excited within the chamber, but the substrate is outside of the plasma. For
the direct and remote reactors, the plasma frequency is commonly set to 13.56 MHz and 2.45
11
GHz, respectively. However, in a dual mode PECVD, these two frequencies operate
simultaneously within the chamber.
100 200 300 400 500 600
101
102
103
1.6 2.0 2.4 2.8 3.2
101
102
103
SiN
x S
eff
UL (
cm
/s)
Deposition Temperature (°C)
Aberle et al.
Aberle et al.
Aberle et al.
Duttagupta Wan Kerr
(a) (b)
SiN
x S
eff U
L(c
m/s
)
Refractive Index (n)
Wan
Lauinger et al.
Mackel et al.
Duttagupta
Fig 2.4: Influence of the surface passivation for the PECVD SiNx with respect to (a) the deposition temperature [75-78] and (b) the different refractive indexes n632 by varying SiH4:NH3 gas ratio [76, 77, 79, 80].
PECVD SiNx is most commonly deposited using SiH4 and NH3 source gases together with
either a He or N2 as the diluent gas. The parameters that affect the deposition of PECVD SiNx
include the deposition temperature, plasma power, active gas ratio, chamber pressure and total
gas flow. A compilation of the different deposition temperatures is plotted in Figure 2.4a and
shows that optimal surface passivation can be obtained with films deposited at temperatures
around 300–450 ˚C. The surface recombination generally reduces with increasing SiNx
refractive index, as shown in Figure 2.4b. However, Wan stated that such observed trends are
due to optimised PECVD deposition conditions [77].
The defects in SiNx are not as well established as thermal SiO2. Silicon dangling bonds in SiNx
have many different configurations and charge states that can bond with silicon or nitrogen
atoms. Jousse et al. associated three distinct defect configurations at three different Lande
Splitting Factor (g values) and energy levels from the ESR and C-V measurements,
respectively [81]. Schmidt et al. defined four different defects (A, B, C and D) using deep-level
transient spectroscopy (DLTS) without knowledge of the atomic configurations for the defects
except for Defect D, which is thought to be the K centre [82, 83]. Stesmans et al. reported
similar ESR signature on dangling bond defect of a thermally grown silicon nitride (Si3N4)
(Pbn), and dangling bond defect of thermal SiO2 (Pb), on a 111 orientated silicon wafer which
12
suggests both dielectrics exhibit similar defect types [84]. This was similarly observed by
Garcia et al. using DLTS on PECVD SiNx wafers, showing that the Dit increases with the Pbn
[84, 85]. The relationship between the Dit at the midgap and the SiNx charge are normally
compared with the defect configuration and the N/Si ratio or with the refractive index of SiNx.
The PECVD SiNx is known to have large quantities of hydrogen within the film. Furthermore,
hydrogen molecules and radicals are generated during the deposition of SiNx [86, 87].
The deposition of PECVD SiNx has been shown to hydrogenate grain boundaries and the bulk
regions of multi-crystalline solar cells [88, 89], passivate the dangling bonds of the Si-SiO2
interface [90-94] and even hydrogenate FZ bulk wafers [95]. While the mechanism in which
SiNx improves the surface passivation is not unequivocal, the SiNx film is capable of releasing
hydrogen through an annealing process. Sheoran et al. demonstrated the release of deuterium
into the silicon bulk via the rapid thermal annealing of SiNx:D at 750 ˚C for one second [96].
2.3.1 PECVD silicon nitride charges
The specific silicon-nitrogen dangling bonds in which three N atoms are back-bonded to a Si
atom (Si≡N3), known as K centre defects, are the primary charge-trapping defects present in
the SiNx film [97-100]. The K centres are reported to be responsible for the large charges
measured within SiNx. The K centre exists in three different charge states: neutral K0, positively
charged K+ and negatively charged K-, with one, zero or two electrons on the dangling bond,
respectively. Sharma et al. managed to alter the K trapped centres using both positive and
negative corona charging on the SiNx wafers [101]. The altered charges injected into the SiNx
were found to be stable after a year in ambient conditions.
Mackel and Ludemann proposed that N-H bonds act as precursor sites with the •Si≡N3 dangling
bonds as the K-centre [80]. Therefore, it is predicted that Qeff increases as the SiNx becomes
more N-rich. However, Wan et al. compiled information on various deposition conditions from
different PECVD reactors and found that the Qeff in SiNx is strongly dependent on the
deposition conditions [77]. Moreover, Wolf et al. showed that MOS structures with a dielectric
SiNx refractive index ranging from 2 to 3 were capable of trapping positive and negative
charges by altering the direction of voltage sweep when performing C-V measurements [102].
A compilation of the Qeff of PECVD SiNx with various refractive indexes is shown in Figure
2.5 with no observed trend over the considered range.
13
1.6 2.0 2.4 2.8 3.2
1010
1011
1012
1013
Wan et al. (µW/RF dual-mode)
Lamers et al. (µW Remote)
De Wolf et al. (LF Direct)
Lelievre et al. (LF Direct)
Bagnoli et al. (RF Direct)
Dauwe (µW Remote)
Garcia et al. (ECR)
Hazel et al. (LF Direct)
Landheer et al. (ERC)
Helland (RF Direct)
SiN
x Q
eff (
cm
-2)
SiNx refractive index (n)
Fig 2.5: Effective charge Qeff measured within SiNx for various refractive indexes n632 [85, 102-109].
2.3.2 Optics of PECVD silicon nitride
The PECVD SiNx has a large range of refractive indexes that generally range between 1.9 and
2.7. An ARC of single layer PECVD SiNx has potential benefit over thermal SiO2 due to its
higher refractive index, which reduces the optical reflection of solar cells at an optimal
thickness in air or in modules encapsulated with glass.
The PECVD SiNx refractive index, extinction coefficient and thicknesses vary depending on
the conditions of the deposition parameters (power, pressure, temperature, gas flow, etc.). The
amount of silicon in the SiNx film dictates both the refractive index and the absorption
coefficient, as will be discussed in the following paragraph. Each PECVD system would,
therefore, require calibration to achieve the desired SiNx deposition conditions.
The refractive index of SiNx could be represented as the bonding-density-weighted linear
combination of reference refractive indexes at N/Si = 0 (i.e., amorphous silicon) and at N/Si =
4/3 (i.e., Si3N4) [110]. By neglecting the hydrogen bonds in the SiNx, Bustarret et al. proposed
that this ratio could be calculated using Eq 2.1 [111]:
= 1.33(3.3 − 632)632 − 0.5 (2.1)
n632: refractive index measured at 632 nm
14
As discussed previously is section 2.2.2, the extinction coefficient, k, is the sum of scattering
coefficient and absorption coefficient (α). When the extinction is only due to absorption (i.e.,
no scattering), the relationship between α and k is presented in Eq 2.2:
∝= 4 (2.2)
λ: measured wavelength k: extinction coefficient
A compilation of different SiNx with N/Si ratios using Eq 2.1, and extinction coefficients using
Eq 2.2, are plotted in Figures 2.6a and 2.6b. It is observed that an increasing N/Si ratio causes
both the n and k values to decrease as the SiNx become more N-rich.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.61.6
2.0
2.4
2.8
3.2 Bustarret et al.
Verlaan et al.
Verlaan et al.
Kessels et al.
This work
Bustarret Model
Re
fra
ctive
In
de
x (
n632)
N/Si Ratio
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.210-4
10-3
10-2
10-1
100(b)
Wan
Duttagupta et al.
Doshi et al.
van Erven et al.
This work
Extin
ctio
n c
oe
ffic
ien
t k a
t 3
60
nm
(k 3
60)
Refractive Index (n) at 632 nm
(a)
Fig 2.6: (a) Correlation between the refractive index n632 and the N/Si ratio for various SiNx films [111-113], and (b) the correlation between the extinction coefficient k measured at 360 nm (k360) and the refractive index n632 [77, 114-116].
2.3.3 Surface passivation of PECVD silicon nitride
The successful adoption of PECVD SiNx for commercial use in silicon solar cells resulted from
a variety of advantages, including a low-temperature deposition, atomic hydrogenation of the
surface and bulk [106], field-effect passivation from high positive charges and excellent ARC
properties. The PECVD SiNx has been reported to achieve a low Dit of ~1.8 × 1010 eV-1cm-2 on
a 1 Ω.cm n-type silicon substrate [117], which is comparable to the FGA of thermal SiO2. The
passivation of PECVD SiNx applied on the front surface of an IBC solar cell at ANU achieved
excellent surface passivation with a Voc of 703 mV in addition to the advantages of the
15
transparent SiNx ARC properties with a low absorption coefficient [14]. The excellent surface
passivation of SiNx deposited with Roth Rau AK400 dual mode plasma reactors were thought
to arise from an experimental artefact where the radio frequency (RF) substrate bias ignites an
unintentional deposition plasma before the ignition of the main microwave plasma [118]. The
RF plasma deposited a Si-rich layer, intervening SiNx layer in a film otherwise stoichiometric
SiNx [118].
As the solar industry utilises SiNx for surface passivation, continuous effort is being devoted
to reducing the surface recombination. The Seff of PECVD SiNx with various wafer resistivities
and refractive indexes from literature [14, 17, 115, 119-122] were compared to the optimised
PECVD SiNx deposited using Roth Rau AK400 at the ANU, is plotted in Figure 2.7 [117].
10-1 100 101 102
10-1
100
101
102
Seff U
L (
cm
/s)
Si wafer resistivity (Ω.cm)
P-type 100
N-type 100
N-type 111
N-type rantex
P-type 100 - This work
N-type 100 - This work
N-type rantex - This work
Fig 2.7: A compilation of SiNx passivations for various silicon wafer resistivities from the literature [14, 17, 115, 119-122] (transparent symbols) compared to the PECVD SiNx deposited using PECVD Roth Rau AK400 (filled symbols).
2.4 Atomic layer deposition of aluminium oxide
ALD can produce thin films through a layer-by-layer process [123]. The reaction cycle of a
two-precursor process is commonly executed as the first precursor reacts with the surface to
form a monolayer of material. After the excess precursor and by-products are purged from the
first reaction, the second precursor reacts with the first previously deposited layer on the surface
in a sequential, self-limiting manner. Under controlled deposition conditions, the film thickness
can be varied by only adjusting the number of reaction cycles.
16
There are two typical reactor configurations: Thermal and plasma-enhanced ALD (Pe-ALD).
Thermal ALD requires a certain temperature (temperature window) that is typically between
100-400 °C for reactants to react within the tight tolerances of processing conditions to achieve
the desired thickness. Temperatures outside the temperature window could decrease or increase
the growth of the film, either due to the lower thermal energy required for a reaction,
condensation of the precursor or from desorption or decomposition of the reactants. On the
other, PE-ALD uses plasma to enhance the reactivity of the reactants or influence the deposited
material characteristics. By increasing the reactivity of the reactants, quality films with high
growth rates can be achieved at relatively lower temperatures.
The deposition of Al2O3 with ALD is commonly performed using trimethylaluminum (TMA)
together with either O2 or H2O as the oxidizer. It has been reported that a thin layer of SiO2
forms between the silicon and the deposited Al2O3 [124-126]. The interface defects are reported
to be of the Pb0 type, which is similar to the Si-SiO2 interface on a 100 orientated wafer [127].
Furthermore, the Al2O3 film has been shown to release hydrogen when post-deposition
annealing (PDA) is performed above the deposition temperature, but the amount of released
hydrogen may be less than of PECVD SiNx [95, 128, 129].
2.4.1 ALD aluminium oxide charges
The high fixed charge density reported for Al2O3 is still a matter of discussion. The tetrahedral
coordination of AlO4 predominant at the silicon interface is considered a possible origin of the
fixed charge density [130-132]. The charges were reported to be located within the first few
nanometres above the silicon surface, and are independent of the Al2O3 thickness [130, 133].
Another explanation for the origin of the negative charges is due to interstitial oxygen atoms
caused by silanol rehydroxylation within the film [134].
2.4.2 Optics of ALD aluminium oxide
The refractive index n of ALD Al2O3 with a deposition temperature of ~200 ˚C on silicon is
approximately ~1.64 [135]. Kumar et al. similarly found ALD Al2O3 to have a n between 1.64–
1.67 on silicon with thicknesses of 200–400 nm [136]. However, Barbos et al. found the
refractive index of Al2O3 increases for thicknesses less than 10 nm [137]. The changes in the
17
refractive index of the film are thought to be due to the strong influence of the interfacial SiOx
between the silicon and Al2O3 [137].
2.4.3 Surface passivation of aluminium oxide
As ALD Al2O3 is less often employed commercially due to its slow deposition rates and low
throughput, the development of deposition alternatives for Al2O3 to increase throughput
includes PECVD, Spatial ALD and atmospheric pressure chemical vapour deposition
(APCVD). However, ALD Al2O3 is utilised extensively in laboratories to achieve excellent
surface passivation.
10-1 100 101 102
10-1
100
101
102
N-type 100 - this work
N-type 111 - this work
Seff U
L (
cm
/s)
Si wafer resistivity (Ω.cm)
P-type 100
N-type 100
Fig 2.8: A compilation of the data for Al2O3 passivation on various resistivities from the literature (transparent symbols) [17, 138-140] compared to Al2O3 undertaken using plasma ALD on a Beneq TS 200 (filled symbols).
The ALD Al2O3 provides both excellent chemical passivation and field-effect passivation from
negative charges. The Al2O3 deposited on the front of a boron diffused surface with ALD and
a backend phosphorus-doped polysilicon achieved an efficiency of 24.7% with a Voc of 703
mV [141]. Black et al. reported a measured Dit for ALD Al2O3 of ~4 × 1010 eV-1cm-2 on a 1
Ω.cm p-type silicon substrate [142], which is slightly higher than the average Dit for
hydrogenated thermal SiO2. A compilation of Seff.UL of Al2O3 passivation from literatures are
compared with the optimised Al2O3 deposition employed in this dissertation using the ALD
Beneq TS 200, as shown in Figure 2.8 [17, 138-140].
18
2.5 Doped polysilicon passivated contacts
Carrier selective passivation of contacts has attracted significant attention within the PV
research community. Doped polysilicon or tunnel oxide passivated contact (TOPcon) are
among the many technologies in this category, which are of high interest due to their excellent
electrical performance, commercial scalability and compatibility to existing silicon PV
production technologies. They typically consist of an ultra-thin SiO2 layer at 1-2 nm and a
heavily doped (phosphorus or boron) silicon layer with a polycrystalline phase. The IBC solar
cells utilising doped polysilicon technology recently achieved efficiency of 26.1% [11] . The
key advantage of doped polysilicon contacts is that they form a well passivated surface that
also enables carrier extraction through the thin SiO2 layer [143-145].
The thin SiO2 layer can be grown either chemically [146], using ozone oxidation [147] or in a
high-temperature furnace [148] for a short duration. The amorphous silicon is deposited either
through PECVD or with low-pressure chemical vapour deposition (LPCVD) and is doped and
annealed at high temperatures to form the doped polysilicon with either thermal diffusion [148,
149], spin-on doping, or ion implantation [150]. The thin SiO2 layer between the doped
polysilicon and the silicon substrate provides chemical passivation and acts as a tunnel oxide
for holes or electrons to tunnel through [151, 152], or as a low-density pinhole layer that allows
carriers to channel through [151]. The doped polysilicon provides a field-effect passivation that
can induce a band bending at the polysilicon-silicon interface which prevents recombination of
minority carriers onto the surface [153]. The surface passivation can be further improved with
hydrogenation process of the polysilicon structure [154-156].
2.5.1 Optics of polysilicon
A thick polysilicon layer annealed at high temperature has a relatively similar refractive index
as crystalline silicon [157]. However, the optical properties of thin polysilicon layers have not
been well characterized. Laghla et al. showed the refractive index of polysilicon varies with its
thickness [158]. Using LPCVD, they observed variations in the polysilicon refractive index
due to surface roughness with increasing deposition time. Due to the absorptive nature of doped
polysilicon at visible and infrared wavelengths, high-efficiency cells have polysilicon
deposited mostly at the back side to avoid absorption losses [159].
19
2.5.2 Passivation and contact resistivity of doped polysilicon
The growth conditions of silicon oxide between the doped polysilicon and silicon are important
for the quality of the surface passivation and contact resistivity for a solar cell. The silicon
oxide should be sufficiently thick to provide excellent passivation while thin enough for
carriers to flow. Therefore, a trade-off is commonly observed between the quality of surface
passivation and contact resistivity [149, 160].
Phosphorus-doped polysilicon with a chemical oxide or thermal SiO2 has been reported as
having excellent properties. Yan et al. reported phosphorus-doped polysilicon with a SiOx at
1.4 nm thick that achieved a saturation current density (J0) ~2 fA/cm2 and contact resistivity of
~3 × 10-3 Ω.cm2 [141]. Fong et al. reported a thermal SiO2 that was under 1.5 nm achieved a
J0 ~3 fA/cm2 and contact resistivity ~7 × 10-4 Ω.cm2 [161]. A compilation of the J0 and contact
resistivity for passivated contacts with phosphorus-doped polysilicon is plotted in Figure 2.9a.
10-3
10-2
10-1
100
101
102
103
100
101
102
103
10-3
10-2
10-1
100
101
102
103
100
101
102
103
Satu
rate
d c
urr
ent
J0 (
fA/c
m2)
Contact resistivity (mΩ.cm2)
Gan et al.
Feldmann et al.
Peibst et al.
Yan et al.
Fong et al.
(a) (b)
Satu
rate
d c
urr
ent
J0 (
fA/c
m2)
Contact resistivity (mΩ.cm2)
Gan et al.
Feldmanns et al.
Yan et al.
Peibst et al.
Fig 2.9: Doped polysilicon comparing the measured contact resistivity and the saturated current J0 for (a) doped phosphorus [149, 151, 162, 163] and (b) doped boron [148, 151, 162, 163].
A compilation of boron-doped polysilicon passivated contact results from the literature is
plotted in Figure 2.9b and shows an overall slightly higher J0 and contact resistivity as
compared with phosphorus-doped polysilicon [148, 151, 162, 163]. To the author’s knowledge,
the report of Peibst et al. is one of the best for boron-doped polysilicon with thermal SiO2,
which achieved a J0s of ~4 fA/cm2 with a contact resistivity of ~10-2 Ω.cm2 [151].
20
2.6 Electret
An electret is a stable dielectric material that exhibits a quasi-permanent electric charge or
dipole polarisation. There are two classes of electrets: dipolar electrets and space charge
electrets. Dipolar electrets are electrically neutral but have a macroscopic electric dipole
moment (like a magnet), whereas space charge electrets have a net macroscopic electrostatic
charge (like a capacitor).
The two types of electrets are fabricated using different techniques. Dipole electrets are
constructed by heating a material above its glass-transition temperature and cooling it slowly
within a strong electric field. As the material solidifies, the individual molecular dipoles
become ‘frozen’ with a net orientation in the direction induced from the electric field. Space
charge electrets are fabricated by incorporating changes into the surface (or bulk) through a
bombardment with an electron beam, corona discharge or the direct contact with a charged
electrode.
2.6.1 Corona charging on silicon oxide and silicon nitride electret
Corona discharge is a process where an electrode with a high potential ionizes the air around it
to create a plasma. The ions (ionized air molecules) pass charges to a nearby lower potential
region or recombine to form a neutral gas molecule. A corona charger is therefore used to
deposit charges onto the surface of a wafer.
A conventional corona charger has a needle that is placed several centimetres above the desired
sample [164]. A high potential is then applied to the source needle, which ionizes the
surrounding air molecules. Depending on the polarity of the applied potential, the majority of
the ionized air molecules, of either COor H3O+, are deposited onto the surface of the sample
[165]. A mesh grid with lower potential between the sample and the needle can be used to
control the amount of charges and their distribution on the surface [164].
The formation of a silicon oxide electret can benefit due to both its excellent chemical
passivation and additional field-effects to reduce the surface recombination [65, 166, 167]. An
ideal corona charged silicon oxide electret should retain the deposited charges to render it
useful; however, there are reports of the corona charge electrets decaying at high temperatures,
21
humidity, light exposure, and bulk and lateral conduction of the dielectric material [168-172].
Nonetheless, there are ways to overcome certain decay mechanisms, such as by reducing the
surface conduction by using hexamethyldisilazane (HMDS), while additional annealing can
drive surface charges into the bulk of the dielectric [167, 170, 172].
Corona charging to passivate dielectrics can be of benefit by inducing a field-effect via either
accumulation or inversion to reduce the surface recombination [65, 166, 167, 173, 174].
However, as mentioned, corona charging treatments of surfaces are known to decay over time.
The silanol group at the surface of the SiO2 was reported by Voorthuyzen et al. to be
responsible for the lateral conduction of charges at the surface, either due to mobile protons
from these groups or the ability of the groups to attract water molecules [172]. Olthuis et al.
showed that the lateral conduction of charges can be reduced by modifying the polar silanol
surface with a terminating apolar methyl group using HMDS [168]. They also acknowledged
that although using HMDS may reduce the surface conduction, the silanol group within the
bulk of the silicon oxide may pose a threat to the long-term charge stability in humid
environments.
Other methods of charge storage with SiO2 include annealing positive charges at temperatures
of 250–400 ˚C [65, 167, 170]. Minami et al. showed that annealing a corona-charged surface
drives the charges into the bulk and is able to withstand high humidity for long periods of time
[170]. Although Minami et al. performed various characterizations to investigate the effect of
annealing on the charge storage, the results were inconclusive, and the underlying mechanism
was not well understood. Other methods, including capping the SiO2 with Si3N4 (SiO2-Si3N4
structure) or Si3N4-SiO2 (SiO2-Si3Nx-SiO2 structure) have been reported to be superior at
retaining positive charges compared with a single SiO2 layer at 300 ˚C [175]. Zhang et al.
showed that annealing causes the trapped charges to drift from the surface of the ON structure
into the dielectric bulk in a similar manner as SiO2 [176].
2.6.2 Surface passivation of corona charged silicon oxide
As previous discussed in Chapter 2.2.1, thermal SiO2 has a low density of fixed oxide charges.
To demonstrate the outcome of the field-effect passivation, corona charging was performed on
a high resistivity 100 Ω.cm silicon wafer with thermal SiO2 surface passivation.
22
The surface passivation improves (reduced J0s) with an increasing positive corona charge
deposited onto the SiO2 surface, as plotted in Figure 2.10. The accumulation of majority
carriers at the surface prevents minority carriers from recombining. Corona charging over 80
seconds has shown to have a reduced lifetime; however, the J0s remains relatively constant,
which suggests that corona charging may have cause bulk degradation via dehydrogenation.
Such observations are not new, and other research groups have observed similar occurrences
related to dehydrogenation [177, 178].
0 20 40 60 80 100
4
8
12
16
20
τeff
(∆n ~ 1015
)
J0s
Corona charging duration (s)
τ eff
(ms)
4
8
12
16
20
J0s (fA
/cm
2)
N-type 100 Ω.cm
Fig 2.10: Accumulative corona charging for an n-type 100 Ω.cm FZ wafer with at a 406-µm thick thermal SiO2.
These results demonstrate that the field-effect improves the surface passivation; however,
caution has to be taken so that sufficient charge is deposited without degrading the surface or
bulk via dehydrogenation. The use of corona charging will be extended onto surface
passivation with an ONO stack as discussed in subsequent chapters.
2.7 Chapter summary
This chapter discussed and summarised the various methods of surface passivation commonly
used in silicon solar cells. Thermal SiO2 can attain a low Dit after hydrogenation with relatively
low fixed oxide charges. PECVD SiNx can achieve a low Dit and high positive charges, whereas
ALD Al2O3 can similarly achieve a low Dit and high negative charges. The charges create a
field-effect passivation that may accumulate or invert the surface.
23
The following chapters present the fabrication, optimisation and implementation of ONO stack,
which includes thermal SiO2, PECVD SiNx and SiOx, together with corona charging to
investigate the best methodology to improve chemical and field-effect passivation in IBC solar
cells.
24
Chapter 3
Characterisation methods
This chapter discusses the characterisation methods used throughout this work, which include:
1. Characterisation of the recombination in the silicon bulk, surface, and diffused region
2. Characterisation of the charge density in dielectrics
3. Current-voltage (I-V) measurements and analysis of I-V data in solar cells.
3.1 Photoconductance measurement and recombination mechanism in
solar cells
Photoconductance measurements performed on wafers determines the decay in the
conductivity after illumination to calculate the minority carrier lifetime [179, 180].
The initial conductivity of a silicon wafer is measured with the wafer placed above a coil to
form a bridge circuit. A flash is then applied to the wafer, causing an increased conductance.
As the flash intensity decreases, the differences in the decrease conductivity can be used to
calculate the minority carrier concentration using Eq 3.1
∆ = ∆ ! + !# (3.1)
µn: mobility of electrons µp: mobility of holes w: thickness of wafer ∆σ: conductivity
With known carrier concentration given by Eq 3.1, the effective lifetime can be calculated
using Eq 3.2
$%&& = ∆' − (∆()
(3.2)
where ∆n is the time-dependent average excess carrier density and G is the photogeneration
rate for the electron-hole pairs.
25
There are two different types of measurement modes: quasi-steady state (QSS) and transient.
During QSS measurements, the illumination period is long relative to the lifetime. Thus, the
decay of the excess carrier concentration can be ignored, and the lifetime measurement can be
calculated as in Eq 3.3. While the QSS mode is not limited by the lifetime, the photogeneration
rate is required for accurate measurements.
During transient measurements, the illumination period is shorter than the lifetime. Thus, the
photogeneration rate can be ignored, and the lifetime measurement can be calculated as in Eq
3.4. The transient mode is limited by the measured lifetime, as it requires the lifetime to be
much longer than the decay of the illumination period (commonly with measured lifetimes
above 200 µs).
$%&& = ∆' (3.3)
$%&& = ∆(∆() (3.4)
All photoconductance measurements performed in this thesis were in transient mode because
the measured wafers were well-passivated and have relatively high lifetimes. The measured
effective lifetime can be modelled to represent the surface, bulk and emitter recombination as
given by Eq 3.5 because the minority carrier diffusion length is large compared with the wafer
thickness. Each of the recombination will be discussed in the following sections.
1$%&& = 1$*+,- + 1$.+/&01% + 1$%2344%/ (3.5)
3.1.1 Bulk recombination
There are three main fundamental recombination mechanisms within bulk silicon material:
Radiative, Auger and Shockley-Read-Hall.
Radiative recombination occurs when an electron from the conduction band recombines with
a hole in the valance band and emits a photon. This recombination dominates in direct bandgap
semiconductors such as GaAs; however, an indirect bandgap material such as silicon has low
radiative recombination relative to other modes that is unlikely to impact the overall lifetime.
26
Auger recombination occurs when an electron recombines with a hole by releasing excess
energy to a third charge carrier (electrons in the conduction band or holes in the valance band).
The kinetic energy given to the third charge carrier is lost as phonons when the excited carrier
relaxes to its original energy state via ‘thermalisation’. Three charge carriers are involved in
Auger recombination: either two electrons and a hole, or two holes and an electron. Therefore,
the recombination rate is proportional to the product of the concentration of the three carriers.
An empirical parameterisation based on experimentally measured lifetimes is often used
instead to describe the Auger recombination rate due to difficulties in theoretically determining
the Auger recombination parameters. The parameterised Auger recombination rate
implemented in this work can be written as shown in Eq 3.6 [17].
$34/,%6 = ∆7(2.5 × 109:%%6; + 8.5 × 10=:%667; + 3.0 × 10=>∆;.>= + ?,@A (3.6)
:%%6(;) = 1 + 13 B1 − tanh GH ;3.3 × 109IJKL;.MMNO (3.7)
:%66(7;) = 1 + 7.5 B1 − tanh GH 7;7.0 × 109IJKL;.MNO (3.8)
Blow: Radiative recombination coefficient for lowly doped and lowly injected silicon 4.7 × 10-15 cm3s-1 at 300 K [181]. n0: Thermal equilibrium of electron density p0: Thermal equilibrium of hole density
Crystal defects and impurities introduce energy states or defect levels within the bandgap,
which allows a free electron within the conduction band to transition into the defect level before
recombining with a hole in the valance band. The recombination rate depends on the electron
and hole concentrations, as well as the properties and density of the defect. The recombination
can be modelled using Shockley-Read-Hall (SRH) statistics and for a single defect level, as
shown in Eq 3.9 [182].
QRST = U46V(7 − 3=) + 9 + 7 + 79= 7 − 3=$;( + 9) + $;(7 + 79) (3.9)
$; = 1VU46 (3.10)
$; = 1VU46 (3.11)
27
9 = 1WX7 YZV − Z1[ \ (3.12)
79 = ]WX7 YZ] − ZV[ \ (3.13)
: capture cross section of holes : capture cross section of electrons V: density of defect U46: thermal velocity charge carriers ET: energy level of the defect n1: electron density when Fermi level coincides with defect energy level ET
p1: hole density when Fermi level coincides with defect energy level ET Nc: effective densities of states in the conduction band Nv: effective densities of states in the valance band
The SRH bulk lifetime for n-type silicon can be derived from Eq 3.9 and expressed as Eq 3.14.
$RST ≈ $;( + 9) + $;(7 + 79)_ + ∆ (3.14)
3.1.2 Surface recombination
Dangling bonds on the surface can give rise to a large density of defect levels within the silicon
bandgap. Unlike bulk SRH centres, which occupy a single energy state, multiple states can
exist on the surface throughout the bandgap. The surface recombination can be modelled using
SRH statistics from the bulk by replacing NT with Dit and integrating over the entire bandgap,
as given by Eq 3.15 [182].
QR = ` U46(.7. − 3=). + 9(Z) + 7. + 79(Z)a1
a] b34(Z)(Z (3.15)
ns: electron density at the surface ps: hole density at the surface
The surface values of ns, ps, σp, σn and Dit are generally not known; however, the surface
recombination in Eq 3.15 can be further simplified using a surface recombination velocity (Seff)
with the respective carrier concentration at the surface, as shown in Eq 3.16. Alternatively, for
a highly charged surface passivation, the surface recombination can be described using a
saturation current density J0s as in Eq 3.17 [183]. The J0s can be measured using Kane and
Swanson method from photoconductance measurements of symmetrical passivation on silicon
wafers [184]. In most of our work, J0s is used to describe the surface passivation of an ONO
28
stack as it satisfies the condition Q2/Ns >1.5 × 107 cm. The advantage of J0s over Seff is that J0s
is carrier injection independent within the measured range of excess carrier concentration [183].
QR = %&&∆. (3.16)
QR = 3= × c;.(7.. − 3=) (3.17)
When a wafer has a high bulk lifetime and the excess carrier concentration is uniform
throughout the sample, the surface carrier concentration is assumed to be similar to the bulk
carrier concentration (Eq 3.18) or for a highly charged surface passivation (Eq 3.19).
$.+/&01% = d2%&& (3.18)
$.+/&01% ≈ 3=d2c;.(e + ∆) (3.19)
It should be noted that Kane and Swanson method does have limitations. One of the limitations
includes assuming τbulk is constant across the measured carrier injection level. Such limitation
is observed in some of the measured J0s presented in Chapter 4.
3.1.3 Emitter recombination
Recombination within the emitter depends on several factors, including the minority carrier
concentration, Auger recombination, SRH recombination, carrier mobility, effective masses
and the band gap narrowing. Moreover, the surface concentration from the emitter doping
affects the surface recombination. Cuevas et al. [185, 186] solved the continuity equation and
used a 3rd order analytical approximation to calculate the recombination of the emitter, as
shown in Eq 3.20. However, accurate calculation of J0e requires details of the surface
recombination velocity SP, the diffusion profile and the Auger lifetime τp within the emitter,
which are generally not well known.
c;% = 7;(d)f1 + ?=()g + h (X 7;(X)$(X) i=(X)j;1 + h (X 7;(X)$(X) k9(X) + 7;()fk9() + k()gA;
(3.20)
29
k() = ` (X9 1b(X9)7;(X9)` (X= 7;(X=)$(X=) ` (X 1b(X)7;(X)l=
;l9
;j
;
k9() = ` 1b(X9)7;(X9)j
; (X9 (3.21)
Nevertheless, the measured values of J0e can be extracted using the Kane and Swanson method
from photoconductance measurements of a high resistivity wafer with symmetrical diffusion,
as shown in Eq 3.22 [184].
$%&& ≈ 3=d2c;%(e + ∆) (3.22)
The reported J0s and J0e in this thesis were an average of at least of 3 photoconductance
measurements.
3.2 Capacitance-voltage measurement
Capacitance-voltage (C-V) measurements of metal-oxide-semiconductor (MOS) capacitors are
widely used to measure the charges within dielectrics and the Dit of MOS structures. The MOS
structure is a two-terminal device composed of a metal deposited on top of a dielectric oxide
with the rear contact on grounded silicon. The following discusses the MOS structure for
thermal SiO2.
Thermal SiO2 may contain various charges trapped within the dielectric. As discussed in
Chapter 2, thermal SiO2 charges can be categorized as either fixed charges (Qf), oxide-silicon
interface charges (Qit), oxide trapped charges or mobile oxide charges. The fixed charges
within thermal SiO2 are generally positive and can be reduced using POA in either N2 or Ar
gas. The interface trap charges are either positive or negative and are caused by either dangling
bonds at the Si-SiO2 interface, oxidation-induced defects or metal impurities. The interface trap
charges within the Si-SiO2 interface can be reduced via hydrogen annealing at low temperatures.
Oxide trapped charges are either positive or negative and are the result of holes and electrons
within the thermal SiO2. The causes of such charges include ionizing radiation, avalanche
injection or they occur during the operational conditions of the device. Mobile oxide charges
can also consist of ionic impurities within the oxide, such as sodium, lithium, potassium or
hydrogen ions. These impurity contaminations are commonly found within the oxide due to
30
exposure during equipment cleaning processes that use chemicals including vacuum pump oil
and chemical-mechanical polish. The ion contaminations on the wafers can be reduced using
Radio Corporation of America (RCA) cleaning.
In an ideal condition when no charges are presented within the oxide, the flatband voltage (VFB)
is equal to zero. However, the presence of charges commonly found within the oxide (Qox)
shifts the VFB. Under such condition, the flatband condition in a MOS structure illustrated in
Figure 3.1, occurs when no charges are present within the semiconductor. The solution of Eq
3.23 can provide the quantity of charges within the thermal SiO2 at the flatband voltage.
Fig 3.1: MOS capacitor structure with the (a) energy band diagram and (b) charge density under flatband conditions
m@l = i@l nop × (@lk((@l − X) (3.23)
A: Area of metallised region q: Electron charge of 1.602 × 10-19 C Ф2.: Workfunction differences of metal and silicon Cox: Oxide capacitance VFB: Flatband voltage
During a C-V measurement, the VFB could be obtained from the calculated flatband capacitance
(CFB) as shown in Eq 3.24 and 3.25.
Ef,m
Фm
Qox
Ef,Si
n-type Si
SiO2
Metal
Evac
EC
EV
ρ(x)
(a)
(b)
χ
dox
qVFB
E
i
x
31
1iop = u_k. vR3 + 1i@l (3.24)
u_ = wvR3[=_ (3.25)
The LD in Eq 3.25 is defined as the Debye length, which is known as an ‘effective shielding
distance’ and is described by Evans as a ‘characteristic distance that some external electric field
can penetrate a neutral semiconductor surface without substantially perturbing the
semiconductor away from neutrality.’ [187].
The work function difference between a metal and silicon can be determined using Eq 3.26.
Ф2. = nop = Ф2 − x. − (Z1 − Z3) + Z& − Z3# (3.26)
Z1 − Z3 = [ y Y13 \ (3.27)
Z& − Z3 = [ y Y_3 \ (3.28)
Ф2: Workfunction of metal x.: Electron affinity Nc: Effective densities of states in the conduction band Nd: Concentration of donor doped atoms
3.3 Current-voltage measurement
Current-voltage (IV) measurements are used to establish the performance of a solar cell. The
cell performance can be analysed from each I-V curve to determine the short circuit current
(Jsc), open circuit voltage (Voc), fill factor and the efficiency of the cell. Other information, such
as the series and shunt resistances, non-ideality factor(s) and temperature coefficient, can be
extracted from multiple I-V measurements under different lighting and temperature conditions.
The I-V measurements for an IBC solar cell were performed using a custom designed
measurement jig with an independently measured aperture mask of 3.99 ± 0.01 cm2. The layout
of the jig is presented in Figure 3.2 and has multiple probes that can measure six IBC solar
cells on each wafer. Each cell has eight probes in total; six current and two voltage probes. The
middle voltage and current probes are 3 mm apart, whereas the distance between the current
probes at a similar busbar polarity is 6.7 mm. Each of the current probes is connected to a
32
resistor for uniform current distribution across each pin. The jig has a thick Al base and four
Peltier coolers and fans to control the overall temperature while taking the measurements. The
jig was anodised black to avoid light reflections that may cause artificial increases in the Jsc.
The cells loaded onto the jig were held in place with a vacuum pump and the aperture mask
that defines the active cell area was made from a silicon wafer. The mask was painted with
black matt paint on the front and a 100 nm evaporated Al layer at the rear to reduce the
reflection of light back into the light source (mirrors are the light source) and to prevent infrared
wavelength into the cell.
Fig 3.2: Layout design of the cells placed onto the jig with metal contact probes.
Listed below are the steps performed to achieve accurate I-V measurements:
1. For a halogen light source, the lamp was pre-warmed for 30 minutes to an hour. The jig
temperature was set and stabilised for at least ten minutes before the measurements.
Figure 3.3 shows the measured surface temperature of the jig using a calibrated
thermocouple with time at different pre-set temperatures. The pre-set temperatures on
the controller were measured to be 1–2 ˚C lower than the desired jig temperature; thus,
a pre-set temperature of 26.2 ˚C was set to achieved ~25 ˚C on the jig.
2. The current density of a calibrated reference cell was measured at a defined area under
the illuminated light source. The light intensity of the halogen lamp was adjusted to
match the specified current density of calibrated reference cell at 1 sun.
TLM structure for boron
TLM structure for phosphorus
Dielectric isolation pads
Metal line resistance
33
3. The IBC solar cell, together with the aperture mask, was placed in a similar area and at
a similar height to the previous reference cell location.
4. Measurements of the I-V curve were performed by sweeping the voltage from 0.8 to -
0.05 V using a Keithly source meter. To avoid an unnecessary increase in the cell
temperature caused by the illumination of the light source, an inbuilt shutter was
programmed to open just before the cell measurement.
5. After measuring all cells, the light intensity was remeasured with the calibrated
reference cell at cell measurement area to account for any drift in the halogen light
source.
0 500 1000 1500 2000
20
21
22
23
24
25
26
27
Pre-set
to 26 °C
Pre-set
to 23 °C
Calibrated thermocouple top of stage
Internal thermocouple
Te
mpe
ratu
re (
°C)
Time (s)
Pre-set to 27 °C
Fig 3.3: Different pre-set jig temperatures with measured internal (underneath the Al plate) and external (top of the stage) thermocouples.
The series resistance (Rseries) of a solar cell can be determined using either multiple light I-V
method or comparing light and dark I-V measurements [188]. The measured series resistance
from an I-V curve includes resistance from the bulk, metallised fingers and busbar as well as
the contact resistance of the metal and silicon interface. Figure 3.4a plots the light and dark I-
V measurements for an IBC solar cell, from which the Rseries can be extracted at specific
voltages, as shown in Figure 3.4b, using Eq 3.27. It is noted that the extracted Rseries can be
viewed as a function of the voltage. Therefore, the series resistance, which is commonly
represented as a lumped Rseries, is oversimplified. The shunt resistance in a solar cell is often
due to imperfections of fabricate solar cell device which provide an alternative path for the
light-generated current [189, 190]. The shunt resistance (Rshunt) can be determined from the
34
dark I-V measurements at low voltages of 0–0.1 V, as shown in Figure 3.4a. However, the
accuracy of measuring Rshunt is limited with non-ideal recombination at low voltages.
zW|W ≈ n(| − ny:ℎ)cJ (3.27)
0 200 400 600 80010
-3
10-2
10-1
100
101
102
0 200 400 600 8000
1
2
3
4(b)
Cu
rre
nt
(mA
/cm
2)
Voltage (mV)
Dark IV
Shifted light IV J
RShunt
J0
Mpp
Fitting Rs
Se
rie
s R
esis
tan
ce
(Ω
.cm
2)
Voltage (mV)
Mpp
(a)
Fig 3.4: Measurement of (a) the shifted light and dark I-V curves with the simulated shunt resistance and J0, and (b) the extracted Rs measurements from the shifted light and dark I-V curves using Eq 3.27.
35
Chapter 4
ONO: Growth and deposition conditions
4.1 Introduction
Excellent surface passivation is predominately achieved by having both exceptional chemical
and induced field-effect passivations. This chapter discusses the development of an ONO
surface passivation stack, which consists of a thin thermal SiO2, followed by a PECVD SiNx
and SiOx stack. The initial thermal SiO2 layer provides chemical passivation from its low Dit
between Si-SiO2. The subsequent PECVD SiNx layer enhances the passivation with a field
effect from positive charges and hydrogenates the Si-SiO2 interface. The final PECVD SiOx
layer improves the overall optical properties of the stack in air while retaining additional
positive charges from corona charge deposition.
This chapter begins with the baseline fabrication process sequences used in the formation of
ONO stacks, which include thermal oxidation, the deposition of PECVD SiNx and SiOx, FGA
and corona charging. This is followed by sections that describe the optimisation study of the
film deposition by varying the growth and deposition conditions of each individual layer, while
simultaneously evaluating both the passivation quality and the optics of the stack. Finally, this
chapter summarises the optimal passivation conditions performed on undiffused, n-type,
silicon wafers to achieve lifetimes that exceed the commonly accepted intrinsic recombination
model.
4.2 ONO baseline procedure
High resistivity FZ n-type 100 Ω.cm silicon wafers with a 100 orientation were etched in
TMAH for 10 minutes at 85 ˚C to remove any saw damage, cleaned using the standard RCA
process and subsequently dipped in a 1% HF solution until the surfaces became hydrophobic.
Thermal oxidation was conducted in a quartz tube furnace under ambient O2. The wafers were
loaded at 700 ˚C and ramped up to 1000 ˚C at a rate of 15 ˚C/min in O2. After reaching 1000
˚C, the wafers were annealed in N2 at the same temperature for 45 minutes followed by a ramp
36
down to 700 ˚C. The thermal SiO2 thickness was measured as 15 ± 1 nm using an ellipsometer
(JA Woollam M2000D) [62].
After the thermal oxidation, amorphous SiNx and SiOx films were deposited individually with
PECVD using an Oxford Instruments PlasmaLab 100 deposition tool. For the SiNx depositions,
gas flowrates of 13 sccm for SiH4, 14 sccm for NH3 and 980 sccm for N2 were used at a
deposition temperature of 400˚C, a chamber pressure of 650 mT and forward plasma power of
20 W, which yielded an SiNx thickness of 50 ± 3 nm and refractive index at 632 nm (n632) of
~1.93. The PECVD SiOx depositions were performed at 250˚C with flows of 9 sccm for SiH4,
710 sccm for N2O and 161 sccm for N2, which produced films with a thickness of 90 ± 5 nm
and n632 of 1.48. The thickness of the SiNx and SiOx films was selected specifically for ARC
purposes based on simulations in OPAL2 [19]. All the wafers received a FGA at 400 ˚C in a
quartz tube furnace for 30 minutes.
The ONO wafers were then positively corona charged in a conventional setup without a mesh
grid using a steel needle with an applied voltage of 5 kV at an elevation of 8 cm above the
wafers [164]. The surface charge deposition was performed symmetrically on both surfaces,
and the wafers were then subjected to an additional FGA at 400 ˚C for 30 minutes to embed
the surface corona charges into the ONO stack [65, 167, 176]. The effective lifetime of the
wafers was measured before the positive corona charging and again after the anneal step.
4.3 Thermal oxide growth conditions for an ONO stack
This section investigates the effect of the thermal SiO2 thickness and duration of the post-
oxidation annealing (POA) on the passivation quality of the ONO stack. The performed
investigation is shown in the flowchart presented in Figure 4.1 with the details described in the
following subchapters.
37
Fig 4.1: Flow chart detailing the variations for each layer (relative to the baseline) to establish the best passivation conditions of thermal SiO2 for ONO stack (a) The baseline procedure is represented by the white boxes, while variations to the oxidation temperature are highlighted in grey. (b) Variations to the POA time and ambient are highlighted in dark blue.
4.3.1 The effect of varying the thermal oxide thickness
The primary function of the thermal SiO2 is to provide a low Dit between the Si and the
passivating dielectric stack. A thermal SiO2 satisfies the basic criteria of having a low Dit
interface while providing excellent thermal stability. Further layers can be deposited on the
surface without negatively impacting its physical properties. The goal of the thermal SiO2
optimisation is to form a film that provides the desired low Dit characteristics with low
thickness to limit the optical losses associated with having a low refractive index material next
Embedding Charges
Forming Gas Anneal 400 °C
Planar 100, quartered
Thermal
Oxidation
850 °C
PECVD Silicon Nitride 400°C
PECVD Silicon Oxide 250 °C
Forming Gas Anneal 400 °C
Positive Corona Charging
Thermal
Oxidation
900 °C
Thermal
Oxidation
950 °C
Thermal
Oxidation
1000 °C
Nitrogen annealing 1000 °C
(a) Thermal SiO2 thickness
Planar 100, quartered
Thermal
Oxidation
1000 °C
Ramp down in
oxygen
PECVD Silicon Nitride 400 °C
PECVD Silicon Oxide 250 °C
Forming Gas Anneal 400 °C
Positive Corona Charging
Embedding Charges
Forming Gas Anneal 400 °C
Thermal Oxidation
1000 °C
Anneal and ramp
down in nitrogen
(b) Post-oxidation annealing in N2
38
to the silicon surface [191, 192]. Therefore, this section examines the effects of varying the
thermal SiO2 thickness on the overall electrical performance of the ONO stack.
Experimental details:
A 100 Ω.cm n-type FZ silicon wafer with a thickness of approximately 400 µm was cleaved
into quarters. The growth and deposition of the ONO on all quarters were identical to the
baseline, except for the variable temperature for oxidation (and hence oxide thickness) as
described in Figure 4.1a. Each wafer was loaded in pure O2 at 700 ˚C and ramped to different
temperature set points. The oxide growth occurred during the ramps to 850, 900, 950 and 1000
˚C. Once the temperature set points were reached, the gas flow was switched from O2 to N2
and the wafers were subjected to further annealing at 1000 ˚C for 45 minutes in N2.
Results and discussion:
The measured surface saturation current density (J0s) and effective lifetime (τeff) for all the
wafers are presented in Figure 4.2. Two different sets of lifetimes are reported. The τeff reported
at an carrier injection level of 1015 cm-3 (τeff_1015) corresponds well to the operating maximum
power point of a high-efficiency solar cell, whereas the maximum lifetime (τeff.max) is reported
across measured injection level between 1013–1016 cm-3.
The experimental results indicate that a minimal oxide thickness of around 7 nm is necessary
for passivation levels of <5 fA/cm2. Further increases in the thermal SiO2 thickness do not
provide additional benefits, so this is considered the optimum for electrical and optical
performances of the ONO stack. For practical reasons, a target of 10 nm thick thermal SiO2 is
used when ONO is utilised in cell fabrication (Chapter 6) due to uncertainties in the process
controls.
In most cases, variations in the passivation layer thickness are known to affect the passivation
quality [193]. In general, thicker passivation layers (thermal SiO2, PECVD SiNx and ALD
Al2O3) perform better than thinner films [139, 192, 194, 195]. It is uncertain why the
passivation of thinner thermal SiO2 layers capped with either SiNx or SiNx-SiOx has a worse
performance when less than 10 nm. However, Black et al. suggested that thinner thermal SiO2
layers may be related to the deterioration of the chemical passivation [193]. Moreover, a similar
39
trend was observed by Kerr et al. and Mack et al. for thermal SiO2 capped with PECVD SiNx
(ON stack), in which they reported no correlation of passivation quality with thermal SiO2
thicknesses above 10 nm [192, 194]. Nevertheless, there is a possibility that in this experiment,
the variations in the oxidation growth temperatures from 850 to 1000 ˚C to achieve the desired
thicknesses may affect the surface passivation.
0
5
10
15
20
25
30
35
τ eff
(ms)
τeff.max
τeff_1015
J0s
4 6 8 10 12 14 160
5
10
15
J0s (
fA/c
m2)
Thermal oxide thickness (nm)
Fig 4.2: Minority carrier lifetimes and J0s measured for ONO wafers with different thermal SiO2 thicknesses.
4.3.2 The effect of post-oxidation annealing of thermal oxide
The passivation of dielectrics with a large number of charges may benefit (accumulation of
majority carriers at the surface) or worsen (deplete majority carriers at the surface) the solar
cell performance [196]. As reviewed in Chapter 2, performing an anneal with N2 at
temperatures of 800–1000 ˚C reduces the number of positive charges in the thermal SiO2 [53,
57]. However, the impact of POA on the surface Dit of Si-SiO2 is more complicated. Razouk
et al. reported that the POA can either increases or reduce the surface Dit depending on the
wafer orientation, annealing duration and subsequent hydrogen annealing [30]. In this section,
POA with N2 on thermal SiO2 was examined to achieve a desired low surface recombination
on the ONO stack.
40
Experimental details:
A 100 Ω.cm n-type FZ silicon wafer with a thickness of approximately 400 µm was split into
quarters. The growth and deposition of the ONO on all quarters were identical to the baseline,
except for the variable POA as detailed in Figure 4.1b. The wafers were loaded at 700 ˚C and
ramped up to 1000 ˚C in O2. After reaching 1000 ˚C, the wafers were annealed in N2 for 0, 15
and 30 minutes and then cooled in N2. A control quarter without N2 annealing was loaded at
700 ˚C, ramped up to 1000 ˚C and ramped down to 700 ˚C in O2.
Results and discussion:
The experimental results shown in Figure 4.3 indicate there were no improvements to J0s or τeff
as the duration of the POA increases. Instead, J0s increased slightly from 0.2 to 0.5 fA/cm2 and
τeff_1015 decreased slightly from 30 to 25 ms. It can be concluded that for these undiffused ONO
wafers, POA is not beneficial, and can even cause an increase in recombination.
0 10 20 30O2
0
10
20
30
40
50
60
τeff.max
τeff_10
15
J0s
N2 Annealing (minutes)
τ eff
(ms)
Ramp down in O2
0.0
0.4
0.8
1.2
1.6
2.0 J
0s (
fA/c
m2)
Fig. 4.3: Minority carrier lifetimes and J0s measured for ONO wafers with different thermal SiO2 annealing times in N2 or O2 ramp down
The source of the reduced lifetime and passivation quality may be caused by metal impurity
contamination (e.g. Fe, Cr, Ni) during the N2 anneal [197]. Alternatively, the reduced lifetime
may be due to the re-introduction of vacancy-like defects back into the silicon bulk during the
N2 anneal, as demonstrated by Abe [198].
41
Figure 4.3 also shows that when ramp-down is performed in O2, the surface passivation is
slightly worse as compared to ramp-down performed in N2 (0.8 fA/cm2 instead of 0.2 fA/cm2);
however, the passivation exhibits a higher measured τeff.max (55 ms instead of 43 ms). This
observation reinforces the suggestion that using only ambient N2 during annealing contributes
to the formation of bulk defects. These findings are consistent with the work of Grant et al.
who demonstrated that vacancy related intrinsic defects (incorporated during FZ ingot growth)
can be annealed out during high-temperature oxidation, thereby improving the bulk lifetime of
FZ silicon [199, 200].
While an exact mechanism for bulk degradation resulting from the POA has not yet been
determined, with no POA (O2 rampdown) or 0 min POA (N2 rampdown), the performance of
a solar cell will be similar with operating conditions at ∆n ~1015 cm-3. Thus, the use of POA
under these conditions does not lead to any observable benefit from a device perspective.
4.4 Deposition conditions of PECVD for ONO stack
Stacking an additional dielectric layer onto the surface passivation layer of a solar cell is used
to increase the efficiency by improving the surface passivation, electrical isolation of the metal
contact and for ARC properties. The Al2O3 and SiNx stacked onto thermal SiO2 in some solar
cell designs improve the surface passivation by providing additional field-effect passivation
and hydrogenation of the Si-SiO2 interface [201].
This section initially investigates the surface passivation behaviour of the different dielectric
stacks of SiOx (OO), SiNx (ON) and SiNx and SiOx (ONO) onto thermal SiO2. The investigation
continues the development for the ONO stack by examining the deposition conditions for the
PECVD SiNx and SiOx layers. The investigations are shown in flowcharts as presented in
Figures 4.2 to 4.4 with the details described in the following subsections.
42
Fig 4.4: Flow chart detailing the deposition of the PECVD SiOx and SiNx on thermal SiO2 to form the SiO2-SiOx (OO), SiO2-SiNx (ON) and SiO2-SiNx-SiOx (ONO) stacks.
Forming Gas Anneal 400 ᵒC
Planar 100
Thermal Oxidation and nitrogen annealing
at 1000 ᵒC
PECVD SiNx
400 ᵒC PECVD SiOx
250 ᵒC
PECVD SiOx
250 ᵒC
Positive Corona Charging
Various PECVD dielectric stack on thermal SiO2
ONO ON OO Control
43
Fig 4.5: Flow chart detailing variations in each layer (relative to the baseline) to establish the best passivation conditions for PECVD SiNx. (a) The baseline procedure is represented by the white boxes, while variations to the gas flow ratio of SiH4 and NH3 are shown in the blue boxes. (b) The variations to the deposition temperature of SiNx (shown in green box). (c) The variation to chamber pressure of SiNx (shown in orange box).
Planar 100
Planar Rantex
Planar 111
TMAH TMAH and IPA
Thermal Oxidation and nitrogen
annealing at 1000 ᵒC
PECVD Silicon Nitride Deposition Temperature:
250 – 550 ᵒC
PECVD Silicon Oxide 250 °C
Forming Gas Anneal 400 °C
Positive Corona Charging
Embedding Charges Forming Gas Anneal 400 °C
(b) Deposition temperature of SiNx
Planar 100
Thermal
Oxidation
at 1000 ᵒC
and ramp
down in
nitrogen
PECVD Silicon Oxide 250 ᵒC
Forming Gas Anneal 400 ᵒC
Positive Corona Charging
Embedding Charges Forming Gas Anneal 400 ᵒC
(a) Gas ratio of SiNx
PECVD Silicon Nitride Gas Flow Ratio: SiH4: 8 - 24 sccm
NH3: 20 - 4 sccm
Planar 100
Thermal Oxidation and nitrogen
annealing at 1000 ᵒC
PECVD Silicon Oxide 250 ᵒC
Forming Gas Anneal 400 ᵒC
Positive Corona Charging
Embedding Charges Forming Gas Anneal 400 ᵒC
(c) Chamber pressure of SiNx
PECVD Silicon Nitride Chamber Pressure: 600 - 1000 mTorr
Thermal
Oxidation
at 1000 ᵒC
and ramp
down in
oxygen
44
Fig 4.6: Flow chart detailing variations in the process for each layer (relative to the baseline) to establish the best passivation conditions for PECVD SiOx. (a) The baseline procedure is represented by the white boxes, while the variations to the gas flow ratio for SiH4 and N2O are highlighted in blue. (b) The variations to the deposition temperature of SiOx are highlighted in green.
Planar 100, quartered
Thermal Oxidation and nitrogen
annealing at 1000 ᵒC
PECVD Silicon Oxide
Gas Flow Ratio
SiH4: 4 - 40 sccm
N2O: 679 - 715 sccm
Forming Gas Anneal 400 ᵒC
Positive Corona Charging
Embedding Charges
Forming Gas Anneal 400 ᵒC
(a) Gas ratio of SiOx
PECVD Silicon Nitride 400 °C
Planar 100, quartered
Thermal Oxidation and nitrogen
annealing at 1000 ᵒC
PECVD Silicon Oxide
Deposition Temperature:
200 – 400 ᵒC
Forming Gas Anneal 400 ᵒC
Positive Corona Charging
Embedding Charges
Forming Gas Anneal 400 ᵒC
(b) Deposition temperature of SiOx
PECVD Silicon Nitride 400 °C
45
4.4.1 PECVD dielectric stack on the thermal oxide
As previously discussed in Chapter 2, the PECVD SiNx stack onto thermal SiO2 is known to
provide an abundance of hydrogen, which help to passivate the dangling bonds of the Si-SiO2
interface and positive charges to create field-effect passivation [202].
The PECVD SiOx stack on thermal SiO2 has been reported to reduce the Dit of the Si-SiO2
interface after alneal (annealing in the presence of Al) with little change to the charge density
[192]. However, most of the hydrogenation sources from alneal is thought to be from FGA.
In this section, the OO, ON and ONO stacks, as well as the control thermal SiO2, were
examined.
Experimental details
A 100 Ω.cm n-type FZ silicon wafer with a thickness of approximately 400 µm was cleaved
into quarters. The growth and deposition of the ONO on one of the quarters was identical to
the baseline, except the wafer was not subjected to further annealing after corona charging.
Two other quarters with the baseline thermal SiO2 had either PECVD SiNx (ON stack) or SiOx
(OO stack) deposited. The PECVD SiNx and SiOx were similar to the baseline process. The
control quarter was not subjected to any PECVD deposition. No annealing was performed on
any sample after positive corona charging. The sequences of each process are illustrated in
Figure 4.4.
Results and discussion
The effective lifetimes of deposited dielectric OO, ON and ONO stacks and a control wafer
with only thermal SiO2 are plotted in Figure 4.7. Before corona charging, the measured surface
passivations of the ON and ONO dielectric stacks showed very similar lifetimes across the
measured excess carrier densities (∆n) range. The control thermal SiO2 passivation had the
lowest lifetime, and the OO passivated stack lifetime was between the thermal SiO2 and SiNx
capped (ON and ONO) wafers. This initial observation indicates that the SiNx capped onto
thermal SiO2 is beneficial to improve the surface passivation.
46
1013
1014
1015
1016
0
10
20
30
40
1013
1014
1015
1016
0
10
20
30
40
Thermal Oxide
OO
ON
Eff
ective
Life
tim
e (
ms)
Excess Carrier Density (cm-3)
ONO
(a) (b)
OO
Thermal Oxide
OO
ON
Eff
ective
Life
tim
e (
ms)
Excess Carrier Density (cm-3)
ONO
Fig 4.7: Lifetime curves for the PECVD SiOx, SiNx and SiNx-SiOx deposited on thermal SiO2 to form OO, ON and ONO dielectric stacks (a) before and (b) after positive corona charging.
The various dielectric stacks and the control wafer all received additional positive corona
charges at the surface to induce the field-effect passivation. All of the passivation stacks
including the control thermal SiO2 passivation layer, were positively corona charged, till no
significant improvement was observed across measured lifetime curves. The corona charges
measured with a Kelvin probe were >3 × 1012 cm-2, assuming dielectric constants for the
thermal SiO2, PECVD SiNx and SiOx were 3.9, 7.0 and 5.0, respectively [203, 204]. The surface
passivations for all dielectric stacks improved with additional positive corona charges, as
plotted in Figure 4.7b. Two sets of lifetimes were observed, the first set with the ON and ONO
stacks and the second set with the OO and only the thermal SiO2 passivated wafer. Each of the
two different passivation schemes on each set had similar lifetimes across the measured range
of ∆n.
Based on these results, the higher lifetime first observed in Figure 4.7a for the OO stack relative
to the thermal SiO2 is most likely due to charges within the SiOx film. This is evidenced by
further corona charging as shown in Figure 4.7b, which improves the thermal SiO2 and OO
stack to a near identical surface passivation due to the addition of charge induced field-effect
passivation, suggesting otherwise equivalent chemical passivation. However, the measured
lifetimes of the corona charged thermal SiO2 and OO stack passivations are both lower
compared to wafers with SiNx. The key hypothesis in the improved lifetime seen on the SiNx
47
wafers is that they benefit from the hydrogenation of the Si-SiO2 interface, which was
introduced during the PECVD SiNx deposition and subsequent FGA steps.
Therefore, the deposition of PECVD SiNx onto thermal SiO2 is crucial. It further improves the
surface passivation compared to PECVD SiOx on thermal SiO2. The mechanism in which it
further reduces the surface passivation for PECVD SiNx is thought to be atomic hydrogenation
at the Si-SiO2 interface rather than molecule hydrogenation introduced with FGA [106].
4.4.2 Deposition conditions of PECVD SiNx in ONO stack
The important parameters during the deposition of PECVD SiNx are the radio frequency (RF)
incident power, gas flow ratio, chamber pressure and temperature. These parameters affect the
optical properties and the deposition rate of SiNx [117, 194, 205].
In the following sections, the effects of the SiH4:NH3 gas ratio, deposition temperature and
chamber pressure on the electrical characteristics of the deposited PECVD SiNx are discussed.
A similar RF power was used in each experiment set to adequately ignite the plasma while
reducing the possibility of plasma damage and ion bombardment [205]. For each experiment,
only one parameter was varied while the other deposition conditions were held constant.
Experimental details
The experimental details for the deposition of PECVD SiNx are divided into three subsections.
Silane to ammonia gas flow ratio - To investigate the influence of the SiH4:NH3 gas ratio on
SiNx, a 100 Ω.cm n-type FZ silicon wafer with a thickness of approximately 400 µm was split
into quarters. The growth and deposition of an ONO stack on all quarters were identical to the
baseline except for two processing variations: i) the growth of thermal SiO2 and ii) the
SiH4:NH3 gas ratio.
For thermal oxidation, experiments were performed on wafers under two conditions. Under the
first set of conditions, POA with N2 ramp down was performed. The wafers were loaded at 700
˚C and ramped to 1000 ˚C in O2. After reaching 1000 ˚C, the supply of O2 was switched to N2
while cooling to 700 ˚C. The second set of conditions were wafers without POA. The wafers
48
were loaded at 700 ˚C, ramped up to 1000 ˚C and ramped down to 700 ˚C while maintaining
in O2 ambient
In the second variation, the gas ratio of SiH4:NH3 was varied between 4 to 22 sccm. The
deposition time was varied to maintain the SiNx thickness under different gas flow ratios. For
antireflective purposes, the SiNx and SiOx thicknesses of 50 ± 3 nm and 90 ± 5 nm, respectively,
were maintained, as outlined in the baseline procedure. The performed investigation is shown
in the flowchart presented in Figure 4.5a.
Deposition temperature - To investigate the influence of the SiNx deposition temperature,
several FZ and Czochralski (Cz) n-type 100 Ω.cm silicon wafers featuring different surface
conditions were used: chemically polished FZ 100 planar, chemically textured FZ using a
TMAH and isopropanol (IPA) solution mixture to form rantex and mechanically polished Cz
111 planar surfaces. The wafer thicknesses for the 100 and 111 planar and the rantex
surfaces were measured to be approximately 400, 420 and 380 µm, respectively. The growth
and deposition of the ONO stack on all wafers was identical to the baseline, except for the
PECVD SiNx deposition temperature, which varied between 250–550 ˚C, as shown in Figure
4.5b. The deposition time was varied to maintain the SiNx thickness at different deposition
temperatures (as temperature increased, the deposition rate decreased and the refractive index
n632 increased from 1.9 to 2.0 [205]).
Chamber pressure - To investigate the influence of the chamber pressure on the deposition
of SiNx, a 100 Ω.cm n-type FZ silicon wafer with a thickness of approximately 400 µm was
split into quarters. The growth and deposition of the ONO stack on all quarters were identical
to the baseline, except for the chamber pressure, which varied between 600 to 950 mTorr, as
shown in Figure 4.5c. The deposition time was varied to maintain a similar SiNx thickness
across the different chamber pressure conditions.
Results and discussion
The results of each condition are discussed in the following subsections. The dependence of
the surface recombination, charge density and optical properties of the PECVD SiNx on the
various deposition parameters are shown in Figure 4.8.
49
109
1010
1011
1012
100
101
ramp down O2
ramp down N2
τ eff (
ms)
(a) (c) (b)
τeff_10
15
J0e
0
5
10
15
20
J0s (f
A/c
m2)
ON
O Q
eff
(cm
-2)
N2
O2
O2
N2
2:5 3:4 1:1 4:3 9:5 5:21.5
2.0
SiH4:NH
3 gas ratio
SiN
x r
efr
active
in
de
x (
n)
250 350 450 550
Temperature (°C)
600 700 800 900 1000
n
k
Pressure (mTorr)
10-4
10-3
10-2
10-1
100
k a
t 3
60
nm
Fig 4.8: The effect of the PECVD SiNx deposition conditions on the ONO dielectric stack with the measured effective lifetime τeff_10
15, extracted effective charge density with C-V and measured SiNx refractive index n632
with different (a) SiH4:NH3 gas ratios, (b) deposition temperatures and (c) chamber pressures. All lifetime measurements were performed on n-type 100 Ω.cm 100 silicon wafers.
Silane to ammonia gas flow ratio - The measured lifetimes and J0s of the SiH4:NH3 ratio
shows two trends in Figure 4.8a. First, the surface passivation deteriorates with an increased
SiH4:NH3 gas ratio in both thermal SiO2 conditions. Second, the N2 ramp down during thermal
oxidation has a slightly better J0s but poorer τeff_1015 as compared to the ramped down O2. To
further investigate this observation, the effective charge (Qeff) of the ONO dielectric was
50
determined using C-V measurements on low resistivity 1 Ω.cm n-type 100 silicon wafers.
The C-V measurements on the ONO stack with and without the N2-annealed thermal SiO2 as
shown in Figure 4.8a exhibit two trends. As the SiH4:NH3 ratio increased, the effective charge
density of the ONO stack with the N2-annealed thermal SiO2 decreased to as low as 6.9 × 109
cm-2. Secondly, higher Qeff were measured for SiNx n at ~1.94 (SiH4:NH3 gas ratio 1:1) and
above on thermal SiO2 without any N2 annealing.
The Qeff measured on the N2-annealed wafers declined steadily with the increasing SiNx n
above 1.91 as compared to O2 ramped down wafers having no obvious trend with the SiNx n.
Differences in both the annealing conditions may be due to reducing positive charges within
the thermal SiO2 when subjected to N2 annealing [30, 53, 57]. However, the charges measured
within the stack, which affect the field-effect passivation, showed no clear correlation with J0s.
The slightly lower lifetimes observed with the N2 ramp down wafers could be due to the
introduction of bulk defects with the N2 annealing, as similarly observed in Section 4.3.2.
The annealing conditions (O2 and N2 ramped down) for both wafers further proceeded with the
deposition of positive corona charging and FGA. The results shown in Figure 4.9 show
improvements in the surface passivation for a SiNx n of ~1.94 (SiH4 and NH3 gas ratio of 1:1)
and above. However, either slight degradations or no improvement was observed with wafers
below a SiNx refractive index of 1.94.
1.8 1.9 2.0 2.1 2.2 2.31
10
Orange: Before CC
Red After CC and FGA
SiNx refractive index (n)
τ eff
(ms)
0
5
10
15
20
J
0S
(fA
/cm
2)
1.8 1.9 2.0 2.1 2.2 2.3100
101
(b)
τeff_1015
J0s
τeff_1015
J0s
SiNx refractive index (n)
τ eff
(ms)
(a)
0
5
10
15
20
J0S
(fA
/cm
2)
Purple: Before CC
Blue: After CC and FGA
Fig 4.9: The different thermal oxide conditions with (a) O2 ramp down and (b) N2 ramp down on various SiNx refractive indexes with a measured lifetime at ∆n = 1015 cm-3 and surface recombination J0s.
51
Based on the results shown in Figure 4.9, the lifetime improves more significantly for the O2
ramp down compared with the N2 ramp down. This further supports the hypothesis that
subjecting wafers to N2 annealing introduces bulk defects. The relatively constant J0s observed
with SiNx refractive indexes n632 of 1.94 to 2.21 for the O2 ramp down wafers may suggest
improvements in the bulk with increases in the SiNx refractive index while within this range.
This was not observed with the N2 annealed wafers as the bulk defects may have limited the
bulk lifetime.
Deposition temperature - The measured lifetime and J0s for deposition temperatures from 250
to 550 ˚C shows two trends in Figure 4.8b. First, the surface recombination decreased with the
rising temperature within the range of 250–400 ˚C. Second, an opposing trend is observed
where the surface recombination increased as the deposition temperature exceeded 400 ˚C.
Further investigations show that the measured Qeff on low resistivity 1 Ω.cm n-type 100
silicon wafers are relatively constant when below the deposition temperature of 400 ˚C.
Wafers with similar resistivities and different wafer crystallographic orientations and surface
morphologies were deposited with ONO using SiNx deposition temperatures from 250–550 ˚C.
The plots in Figure 4.10 show similar results were observed with decreased surface
recombination over the range of 250–450 ˚C and increased surface recombination when the
deposition temperature exceeded 450 ˚C. It should be noted that 100 wafer measured J0s <0
fA/cm2 at PECVD SiNx deposition temperatures of 400 ˚C before and after corona charging.
The measured negative J0s might be either due to injection dependent or an underestimation of
τbulk with Kane and Swanson method [184].
A decrease and increase of the surface recombination with temperature were similarly observed
for a single PECVD SiNx passivation layer on silicon [75, 117], suggesting that the deposition
temperature of SiNx strongly influences the surface recombination, either as a stack on top of
the thermal SiO2 or as a single passivation layer. The lowest J0s (highest lifetime) was achieved
when the deposition temperature was within the range of 350-450 ˚C. A decrease in J0s with
the increasing deposition temperatures up to 400 ˚C suggests that either the density of electric
charges in the film increases or that the interface defect concentration decreases with
temperature. The trend is particularly noticeable for 111 and rantex wafers, which have
previously been found to exhibit higher Dit than 100 surfaces [44, 206, 207], even after a
FGA [44].
52
It is assumed that the trend for the Qeff measured on 1 Ω.cm n-type 100 silicon wafers is the
same for all ONO samples with different resistivities, crystallographic orientations and surface
morphologies. Therefore, the measured lifetime and surface recombination in Figures 4.10a-c
indicate that the decreased J0s with deposition temperatures up to 450 ˚C arises from a decrease
in the interface defect density, rather than an increase in the charge density within the ONO
stack. Although the mechanism for which the SiNx improves the surface passivation is not
unequivocal, the surface passivation from the SiO2, which improves after capping it with SiNx,
is most likely due to the hydrogenation and positive charges [91, 208, 209]. Another possibility
is that the hydrogen molecules and radicals generated during the deposition [86, 87] passivate
the dangling bonds at the Si-SiO2 interface [90-94], causing a reduction in the J0s. The literature
indicates that the common optimum temperature for hydrogenation using a hydrogen plasma
is 400 ˚C [93, 94], which agrees with our observations. Another source of hydrogenation could
be the deposition of SiNx followed by subsequent annealing, which may release hydrogen into
the bulk or Si-SiO2 interface [210-213].
To quantify the amount of hydrogen within the PECVD SiNx film, FTIR measurements were
performed on the PECVD SiNx layers to determine the concentrations of Si-H and N-H bonds
at 2150 and 3350 cm-1. Figure 4.10d plots the absorption rate over the PECVD SiNx thickness
[214] at different deposition temperatures rather than the absolute bond concentration values
[215]. It is thought that as the bond densities of Si-H ([Si-H]) and N-H ([N-H]) reduce with the
deposition temperature, the released hydrogen could passivate the silicon surface and result in
a lower interface defect density (the Dit could not be determined from the low and high-
frequency C-V measurements due to significant measurement uncertainty in the low-frequency
measurement). However, no clear dependence of J0s on the [Si-H] and [N-H] were found. These
findings are similar to those from Wan et al. for the PECVD SiNx passivation layer [117].
After the corona charging and annealing, the J0s decreased to below 20 fA/cm2 for all deposition
temperatures and wafer types. In fact, for planar 100 wafers, the J0s decreased to practically
0 fA/cm2 for temperature depositions across 300 to 400 ˚C. The J0s decreased the most after
corona charging for deposition temperatures below 400 ˚C. Little or no improvements in the
J0s were observed with deposition temperatures above 450 ˚C. The cause for the increased J0s
for deposition temperatures above 450 ˚C remains uncertain. However, it is possible that
dehydrogenation [216] or contamination via the rapid diffusion of contaminants could have
occurred [197].
53
250 300 350 400 450 500 550100
101
Temperature °C
(a)
0
4
8
12
16
20
Te
ff (
ms)
J0
s (
fA/c
m2)
250 300 350 400 450 500 550100
101
τeff_10
15 before CC FGA
τeff_10
15 after CC FGA
J0s
before CC FGA
J0s
after CC FGA
Temperature °C
0
10
20
30
40
50
60
70
80(b)
Te
ff (
ms)
J0
s (
fA/c
m2)
250 300 350 400 450 500 55010-1
100
101
Temperature °C
(c)
0
40
80
120
160
200
Te
ff (
ms)
J0
s (
fA/c
m2)
250 300 350 400 450 500 5501011
1012
(d) Planar 100O
NO
Qe
ff (
cm
-2)
CV Qeff
FTIR [Si-H] FTIR [N-H]
Temperature (°C)
104
105
FT
IR S
iNx:
[Si-
H]
| [N
-H]
Bo
nd
s (
%)
Fig 4.10: Measured effective lifetime τeff_1015 and surface recombination prefactor J0s for ONO stacks with
different SiNx deposition temperatures on (a) 100, (b) 111 and (c) rantex wafers. The τeff_1015 is measured at
∆n = 1015 cm-3 before and after corona charging and FGA. (d) Qeff of ONO stack and bond density in SiNx is plotted. The charge was measured using C-V measurement on a 1 Ω.cm n-type 100 silicon wafer, as outlined in Section 3.2. The absorption for the [Si-H] and [N-H] on SiNx was measured using FTIR.
Impact of crystal orientation on ONO passivation – The surface passivation for various
films has been shown to depend on the crystal orientation and surface morphology of the silicon
wafers [44, 122, 217]. For example, Baker-Finch et al. found that the effective upper limit of
surface recombination velocity (Seff.UL) at carrier density (∆n) of 1015 cm-3 on thermal SiO2 for
planar 111 to be higher than that for planar 100 with a ratio fO ≈ 4 [217]. The fO here
represents the surface recombination velocity (SRV) ratio of the surface passivation between
111 to 100 where the subscript O represents the orientation. Wan et al. found the surface
54
orientation to be less influential for PECVD SiNx with an fO ranging from 0.8 to 1.7 at ∆n =
1015 cm-3 [122]. The surface recombination on a rantex surface (which has 111 oriented
facets) is typically greater than for the planar 111 surface due to its higher surface area (√3
times larger) and possible stress-induced defects at concave and convex features [217, 218]. A
comparison of the surface recombination ratio between the corrected surface area of the rantex
to planar 111 is denoted as fV (where the subscript V is for vertices). Accounting for the
differences in the surface area, Wan et al. found that the SiNx passivation (n = 1.93) has a
higher Seff.UL for rantex over planar 111 with fV ≈ 2 [122]. In contrast, amorphous silicon has
fV ≈ 0.9 [122, 219].
In this work, the fO and fV were compared using the Seff.UL at ∆n = 1015 cm-3 instead of the J0s.
Two trends were observed with calculated fO for the lifetimes plotted in Figures 4.10a-b. First,
the calculated fO was observed to gradually decrease with the increasing SiNx deposition
temperatures up to 350 ˚C. Second, before the corona charging, the ONO stack with SiNx
deposited at 350 ˚C has an fO of ~2.6. After the corona charging and FGA of the ONO stack,
the fO reduced to ~1.2, making it behave more like PECVD SiNx than SiO2. Thus, whether the
crystal orientation was 100 or 111, the influence of surface defects on the ONO passivation
is comparable to PECVD SiNx [122, 219].
Similar trends of fO were observed for the calculated fV with the lifetimes plotted in Figures
4.10b-c. The calculated fV gradually decreased with increasing SiNx deposition temperatures
up to 350 ˚C. The area-corrected fV with the deposited SiNx at 350 ˚C before and after corona
charging showed a similar ratio of ~0.9. This is sufficiently close to unity to indicate that the
poorer ONO passivation on the rantex wafers compared to the planar 111 wafers is due to
their higher surface area, with a minimal impact from the convex and concave aspects of the
morphology.
Chamber pressure - For a direct PECVD configuration, a higher pressure reduces the mean
free paths for all gas species within the plasma chamber, decreases the electron temperature
and reduces the dissociation energies [220, 221]. This leads to a increase in the SiH4:NH3
radical ratio and results in a slightly higher refractive index with higher pressures [222], as
shown in Figure 4.8c.
The J0s shown in Figure 4.8c was found to slightly increase with pressures above 640 mTorr,
and the measure Qeff on the 1 Ω.cm n-type 100 silicon wafer were found to be relatively
similar (>1012 cm-2) across deposition pressures from 600 to 940 mTorr.
55
The observed increase in the surface recombination with increased pressure is postulated to be
due to a reduced dissociation of atomic hydrogen during the SiNx deposition. Interestingly,
Wan et al. observed a decrease in the single layer PECVD SiNx surface recombination with an
increasing chamber pressure on a dual-mode PECVD system from 0.02–0.4 mTorr [77]. An
increased chamber pressure on the dual-model PECVD system causes a decrease in the SiNx
refractive index. The findings from Wan et al. and our results suggest that changes in the
deposition pressure affect the surface passivation and that changes in the refractive index from
only varying the pressure may indicate the quality of the surface passivation.
No improvements in the J0s with the additional corona charging and annealing steps were
observed, as illustrated in Figure 4.11. This suggests that differences in the surface
recombination with chamber pressure are better associated with improvements at the Si-SiO2
interface as compared to the additional field-effect passivation with corona charging. The lower
lifetimes sometimes observed after corona charging and annealing are due to the
dehydrogenation at the Si-SiO2 interface or bulk, and the reduction of charges after annealing
[167, 178].
600 700 800 900100
101
τeff_1015 before CC FGA
τeff.max after CC FGA
J0s before CC FGA
J0s after CC FGA
Pressure (mTorr)
τ eff
(ms)
0
1
2
J
0s (f
A/c
m2)
Fig 4.11: Measured effective lifetimes and J0s on the ONO stacks with different chamber pressures for PECVD SiNx.
56
4.4.3 Deposition conditions for PECVD SiOx in the ONO stack
Like PECVD SiNx, the important parameters during the deposition of the PECVD SiOx are the
RF incident power, gas flow ratio, chamber pressure and temperature affect both the optical
properties and deposition rate of the PECVD SiOx [117, 194, 205].
In the following sections, the effects of the SiH4:N2O gas ratio and deposition temperature on
the electrical characteristics of the deposited PECVD SiOx will be discussed. A similar RF
power was used for each experiment and was set to adequately ignite the plasma while reducing
the possibility of plasma damage and ion bombardment [205]. Only one parameter was varied
for each experiment while the other deposition conditions were held constant.
Experimental details
The experimental details for the deposition of PECVD SiOx are divided into two subsections.
Silane to nitrous oxide gas flow ratio - To investigate the influence of the SiH4:N2O gas ratio
on the SiOx, a 100 Ω.cm n-type FZ Silicon wafer with a thickness of approximately 400 µm
was split into quarters. The growth and deposition of the ONO stack for all quarters were
identical to the baseline, except the SiH4 flow varied from 4 and 40 sccm and the N2O was
between 679 and 715 sccm, as shown in Figure 4.4a. The deposition time was varied to keep
the SiOx thickness similar at different gas flow ratios.
Deposition temperature - To investigate the influence of the SiOx deposition temperature, a
100 Ω.cm n-type FZ silicon wafer with a thickness of approximately 400 µm was split into
quarters. The growth and deposition of the ONO stack on all quarters were identical to the
baseline, except that the temperature varied between 200 and 400 ˚C, as shown in Figure 4.4b.
The deposition time was varied to maintain the SiOx thickness for different deposition
temperatures.
Results and discussion
The results for each of the conditions are discussed in the following subsections. Figure 4.12
plots the dependence of the surface recombination, charge density and optical properties for
PECVD SiOx on the various deposition parameters.
57
1010
1011
1012
100
101
τeff_1015
J0s
τ eff
(ms)
0
1
2
J0s (f
A/c
m2)
(b)
ON
O Q
eff (
cm
-2)
(a)
1:17 1:35 1:79 1:1791.0
1.5
2.0
SiH4:N
2O gas ratio
Re
fra
ctive
Ind
ex a
t 63
2 n
m (
n)
200 250 300 350 400
n k
SiOx Deposition Temperature
10-4
10-3
10-2
10-1
100
k a
t 3
60
nm
Fig 4.12: The effects of the PECVD SiOx deposition conditions on the ONO dielectric stack with measured effective lifetime τeff_10
15, the extracted Qeff determined using C-V measurements and the measured refractive index n with different (a) SiH4:N2O gas ratios and (b) deposition temperatures.
Silane to nitrous oxide gas flow ratio – The J0s and refractive index reduced with decreasing
SiH4:N2O gas ratio, as shown in Figure 4.12a. An initial explanation could be the decreased
effective charges that were measured on the ONO stack with increasing SiH4:N2O ratios.
However, this argument does not explain the results for a ratio of 1:179; the lowest J0s was
presented with measured charges that were similar to SiH4:N2O ratio of 1:35.
Further investigations were carried out on these wafers by corona charging and FGA, as shown
in Figure 4.13a. The results in Figure 4.13a show that a similar surface recombination for J0s
58
was achieved; however, the lifetimes of the wafers were lower compared with the initial
deposition conditions. This suggests that improvements to the interface with respect to the
SiH4:N2O ratio are more associated with reductions in the Dit of the Si-SiO2 interface rather
than the field-effect passivation from corona charges. The observed trends are postulated to be
caused by two factors. First is the stress induced from the SiOx deposited on top of the ON
stack, as this deposition may advance the release of hydrogen from SiNx to the passivation
dangling bonds at the Si-SiO2 interface or in the bulk. Second is the increasing density of SiOx,
as a denser SiOx capping layer may reduce the out-diffusion of hydrogen from the SiNx.
Deposition temperature – A slight improvement in the surface passivation was observed with
an increasing deposition temperature from 200 to 250 ˚C. However, no further improvements
were observed for deposition temperatures over 250 ˚C. Furthermore, there was no observed
trend with measured Qeff at different SiOx deposition temperatures on the ONO stack.
1.44 1.48 1.52 1.5610
0
101
(a)
J0s
τeff_1015
SiOx refractive index
τ eff (
ms)
Light: Initial
Dark: After CC FGA
1.44 1.48 1.52 1.56
0.0
0.2
0.4
0.6
0.8
1.0(b)
J0s
(fA
/cm
2)
200 300 40010
0
101
SiOx Dep Temperature (°C)
τ eff
(ms)
0
1
2
J
0S
(fA
/cm
2)
Fig 4.13: Measured effective lifetimes and J0s on the ONO stacks with different (a) refractive index n632 and (b) deposition temperatures on the ONO SiOx
The results of the corona charging followed by FGA on the wafers in Figure 4.13b shows an
overall marginal improvement in the surface passivation while exhibiting lower lifetimes.
Improvements in lifetimes observed from 200 to 250 C may be caused by stresses or a reduced
out-diffusion of hydrogen from the SiNx, as discussed in the previous section. No changes to
the surface recombination were observed at deposition temperatures greater than 250 ˚C. This
suggests a saturation point in which additional stresses or denser SiOx may not further improve
the ONO surface passivation.
59
4.5 Impact of corona charge and annealing on the ONO stack
As previously discussed in Chapter 2, corona charging for dielectric-coated silicon provides
field-effect passivation that can improve surface passivation either by accumulating or
inverting the concentration of free carriers at the surface [65, 166, 167, 173, 174].
In this section, we investigate the injection dependence of effective lifetime of corona charged
ONO stack, on a rantex surface, for various durations between 0 to 180 seconds. Furthermore,
we monitor the charge storage of ONO stack by examining the effective lifetime τeff_1015 of
ONO stack after corona charged and annealed over an extended period of two years.
Experimental details
To investigate the influence of corona charging, n-type 100 Ω.cm silicon wafer was textured
using a TMAH and IPA solution mixture which resulted in a thickness of approximately 350
µm. The growth and deposition of the ONO stack was identical to the baseline. The corona
charging was performed accumulatively with a symmetrical deposition of positive charges at
5 kV on both surfaces.
The impact of annealing after corona charging was measured over an extended period of two
years with fabricated process wafers in Section 4.4.2.
Results and discussion
Figure 4.14a shows a family of lifetime curves for an ONO rantex wafer subjected to different
positive charging durations. Each successive corona charge led to a significant improvement
in the effective lifetime at all excess carrier densities. However, the lifetime saturates with
corona charging beyond 120 seconds.
For comparison, Figure 4.14a shows the conversion from the effective lifetime to an upper
limit surface recombination velocity (Seff.UL) using Eq 3.18 and assuming an infinite bulk
lifetime. An extremely low Seff.UL of <1 cm/s was attained from a rantex silicon surface after
corona charging on the ONO stack for just 120 seconds.
It is preferred to quantify the surface recombination with J0s rather than using τeff and Seff.UL
due to its independence from the injection level when the surface is under accumulation [183].
60
Figure 4.14b plots the measured J0s (between 1014–1016 cm-3) after successive corona charging
of up to 180 seconds, where no further improvements were observed for τeff across carrier
injection.
There are two notable outcomes in Figure 4.14b. The first relates to the ‘linear’ fit for each
measurement, which indicates the surfaces are in accumulation, as would be expected from a
positively charged dielectric on an n-type silicon wafer [183]. This demonstrates that the
deposited surface charges (Qeff) that cause the accumulation of majority carriers at the Si-SiO2
interface (ns) are large enough to accurately extract J0s.
1013
1014
1015
1016
0
5
10
15
20
25
0 2x1015
4x1015
6x1015
0
50
100
150
200
250
300
180s
120s
60s
20s
10s
0s
fit τeff
τe
ff (
ms)
Excess carrier density (cm-3)
ONO Rantex
--
3.5
1.8
1.2
0.9
0.7
Up
pe
r lim
it S
RV
(cm
/s)
5.4 fA/cm2
44 fA/cm2
37 fA/cm2
21 fA/cm2
11 fA/cm2
5.9 fA/cm2
1/τ
eff -
1/τ
bu
lk (
intr
insi
c)(s
-1)
Excess carrier density (cm-3)
0s
10s
20s
60s
120s
180s
best fit J0s
(a) (b)
Fig 4.14: (a) ONO stack on a 100 Ω.cm n-type rantex silicon wafer that was corona charged for an increasingly cumulative period at 5 kV; the calculated upper limit SRV on the secondary y-axis scale is not to scale. (b) Line plots showing the best-fit
Secondly, the results clearly show a substantial reduction in J0s from 44 to ~5 fA/cm2 after
successive corona charging for up to 180 seconds. The additional corona charging caused an
increased ns, which reduced the recombination of minority carriers at the surface.
The deposition of the corona charging is not stable without further treatment. The deposited
charges can be removed by rinsing the wafers in isopropanol (IPA) [65, 167, 223]. The benefit
of a simple corona charge is, therefore, only temporary and would not provide a long-term
efficiency gain in finished devices. However, annealing corona-charged wafers have been
61
found to embed the surface charges into the dielectric [65, 167, 176]. To examine the stability
of the embedded charges into the ONO stack, the annealed ONO wafers from Section 4.4.2
(100, 111 and rantex wafers) were monitored over a two-year period under ambient
conditions. Figure 4.15 shows the results of the wafers before and after the corona charging,
illustrating the annealed corona-charged wafers after 400 C in FGA. From the measured values
of τeff_1015 and J0s shown in Figure 4.15, the corona-charged wafers were observed to have a
slight increase in the surface recombination after annealing due to their reduced overall charges
or stresses caused by further annealing of the stack [65, 167]. It is evident that the passivation
scheme is stable over a two-year period (stored indoors) and is not dependent on the surface
condition of each wafer.
0 200 400 600 8000
5
10
15
20
25
30 Before CC
After CC
Annealed CC
Before and
after CC
J0s 111
J0s Rantex
τeff_1015 Rantex
τeff_1015 111
τeff_1015 100
Days
τ eff (
ms)
0
5
10
15
20
J0s
(fA
/cm
2)
Fig 4.15: Effective lifetime measured at ∆n = 1015 cm-3 and J0s for the corona-charged wafers plotted after FGA annealing and stored in ambient conditions for up to two years. No data plots are displayed for the J0s of the 100 wafer, as the extracted values were lower than 0 fA/cm2. The wafer thicknesses of the 100 planar, 111 planar and rantex surfaces were measured to be approximately 400, 420 and 380 µm, respectively.
Kelvin probe measurements were performed after the corona charging showed positive surface
charges of 4.3 × 1012 cm-2 for an n-type planar 1 Ω.cm silicon wafer. The C-V measurements
performed before and after the corona charging (with annealing to embed the charges), showed
an increase in the effective charge Qeff from approximately 7 ± 2 × 1011 to 2.4 ± 0.3 × 1012 cm-
2. The measured increase in the effective charge indicates that the deposited surface corona
charges are driven into the ONO dielectric stack after subsequent annealing.
62
4.6 ONO surface passivation on various wafer resistivities and surfaces
A summary of the principal results obtained from this study on the ONO passivation scheme
is compiled in Table 4.1. The table includes details of the wafer types, thicknesses and surface
morphologies. The conditions for thermal SiO2, PECVD SiNx and SiOx were compiled to
establish an ONO stack with optimised surface passivation. The wafers featuring the ONO
surface passivation were processed as follows:
(i) Ramp up from 700 to 1000 ˚C and the subsequent ramp down to 700 ˚C, all in O2, with
no subsequent POA in N2 (12 ± 2nm).
(ii) 400 C PECVD SiNx (50 ± 3 nm) with a SiH4:NH3 gas ratio of 1:1 and chamber pressure
of 650 mTorr.
(iii) 250 ˚C PECVD SiOx (90 ± 5 nm) with a SiH4:N2O gas ratio of 1:79.
(iv) Anneal the ONO stack in FG at 400 ˚C for 30 minutes.
(v) Deposit positive corona charge at 5 kV onto the ONO passivated wafers for 120 seconds.
(vi) Anneal the charged ONO wafers in forming gas at 400 ˚C for 30 mins to embed and
stabilise the corona charges.
1013
1014
1015
1016
1017
10-5
10-4
10-3
10-2
10-1
100
1013
1014
1015
1016
10-3
10-2
10-1
100 (b)
Richter et al.
Trupke et al.
Dingermans et al.
Hacker et al.
Kerr et al.
Veith-Wolf et al.
Wan et al.
Grant et al.
Niewelt et al.
Steinhauser et al.
Bonilla et al.
Kho et al. (this work)
τ eff (s)
Dopant Concentration (cm-3)
(a)
86.7 Ω.cm
1.77 Ω.cm
1.07 Ω.cm
τ eff (
s)
Excess Carrier Density (cm-3)
0.50 Ω.cm
1.07 Ω.cm
1.50 Ω.cm
86.7 Ω.cm
Intrinsic limit
0.50 Ω.cm
n-type
Fig 4.16: (a) Maximum lifetime as a function of the dopant concentration measured at 300 K on an n-type silicon wafer together with data from the literature ([17, 64, 140, 224-230]). (b) ONO passivation with a range of n-type silicon resistivities compared to the intrinsic limits with a parameterised Auger [17] and radiative recombination [181] (lines).
63
Figure 4.16a plots the maximum effective lifetime measurements published in the literature on
n-type silicon wafers. This comparison demonstrates that the lifetime of samples with the ONO
passivation exceeds the lifetimes for the various other passivation schemes as it achieved a
lifetime of 170 ms on a 100 Ω n-type silicon wafer. Figure 4.16b shows the effective lifetime
measurements for three different n-type resistivity wafers with ONO passivation, which
exceeds the intrinsic recombination lifetime model [17]. This not only demonstrates the
outstanding passivation quality of ONO stacks, but it also highlights the necessity of revising
the parameterised intrinsic limits for silicon.
Table 4.1. Measured lifetime parameters for a variety of n-type wafers with ONO, NO and SiNx passivations.
Note: J0s is extracted by fitting injection levels from 1 to 5 x 1015. Values are reported at 300 K, where ni is 9.7 × 109 cm-3, τeff_10
15 is at ∆n = 1015 cm-3, and τeff_max is at ∆n from 1013 to 1016 cm-3. Chem. P: Chemical Polish Rantex: Random texture a,b SiNx Deposition technique: PECVD (Roth & Rau AG, system AK400) b SiNx deposited onto silicon wafer followed by PECVD SiOx [14]. *Wafer resistivity measured at the University of Oxford using the Hall Coefficient measurements after thermal processing [231]. *Wafer was not subjected to step (iv) in Section 4.6 All other wafer reported resistivities were based on dark conductance measurements using the QSSPC before any thermal processing.
ρbulk
(Ω·cm)
Type Crystal
Lattice
w
(µm)
Surface Passivation
Layer
τeff_1015
(ms)
τeff_max
(ms)
J0s
(fA/cm2)
0.50 CZ 100 155 Chem. P ONO 3.2 3.7 -
1.07 CZ 100 272 Chem. P ONO 12.4 15.1 -
1.77* FZ 100 398 Chem. P ONO 19.3 25.5 -
2.71 FZ 100 228 Chem. P ONO 18.6 20.6 -
4.97* FZ 100 388 Chem. P ONO 34.9 43.7 0.2
8.93* FZ 100 181 Chem. P ONO 28.0 38.5 0.8
86.7* FZ 100 291 Chem. P ONO 72.5 170 0.3
142 FZ 100 382 Chem. P ONO 44.9 84.6 -
115 FZ - 350 Rantex ONO 18.0 42.6 4.3
105 FZ - 351 Rantex a SiNx 10.1 12.9 9.8
2.96 FZ - 250 Rantex bNO 4.3 4.5 4.7
64
4.7 Chapter summary
This chapter presents a detailed study for the surface passivation of an ONO dielectric stack on
undiffused n-type silicon wafers. The study is divided into four main areas: thermal SiO2,
PECVD SiNx, PECVD SiOx and corona charging with subsequent annealing.
The initial thermal SiO2 grown on the silicon surface provides good chemical surface
passivation. A thermal SiO2 thickness of 7–15 nm was sufficient to provide excellent surface
passivation, while the introduction of POA with N2 was deemed unnecessary. The POA with
N2 was found to reduce positive charges within the thermal SiO2 and contributed to bulk defects
or contamination.
The second layer of the deposited SiNx improves surface passivation by hydrogenation the Si-
SiO2 interface and induces a field effect passivation with positive charges. The deposition
conditions for the investigated PECVD SiNx include the deposition temperature, SiH4:NH3 gas
flow ratio and the chamber pressure. It was found that the optimum deposition temperature was
from 350–450 ˚C on planar orientated 100 and 111 and rantex wafers. The increase in the
SiH4:NH3 gas ratio was observed to have fewer positive charges in the SiNx. Also, the lowest
surface recombination was observed at a chamber pressure of 650 mTorr.
The third layer capping PECVD SiOx indicates that it traps and embeds the positive corona
charges while improving the overall ARC properties of the ONO stack in air, which will be
discussed further in Chapter 6. The deposition conditions for the investigated PECVD SiOx
includes the SiH4:N2O gas flow ratio and the deposition temperature. It was revealed that the
SiH4:N2O gas ratio of 1:179 and deposition temperatures above 250 ˚C provided the lowest
surface recombination.
The corona charges slowly dissipated in air on the untreated dielectric surfaces. However, by
annealing the corona charged ONO surfaces at 400 ˚C in a forming gas, the charges were
deemed stable for up to two years under indoors conditions. For most occasions, the deposition
of corona charges and further annealing improved the surface passivation and embedded the
charges into the dielectric stack. However, degradation of the surface from corona charging
may occur due to ion bombardment at the Si-SiO2 interface. Therefore, the amount of corona
charging and subsequent annealing should be optimised to avoid damaging the Si-SiO2
interface.
65
Excellent surface passivation and record-breaking lifetimes for silicon wafers featuring ONO
passivation were demonstrated, proving that this passivation scheme is amongst the best for
dielectric films. Surface passivation on planar surface of 100 and 111 wafer orientation
achieved J0s ≤1 fA/cm2 and random texture surface J0s <5 fA/cm2. As such, these could find
applications in high-efficiency silicon solar cells.
66
Chapter 5
Passivation of ONO on diffused surfaces
5.1 Introduction
This chapter focuses on using the ONO stack to achieve excellent surface passivation for
silicon substrates with diffused surfaces by optimising their electrical properties. The primary
use of diffusion is to form a p-n junction in semiconductor devices which enables the specified
carriers to be separated and ‘collected’ at the junction. Other uses of diffusion include reducing
the surface recombination via field-effect passivation, lowering the contact resistivity between
metal and silicon by reducing the barrier width through field emissions and improving the
lateral flow of carriers within a solar cell [232]. This chapter investigates ONO passivation on
boron and phosphorus-diffused surfaces, which is an essential study to achieve high-efficiency
silicon solar cells.
Based on the experimental results presented in Chapter 4, an ONO stack with select processing
conditions was implemented on boron and phosphorus-diffused surfaces. Firstly, the basic
wafer preparation procedure, such as saw damage removal, RCA cleaning, diffusion processes,
etc., is briefly described. Secondly, the impacts of the thermal SiO2 layer (thermal SiO2
thickness and post-oxidation annealing), PECVD SiNx film deposition conditions and post-
treatments on the surface passivation of diffused silicon substrates were studied and evaluated
and are presented in the following sections.
5.2 ONO baseline procedures on diffused surfaces
High resistivity n-type 100 Ω.cm silicon wafers with a 100 orientation were either etched in
TMAH for 10 minutes at 85 ˚C to remove saw damage or chemically textured to form rantex
surface using solution mixture of TMAH and isopropanol (IPA). Planar and rantex wafers after
the etching had thicknesses of ~400 µm and ~350 µm respectively. The wafers were
subsequently cleaned using the standard RCA process and dipped in a 1% hydrofluoric (HF)
solution until the surfaces became hydrophobic.
67
Thermal diffusion was performed in a Tempress 5-inch quartz tube system with wafers loaded
in O2 at 700 ˚C. For phosphorus diffusion, wafers were ramped to 775 ˚C and diffused for 25
minutes with gas flow rates of 130 sccm for the N2 carrier gas with phosphoryl chloride (POCl),
65 sccm for O2 and 2.5 slm for N2 diluent gas. After diffusion, the wafers were ramped down
to 700 °C and unloaded in O2. For the boron diffusion, the wafers were ramped up to 920 ˚C
and diffused for 40 minutes with flow rates of 18 sccm of the N2 carrier gas with boron
tribromide (BBr3), 18 sccm for O2 and 2.5 slm for N2 diluent gas After diffusion, the wafers
were ramped down to 700 °C in O2 and unloaded. The diffused wafers with phosphosilicate
glass (PSG) and borosilicate glass (BSG) layers were removed in 5% HF solution, cleaned
using the standard RCA process and dipped in a 1% HF solution to prepare for the thermal
oxidation.
The growth of thermal SiO2 was similar to those in the baseline procedure in Section 4.2. The
thermal SiO2 thickness was measured using an ellipsometer on the 100 orientated planar
surface with a light phosphorus diffusion of 400–500 Ω/ was 15 ± 1 nm, and was 17 ± 2 nm
for a boron diffusion of ~160 Ω/ (JA Woollam M2000D) [62]. The rantex wafer was assumed
to be similar to the measured phosphorus-diffused 111 wafer with a thickness of 16 ± 1 nm.
The PECVD SiNx and SiOx layer deposited on top of the thermal SiO2 via PECVD (using an
Oxford Instruments PlasmaLab 100) was identical to the procedure given in Section 4.2.
Following the PECVD process, all wafers were subsequently FGA at 400 ˚C in a quartz tube
furnace for 30 minutes.
The diffused wafers with symmetric ONO stacks were corona charged on both the front and
rear surfaces using the conventional setup [164]. Positive corona charging was performed on
the phosphorus diffused surface at 5.5 kV for 120 seconds, whereas negative corona charging
was performed on boron diffused surfaces at 6 kV for 100 seconds.
5.3 Surface passivation of ONO stack on phosphorus and boron diffusion
The net emitter recombination current density pre-factor (J0e) for diffused silicon was
determined based on the quality of the surface passivation, the surface dopant concentration
and the diffusion profile. This section investigates the impact of the ONO stack on the J0e for
different diffusion profiles.
68
Experimental details
Phosphorus and boron-doped silicon substrates with both planar and rantex surfaces were
fabricated as described in the baseline procedures of Section 5.2, except the diffusion
temperature for phosphorus and boron) were varied between 770 to 800 ˚C and 890 to 940 ˚C
respectively. The formation of the ONO stack and deposition of the corona charges onto the
wafers were similar to the baseline procedures detailed in Section 5.2.
Results and discussion
The measured J0e for phosphorus and boron diffused wafers with the ONO stack are presented
in Figures 5.1a-b, respectively. Two trends were observed in Figure 5.1a. First, the J0e for the
phosphorus diffused wafers increased with lower sheet resistances. Second, positive corona
charging reduced the recombination of phosphorus diffused wafers with ONO passivation
stacks. Prior to corona charging, the J0e for the passivated ONO stack on rantex surface (grey
filled triangle symbols) was comparable to that for the rantex alnealed thermal SiO2 (grey
hollow triangle symbols). After positive corona charging of phosphorus doped silicon substrate,
the surface passivation improved significantly on the rantex surfaces, whereas only slight
improvements were observed on the ONO planar surfaces. The lowest phosphorus diffused
sheet resistivity of 520 Ω/ on planar and 610 Ω/ on rantex wafers with ONO stacks and
positive corona charges achieved J0e of 0.5 fA/cm2 and 1.9 fA/cm2, respectively.
Large variations in the J0e were found on boron diffused silicon wafers with ONO surface
passivation prior to corona charging, as shown in Figure 5.1b. No obvious trends were observed
with the ONO passivation as the J0e values ranged from 20 to 34 fA/cm2 across sheet
resistivities from 125 to 180 Ω/. The ONO surface passivation quality is comparable to the
thermal SiO2 data from Kerr et al. [233]. As PECVD SiNx generally exhibits positive charges,
which are undesirable with boron diffused surfaces, the boron diffused ONO stack was
negatively corona charged with a -6 kV bias [234, 235]. The negative charges substantially
reduced the ONO surface recombination and were found to be comparable to the surface
passivation of the Al2O3 layer and the a-Si/SiNx stack, both of which are typically regarded as
among the best passivations available for boron diffused surfaces [236, 237].
69
0 100 200 300 400 500 600
100
101
102
0 50 100 150 200 250100
101
102
Rantex Alneal - M.J. Kerr
Rantex ONO
Pos. CC Rantex ONO
Planar ON - M.J. Kerr
Planar ONO
Pos. CC Planar ONO
J0e (
fA/c
m2)
Sheet Resistivity (Ω/ )
(a)
SiO2 - M.J. Kerr
aSi/SiNx - M. Kessler
Al2O
3 - J. Schmidt
ONO
Neg CC. ONO
J0e (
fA/c
m2)
Sheet Resistivity (Ω/ )
(b)
Fig 5.1: Compilation data for different types of passivation schemes comparing the J0e of (a) planar and rantex phosphorus diffused [194, 233] and (b) planar boron diffused samples [236, 237].
The J0e for the ONO passivated phosphorus and boron-doped silicon wafers increased with
lower sheet resistivities due to an increased Auger recombination within the diffusion profile
[18, 238]. The correct polarity of charges with additional corona charging (positive charges on
phosphorus and negative charges on boron) improved both diffused surfaces as it accumulates
majority carriers from the diffusion towards the surface. The low J0e attained on both diffusions
after corona charging demonstrates that the ONO stacks can provide good chemical passivation.
5.4 Thermal oxide growth conditions in an ONO stack on diffused
surfaces
Varying the thermal SiO2 growth conditions changes the surface passivation quality, surface
dopant concentration and the diffusion profile. During the oxidation process, the dopant
redistributes near the Si-SiO2 interface. The growth of thermal SiO2 tends to deplete the boron
dopants at the surface whereas phosphorus dopants tend to pile up. The post-oxidation
annealing (POA) with N2, however, drives the diffusion dopants deeper into the silicon.
This section investigates the effects of the thermal SiO2 thickness and duration of the POA on
the passivation quality of the ONO stack for both boron and phosphorus diffusions. The
conditions investigated in this section are presented in flowchart Figure 5.2 with the details
described in the following subsections.
70
Fig 5.2: Flow chart detailing the process variations to each layer (relative to baseline) to establish the best passivation conditions for the (a) thermal SiO2 thickness and (b) POA.
5.4.1 The effect of varying the thermal oxide thickness on the diffused surfaces
The difference in the segregation coefficient of silicon and thermal SiO2 for diffused boron or
phosphorus atoms causes the dopant concentration to either deplete or accumulate on the
silicon surface.
As diffusion introduces additional complexities compared with undiffused wafers, this section
examines the effect of varying the thermal SiO2 thickness on the electrical performance of the
ONO stack for similar diffused wafers.
(a) Thermal SiO2 thickness (b) Post-oxidation N2 annealing
Phosphorus Diffusion 780 ˚C
Thermal
Oxidation 850 °C
PECVD SiNx 400 °C
PECVD SiOx 250 °C
FGA 400 °C Boron Diffused
Wafers
Thermal
Oxidation 900 °C
Thermal
Oxidation 950 °C
Thermal
Oxidation 1000 °C
N2 annealing 1000 °C
Planar 100 and rantex
quartered
Boron Diffusion
940 ˚C
Planar 100
quartered
FGA 400 °C Phosphorus Diffused
Wafers
Positive Corona
Charging 5 kV Negative Corona
Charging 6 kV
PECVD SiOx 250 °C
Control
Thermal
Oxidation 1000 °C
Ramp down in O2
PECVD SiNx 400 °C
Thermal Oxidation 1000 °C
Anneal and ramp down N2
Phosphorus Diffusion 780 ˚C
Planar 100 and rantex
quartered
Boron Diffusion
940 ˚C
Planar 100
quartered
FGA 400 °C Boron
Diffused Wafers
FGA 400 °C Phosphorus Diffused
Wafers
Positive Corona
Charging 5 kV Negative Corona
Charging 6 kV
71
Experimental details
To investigate the impact of the thermal SiO2 thickness, both phosphorus and boron diffusion
were performed using a 100 Ω.cm n-type FZ silicon wafer on planar or rantex surfaces. Each
wafer with specific diffusions and surface morphologies were cleaved into quarters. The
diffusion, growth and deposition of the ONO stack on all quarters followed the baseline, except
the duration of the initial thermal oxidation growth was varied. The wafers were loaded in O2
at 700 ˚C and ramped to different temperature set points. The thermal SiO2 growth on the
wafers occurred during the ramp up to 850, 900, 950 and 1000 ˚C. Immediately after reaching
the defined temperature set points, the O2 was switched to N2 and subjected to further annealing
at 1000 °C for 45 minutes in N2. By altering the duration at which the wafers were exposed to
oxidation, the thermal SiO2 thicknesses were measured to be between 4 to 16 nm. The process
flow is as illustrated in Figure 5.1a.
Results and discussion
The thermal SiO2 thicknesses were varied on the phosphorus diffused planar, phosphorus
diffused rantex, and boron diffused planar wafers. It is possible that variations in the oxidation
growth temperatures may affect the surface passivation; however, the different growth
temperatures of the thermal SiO2 underwent POA in N2 at 1000 °C for 45 minutes. The surface
passivations with different thermal SiO2 thicknesses required to achieve excellent surface
passivation are plotted in Figure 5.3.
Figure 5.3a illustrates that a thermal SiO2 thickness of approximately 7 nm or greater provides
excellent surface passivation on a light phosphorus diffused planar surface. However, a thicker
overall thermal SiO2 was required on the rantex surface as observed in Figure 5.3b, which
demonstrates excellent surface passivation with a thermal SiO2 thicknesses of approximately
10 nm or greater. One possible reason for the thicker thermal SiO2 requirements is due to the
concave and convex corners on the rantex, which have slower thermal SiO2 growth rates [239].
The surface passivation on the diffused planar wafers showed no substantial improvements
after positive corona charging; however, notable improvements were observed after corona
charging for rantex wafers with a reduced J0e. This trend was similarly observed on the
undiffused n-type silicon wafer passivated with ONO. This is most likely due to Dit with
thermal SiO2 on the 111 oriented rantex surfaces is generally higher compared to those on
100 oriented wafers [44, 206, 207].
72
5 10 15100
101
418 Ω/
532 Ω/
506 Ω/
(a)
τeff_10
15 before CC
J0e
before CC
τeff_1015 after positive CC
J0e
after positive CC
Thermal SiO2 thickness (nm)
τeff (
ms)
423 Ω/
101
100
J0e (
fA/c
m2)
5 10 15100
101
545 Ω/
692 Ω/
602 Ω/
532 Ω/
(b)
τeff_1015 before CC
J0e
before CC
τeff_1015 after positive CC
J0e
after positive CC
Thermal SiO2 thickness (nm)
τeff (
ms)
100
101
J0e (
fA/c
m2)
5 10 1510
-1
100
101
τeff_1015 before CC
J0e
before CC
τeff_1015 after negative CC
J0e
after negative CC
Thermal SiO2 thickness (nm)
τeff (
ms) 89 Ω/
105 Ω/ 135 Ω/
145 Ω/
100
101
102
J0e (
fA/c
m2)
(c)
Fig 5.3: Minority carrier lifetimes τeff_1015 and J0e measured for ONO on (a) phosphorus diffused planar, (b)
phosphorus diffused rantex and (c) boron diffused planar with different thermal SiO2 thicknesses annealed at 1000 ˚C in N2.
Figure 5.4c shows that the J0e for boron diffused wafers reduced as the thermal SiO2 thickness
increased. Reductions in the J0e with thicker thermal SiO2 is caused by the decreasing boron
dopant concentration at the surface (lower Auger recombination) and a reduced field effect
from SiNx. Due to the preferential segregation of boron dopants into the thermal SiO2, the
overall dopant concentration and the surface doping concentration are reduced with the
increased thermal SiO2 growth [240]. This effect consequently reduced the Auger
recombination while also increasing the sheet resistance [18, 238]. As the PECVD SiNx
generally exhibits positive charges within the dielectric film [234, 235], the field effect of SiNx
73
reduced with the increasing SiO2 thickness due to the charge centroid being driven away from
the silicon surface [192, 241]. As negative corona charges are applied to the surface, the J0e for
all boron diffused wafers decreased. This observation demonstrates the importance of the field-
effect passivation in the passivation of boron diffused surfaces from the ONO film stacks.
5.4.2 The effect of post-oxidation annealing of thermal oxide on diffused surfaces
The POA process on diffused wafers drives dopants deeper into the silicon bulk and slowly
diffuse dopants into the thermal SiO2. Higher POA temperatures with N2 may reduce the
overall Auger recombination of the diffusion profile while maintaining a similar electrical
conductivity, e.g. sheet resistance.
As the effects of the POA on undiffused wafers were discussed in Chapter 4, this section
examines the influence of POA on thermal SiO2 on the electrical properties of ONO stack for
diffused wafers.
Experimental details:
The 100 Ω.cm n-type FZ silicon wafer on planar or rantex surfaces were used to investigate
the effects of the POA in N2 for diffused surfaces. Diffusions performed on the wafers were
done similarly to baseline procedure in Section 5.2. Each wafer with specific diffusion and
surface morphologies were cleaved into quarters. The ONO stacks were similar to baseline
procedures in Section 5.2, except for the POA for thermal SiO2. the subsequent POA in N2
annealing was varied between 0, 15 and 30 minutes at 1000 ˚C and cooled down in ambient
N2. A control quarter without POA in N2 annealing was loaded at 700 ˚C, ramped to 1000 ˚C
and then ramped down in ambient O2. The process flow is illustrated in Figure 5.2b.
Results and discussion:
The results of thermal SiO2 subjected to POA in N2 for both diffusions are shown in Figure 5.4.
POA with N2 from Section 4.4.2 on n-type undiffused planar 100 orientation silicon substrate
has shown to reduce positive charges within the thermal SiO2. The phosphorus diffused planar
wafers in Figure 5.4a show a reduced J0e for a prolonged POA. A longer POA in N2 improves
the J0e by reducing the surface Dit and driving in the diffusion dopants deeper into the bulk,
74
which may reduce the Auger recombination of the diffused region [53]. Further positive corona
charging of the phosphorus diffused planar wafers shows either a marginal improvement or no
changes to the measured J0e. Phosphorus rantex wafers in Figure 5.5b show no obvious trend
with a prolonged N2 annealing before corona charging. However, the surface passivation
improves with subsequent positive corona charging under all annealing conditions. A
consistent J0e of ~4 fA/cm2 was measured across all annealing conditions. This suggests that
the N2 annealing may not improve the surface Dit of Si-SiO2 interface for diffused rantex wafers,
and that charges have a much larger influence on the surface passivation of 111 orientated
wafers as compared to 100 wafers. Both types of phosphorus diffused wafers (planar and
rantex), which were not subjected to any N2 annealing (i.e. when the ramp down is performed
in O2), have higher lifetimes compared to wafers with N2 annealing. This trend was similarly
observed for undiffused n-type wafers in Section 4.3.2. As also discussed in Section 4.3.2, the
reduction in lifetimes with N2 annealing is likely due to the re-introduction of vacancy-like
defects back into the silicon bulk, as demonstrated by Grant et al. [199, 200].
In Figure 5.5c, boron diffused planar wafers share similar trends with those that have
phosphorus diffusion, except when not subjected to any N2 annealing. The surface passivation
improves with N2 annealing due to a reduced surface Dit at the Si-SiO2 interface, dopants
concentration driven deeper into the bulk and reduced positive charges within the thermal SiO2
[53]. In contrast to phosphorus diffused wafers, a high J0e was observed for the boron diffused
surface with no N2 annealing (boron diffused J0e of 230 fA/cm2 as compared to phosphorus
diffused J0e of 4 fA/cm2). The surface passivation quality improved significantly after inducing
negative charges via corona charging, which approached the J0e values for the wafers that
underwent N2 annealing. This demonstrates that the thermal SiO2 that was ramped down in O2
has good chemical passivation and that the measured high J0e was due to positive charges within
the thermal SiO2.
75
0.0 0.1 0.2 0.3 0.4 0.51018
1019
0 10 20 30O2
100
101
556 Ω/
558 Ω/
556 Ω/
503 Ω/
(a)
τeff_1015 before CC
J0e
before CC
τeff_10
15 after positive CC
J0e
after positive CC
N2 Annealing (minutes)
τeff (
ms)
10-1
100
101
J0e (
fA/c
m2)
0 5 10 15 20 25 30O2
100
101
654 Ω/
682 Ω/710 Ω/
642 Ω/
(b)
τeff_1015 before CC
J0e
before CC
τeff_1015 after positive CC
J0e
after positive CC
N2 Annealing (minutes)
τeff (
ms)
100
101
J0e (
fA/c
m2)
0 10 20 30O2
10-1
100
101
τeff_1015 before CC
J0e
before CC
τeff_1015 after positive CC
J0e
after positive CC
N2 Annealing (minutes)
τeff (
ms)
100
101
102
177 Ω/175 Ω/176 Ω/
(d)
J0e (
fA/c
m2)
(c)
202 Ω/
180 Ω/
O2
0 N2
15 N2
30 N2
Simulation
Bo
ron D
opan
t C
on
centr
ation (
cm
-3)
Depth (µm)
180 Ω/
Fig 5.4: Minority carrier lifetimes τeff_1015 and J0e measured for the ONO stack samples on (a) phosphorus diffused
planar (b) phosphorus diffused rantex and (c) boron diffused planar surfaces with different thermal SiO2 POA duration. (d) Boron diffused profile with different POA duration as measured using ECV together with the simulated rectangle diffusion profile.
Electrochemical capacitance-voltage (ECV) measurements and EDNA2 simulations were
performed on the boron diffused wafers to better understand the contributions of Auger and
surface recombination (J0s) on the total emitter recombination (J0e). EDNA2 is a software
package that models the recombination of an emitter in one dimension [18]. The measured
boron diffusion profiles with ECV are plotted in Figure 5.5d. The results shown in Table 5.1
indicate that the J0s and Auger recombination within the emitter reduced with prolonged POA
in N2. To demonstrate the reduction in Auger recombination, simulated profiles of boron
diffusion with identical sheet resistivities show that Auger recombination reduces as the boron
76
dopants are redistributed from the high surface dopant concentration with a shallow junction
to a smaller surface dopant concentration with a deeper junction.
Table 5.1: Simulations for different boron diffusion profiles with EDNA2 after negative corona charging on the ONO stack. The simulation assumes no SRH recombination within the diffusion profile.
5.5 Deposition conditions for PECVD SiNx of the ONO stack on diffused
surfaces
The deposition conditions for the SiH4:NH3 gas flow ratio were examined on undiffused wafers
in Section 4.4.2. The results obtained for undiffused wafers indicate that increasing the ratio
between the SiH4:NH3 increases the SiNx refractive index and reduces the Qeff of the ONO
stack of N2 POA thermal SiO2.
In this section, the effects of the ONO stack with different SiH4:NH3 gas ratios on diffused
wafers were investigated, with the investigation process presented in the flowchart of Figure
5.5.
Experimental details
Several FZ n-type 100 Ω.cm chemical polished 100 planar silicon wafers were used to
investigate the influence of the SiNx refractive index. The diffusion and deposition of the ONO
stack on all wafers was identical to the baseline except for the thermal oxidation and PECVD
SiNx conditions. The thermal oxidation for phosphorus was ramped down in O2 whereas the
thermal oxidation for boron was ramped down in N2. The different gasses performed during
the thermal oxidation ramp down were selected to control the quantity of positive charges
within the thermal SiO2, as discussed in Chapter 4. The phosphorus diffused wafers were
POA Duration Sheet Resistivity Nsurface EDNA 2
(min) (Ω/) (1019 cm-3) Zf (µm) J0e
(fA/cm2) JAuger
(fA/cm2) J0s (fA/cm2)
O2 0 202 0.3 - 21.4 6.5 14.9
N2 0 176 2.0 - 16 8.6 7.4
N2 15 175 2.2 - 12 8.5 3.5
N2 30 177 2.0 - 11 7.6 3.4
Simulation - 180 1 0.540 5.3 5.3 0
Simulation - 180 3 0.203 15 15 0
77
loaded at 700 ˚C, ramped up to 1000 ˚C and ramped down immediately to 700 ˚C in ambient
O2. The boron diffused wafers were loaded in at 700 ˚C and ramped up to 1000 ˚C in O2, and
ramped down in N2 to 700 C. The sheet resistivity of the phosphorus and boron diffused wafers
was measured to be 570 ± 30 Ω/ and 180 ± 10 Ω/ respectively.
In the case of the PECVD SiNx, the SiH4:NH3 gas ratios were varied between 0.4 to 7, as the
SiH4:NH3 gas flows were varied between 4 to 24 sccm. The deposition time was varied to
maintain the SiNx thickness at different gas ratios. The SiNx and SiOx thicknesses of 55 ± 3 nm
and 90 ± 5 nm, respectively, were achieved.
Fig 5.5: Flow chart detailing the process variations for each layer (relative to the baseline) to establish the best passivation conditions of the gas ratio for PECVD SiNx
Gas ratio of SiNx
Phosphorus
Diffusion 780 ˚C
Thermal Oxidation
1000 °C
Ramp down in O2
PECVD Silicon Nitride 400 °C
(Different gas ratio)
PECVD Silicon Oxide 250 °C
FGA 400 °C Boron
Diffused Wafers
Thermal
Oxidation
1000 °C
Ramp down in N2
Planar 100 and
rantex, quartered
Boron Diffusion
940 ˚C
Planar 100
quartered
FGA 400 °C
Phosphorus
Diffused Wafers
Positive Corona
Charging 5 kV
Negative Corona
Charging 6 kV
FGA 400 ˚C FGA 400 ˚C
78
Results and discussion
The results for J0e with various SiNx refractive indexes n632 before and after the corona charging
for both diffusions are plotted in Figures 5.6a-b. Prior to corona charging, the lowest SiNx
refractive index n632 of 1.83 was found to have the highest J0e with both diffusions. The surface
passivation for phosphorus diffused wafers improved and stabilised across SiNx refractive
indexes n632 of 1.90 to 2.58. The improvements to J0e with higher could be related to
hydrogenation of the surface and bulk as observed on the undiffused wafer in Section 4.4.2.
Fig 5.6: Minority carrier lifetimes and surface recombination pre-factors as measured for ONO stack samples on (a) phosphorus diffused planar and (b) boron diffused planar surfaces with different SiNx refractive indexes n632.
Similarly, the surface passivation for boron diffused wafers improved with an increased SiNx
refractive index n632 and stabilised across the range of 1.94 to 2.58. In Section 4.4.2, C-V
measurements performed on the various SiNx refractive indexes shows that the effective
positive charges on the ONO stack decrease as the refractive index increased from 1.90 to 2.21.
The reduced positive charges across the refractive indexes of 1.90 to 2.21 are reflected in the
decreasing J0e for the boron diffused wafers plotted in Figure 5.6b. Negative corona charging
on boron diffused wafers significantly improved the surface passivation. Boron diffused wafer
with a J0e of 580 fA/cm2 had reduced surface recombination of merely 8 fA/cm2 after the
negative corona charging. This again demonstrates that the ONO stack has excellent chemical
passivation for boron diffused samples across all SiNx refractive indexes.
1.8 2.0 2.2 2.4 2.6
101
102
Grey: Before CC
Black: After pos. CC
τeff_1015
J0e
Refractive Index (n)
τ eff (
ms)
101
100
(a)
J0e (
fA/c
m2)
1.8 2.0 2.2 2.4 2.610
-1
100
101
Grey: Before CC
Green: After neg. CC
τeff_1015
J0e
Refractive Index (n)
τ eff (
ms)
(b)
100
101
102
103
J0e (
fA/c
m2)
79
5.6 Impact of corona charging and annealing on diffused surfaces with
ONO stack
Significant improvements were obtained on the ONO passivation as shown with diffused and
undiffused n-type wafers, where immeasurably low J0s values were achieved.
This section presents and discusses the injection dependence of effective lifetime of
phosphorus diffused planar, rantex and boron diffused planar surfaces before and after corona
charging and followed by FGA at 400 ˚C.
Experimental details
To investigate the influence of corona charging, both phosphorus and boron diffusion were
performed using a 100 Ω.cm n-type FZ silicon wafer on planar or rantex surfaces. In the
fabrication of diffused wafers, the ONO stack and corona charging are identical to the baseline
process. However, the wafers were subjected to additional annealing in FG at 400 ˚C for 30
minutes after corona charging.
Results and discussion
The effect of the corona charging on diffused wafers was documented using lifetime
measurements of the deposited ONO stack, corona charging and further annealing in FG at 400
˚C in Figure 5.7.
Degradation of the surface passivation was observed on the phosphorus diffused planar after
attempting to embed corona charging with FGA, as shown in Figure 5.7a. The positive corona
charging on the phosphorus diffused planar wafer had a slight increase in the τeff at injection
levels greater than 1015 cm-3. However, lifetimes at lower injection levels decreased, which
indicates slight degradations that may be due to dehydrogenation of the bulk or the increased
defect interface at the Si-SiO2 interface [95, 177, 178]. The additional FGA to embed the
charges did not improve or recover the lifetime to initial surface passivation conditions.
80
1013 1014 1015 1016
0
20
40
60
80
100
1013 1014 1015 1016
0
10
20
30
40
50
1013 1014 1015 1016
0
5
10
15
20
J0e
6.9 fA/cm2
J0e
1.9 fA/cm2
J0e
~4.0 fA/cm2
τeff (
ms)
Excess Carrier Density (cm-3)
Initial
CC 120s
CC & FGA
fit τeff
(a) (b)
J0e
5.3 fA/cm2
J0e
3.4 fA/cm2
J0e
9.6 fA/cm2
τeff (
ms)
Excess Carrier Density (cm-3)
Initial
CC 120s
CC & FGA
fit τeff
J0e
~59 fA/cm2
J0e
~25 fA/cm2
J0e
~9 fA/cm2
(c)
τeff (
ms)
Excess Carrier Density (cm-3)
Initial
CC 100s
CC & FGA
fit τeff
Fig 5.7: Minority carrier lifetime measurements of (a) phosphorus diffused planar, (b) phosphorus diffused rantex and (c) boron diffused planar surfaces, prior to corona charging, after corona charging and after the additional annealing in FG at 400 ˚C.
Improvements in the passivation were observed on the phosphorus diffused rantex and boron
diffused planar wafers after corona charging and additional FGA. The positive corona charging
on the phosphorus diffused rantex wafers, as shown in Figure 5.7b, resulted in improved
lifetimes at all injection levels, where a J0e of ~3.4 fA/cm2 was achieved. The negative corona
charging for boron diffused surfaces, as shown in Fig 5.7c, improved the surface passivation
and achieved a J0e of ~9 fA/cm2. The subsequent FGA to embed charges within the ONO stack
for both wafers showed slight degradation, but maintained an overall higher lifetime than when
performed prior to the corona charging. The cause of such degradation maybe due to decrease
81
in charges or increase in surface recombination. Some of the charges may not have been
embedded into the ONO stack or were lost during the subsequent annealing step [65], moreover
it is possible that the surface passivation may have deteriorated after corona charging due to
ion bombardment [178].
5.7 Chapter summary
Diffusions are important for the operation of a conventional solar cell. This chapter details the
study of ONO passivation on light boron and phosphorus diffused wafers by examining the
effects of the thermal SiO2 thicknesses, POA with N2, SiNx refractive index, corona charging
and subsequent annealing.
Depending on the orientation and surface morphology, the deposition of corona charges onto
ONO stack to accumulate majority carriers of boron and phosphorus diffused surfaces may
improve the surface passivation. The deposition of corona charges and further annealing was
observed to improve the surface passivation for boron diffused planar and phosphorus rantex
surfaces. However, ONO passivation with light phosphorus diffusion on 100 oriented
surface need not require additional corona charging. Only mild improvement was observed
after charging, and excessive corona charging may degrade the surface and bulk lifetime due
to ion bombardment at the Si-SiO2 interface [178].
Thermal SiO2 with thicknesses from 7 to 10 nm in the ONO stack on lightly phosphorus
diffused wafers were found to provide excellent surface passivation on both planar and rantex
surfaces. A thicker thermal SiO2 was required for rantex surfaces due to the concave and
convex corners, which have slower oxide growth rates. Boron diffused planar surfaces
similarly improved with increasing thermal SiO2 thicknesses due to the resulting light doping
profiles and reduced positive charge centroid from the SiNx.
A much more complex situation was observed on the diffused wafers after the N2 POA. The
J0e on the phosphorus diffused wafers with a planar surface improved after a prolonged POA;
however, no improvements were observed on the rantex wafers. Introducing POA in N2
reduced the lifetime on both the phosphorus diffused surfaces compared with the thermal SiO2
ramped down in O2. The reduced lifetimes with POA in N2 were similarly observed for the
undiffused wafers, suggesting the N2 annealing may have contributed to bulk defects or
contaminations. The J0e for boron diffused planar wafers improved with prolonged POA in N2
82
due to the reduced Auger recombination of the doping profile and the improved surface
passivation of the ONO stack.
Increasing the silane to ammonia gas ratio reduced the J0e for the phosphorus diffused planar
wafers. The decreased J0e with an increased gas ratio may be due to hydrogenation of the
surface and bulk with an increasing SiNx refractive index. The boron diffused surface achieved
improved passivation with higher SiNx refractive indexes due to the hydrogenation and lower
positive charges.
Excellent surface passivation was achieved for phosphorus and boron diffused wafers with
ONO surface passivation after corona charging. Positive corona charged ONO stack passivated
on phosphorus diffused wafer with sheet resistivity of 520 Ω/ planar and 610 Ω/ rantex
surface achieved J0e of 0.5 fA/cm2 and 1.9 fA/cm2, respectively. Negative corona charged ONO
stack passivated on boron diffused wafer with sheet resistivity of 154 Ω/ planar surface
achieved J0e of 4.8 fA/cm2.
83
Chapter 6
Simulation of ONO IBC solar cells
6.1 Introduction
This chapter presents the loss analysis for an interdigitated back contact (IBC) solar cell with
ONO stack surface passivation. Simulation tools, such as EDNA2, SunSolve, OPAL2 and
Quokka3, were used to simulate the solar cell performance. The three general loss categories
are optical, recombination and resistance, which are analysed and discussed in detail.
6.2 Optical losses
The reflectance of a polished silicon surface at normal incidence can be obtained using the
Fresnel equation as shown in Eq 6.1:
z.3 = (1 − )= + ()=(1 + )= + ()= (6.1)
n: refractive index k: extinction coefficient
The reflectance of a polished silicon sample is ~35% at a 632 nm wavelength with established
n and k values of silicon [242]. To reduce the uncaptured energy from the high reflectance, the
silicon surface can be chemically textured to create isotextures or random pyramids. Chemical
etching to create a random textured pyramidal surface can reduce the overall reflection to ~12%
at wavelengths from 400–1100 nm [243]. Other surface morphologies, such as black silicon
(BSi), have gained significant interest in recent years due to their excellent absorption over a
wide range of wavelengths with reflections of ~1% [244]. However, BSi has yet to overcome
the high surface recombination caused by the increased surface area of random nanoscale
structures [244].
Surface reflection can be further reduced using an ARC, which utilises the destructive
interference of reflected light. Single or multiple layers of dielectric stacks are commonly
84
deposited on high-efficiency solar cells to reduce the reflectance, such as SiO2, SiNx, TiO2,
MgF2-ZnS and SiNx-SiOx [14, 117, 245, 246].
The following section discusses simulations that were performed using OPAL2, which is an
optical simulator developed by Baker-Finch et al. that is capable of simulating different surface
morphology for a solar cell [19].
6.2.1 OPAL2 simulation inputs
The simulations in OPAL2 requires user inputs for the surface condition, planar fraction,
dielectric film thicknesses, refractive index and extinction coefficient, substrate thickness and
light trapping model to define the generation current density (Jgen) within the wafer. This
section reviews and discusses each of these conditions.
Textured surface – The limiting number of light ray bounces within the pyramids is
determined from the pyramidal angle. The number of light ray bounces for symmetric pyramids
increases to between 1 and 3 as the pyramidal angle increases from 0 to 60˚ (Appendix A).
Ideally, larger pyramidal angles are desired to increase the number of light ray bounces and
reduce the overall surface reflection.
Monocrystalline silicon texturing is typically performed using potassium hydroxide (KOH),
TMAH or sodium hydroxide (NaOH) together with isopropanol (IPA) or other surfactants. Due
to the different etching rates of the 111 and 100 oriented planes, the anisotropic etching
and masking of IPA (discussed in Chapter 7) result in the formation of randomly scattered
pyramids that are typically 3-20 µm across the base. The theoretical pyramidal angle between
the 111 and 100 silicon planes is 54.735˚. However, reported angles of individual pyramid
facets and the substrate surface plane (α) range from 49 to 53˚ [247]. The random pyramid
facets etched with a mixture of TMAH and IPA solution used on fabricated IBC solar cell
devices in this work (details in Chapter 7) were measured to have a pyramid angle of 51˚ using
electron microscopy.
Planar fraction – Incomplete texturing may occur during the texturing process, which results
in a fraction of highly reflective planar surface coverage. The measured reflectance from a
spectrophotometer can be fitted with the simulated reflectance for a planar fraction, where the
85
simulated reflectance is calculated using the percent of planar region reflectance, including the
remaining percent for the defined surface morphology reflectance.
Refractive index and extinction coefficient – The n and k values were determined for the
applied ARC materials. The ONO stack consists of three different refractive indexes and
extinction coefficients.
The initial bottom layer of the ONO stack is thermal SiO2 with n and k values obtain from Palik
[248]. The second and third layer of the PECVD SiNx and SiOx deposited using an Oxford
Plasmalab 100 have refractive indexes and extinction coefficients that were measured using a
JA Woollam M2000D ellipsometer. The refractive indexes and extinction coefficients for
various SiNx compositions with different SiH4:NH3 gas ratio are plotted in Figure 6.1. The
measured refractive indexes and extinction coefficients increase with the SiH4:NH3 gas ratio
due to the increased absorption of the silicon-rich SiNx. The measured n and k of the third layer
(SiOx) are similar to previously published results [249].
400 600 800 10001.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
400 600 800 100010
-5
10-4
10-3
10-2
10-1
100
101
Re
fra
ctive
In
de
x (
n)
Wavelength (nm)
SiH4:NH
3 ratio
6:1
5:2
9:5
4:3
1:1
3:4
2:5
(b)
Extin
ctio
n c
oe
ffic
ien
t (k
)
Wavelength (nm)
SiH4:NH
3 ratio
6:1
5:2
9:5
4:3
(a)
1:1
3:4
2:5
Fig 6.1: Measured (a) refractive indexes and (b) extinction coefficients for PECVD SiNx with different SiH4:NH3 gas ratios deposited with an Oxford Plasmalab 100.
Substrate thickness – The substrate thickness affects the spectral absorption. For a
conventional silicon solar cell, the increased cell thickness improves the light absorption,
especially at longer wavelengths (>900 nm).
Light trapping model – Light trapping improves the light absorption because the optical path
length is increased to several times the actual device thickness. Light trapping is commonly
86
achieved using a textured surface by coupling light obliquely into the silicon, which changes
the angle at which light travels. Figure 6.3 shows light travelling into two different cell structure.
In Figure 6.2a, the light ray only passes through once in the planar substrate with no light
trapping. However, in Figure 6.2b, the light ray bounces multiple times within the substrate,
increasing the optical light path with a front pyramidal texture and back reflector. The increased
optical light path can be defined using the optical pathlength enhancement factor (Z). The
optical pathlength enhancement factor for a solar cell can be determined by measuring its
external quantum efficiency (EQE) [249].
Fig 6.2: Optical pathlength with (a) no light trapping applied on planar silicon wafer and (b) improved light trapping with a pyramidal textured surface and a back reflector.
A Lambertian scatterer offers a high degree of randomisation to the incoming light rays and
significantly improves the light trapping capability of a solar cell. The ‘ideal’ cases for
Lambertian light models available in OPAL2 are shown in Table 6.1. The differences in the
models are due to the underlying assumptions. Yablonovitch et al., for example, accounted for
weak absorption within the silicon substrate [250], Tiedje et al. assumed no absorption within
the escape cones [251] and Green’s analytical solution considered that a fraction of 1/n2 of the
incident light is scattered into the loss cone [252]. These ‘ideal’ limits only present the
absorptance for Lambertian light paths and do not represent an upper limit.
These Lambertian light models provide a benchmark to evaluate the ‘ideal’ light trapping for
a solar cell. However, solar cells commonly use a model with a constant optical pathlength
enhancement of 2 ≤ Z ≤ 50. The absorption within the substrate for a lumped constant Z can
be re-written as Eq 6.2.
k = 1 − WA (6.2)
w: thickness of the substrate α: absorption coefficient
(a) (b)
Light
87
Table 6.1: The absorption and optical pathlength enhancements for different Lambertian models [250-252]
Absorption in Substrate Optical Pathlength Enhancement
k = 1 − WA = 4=
k = 1 − WA1 − (1 − =)WA = ln(1 + 4=d)d
k = 4=d1 + 4=d = 4 + lnf= + (1 − =)WAgd
w: thickness of the substrate α: absorption coefficient n: refractive index
6.2.2 Simulation of ONO with OPAL2
The ARC simulation for the ONO stack was performed to determine the optimal thicknesses
for each layer of thermal SiO2, PECVD SiNx and SiOx. The parameters used for the simulation
in OPAL2 are listed in Table 6.2.
Table 6.2: Simulation parameters for the ONO stack using OPAL2.
Parameter Details
Surface morphology Random – Upright pyramids
Characterization angle 51˚
Planar fraction 0%
Film 1 PECVD SiOx [249]
Film 2 PECVD SiNx 1.94 (Fig 6.2)
Film 3 Thermal SiO2 [248]
Substrate Crystalline Si [242]
Substrate thickness 230 µm
Light trapping model = 4 + lnf= + (1 − =)WAgd
Simulated wavelength region 250–1200 nm
Two simulations were performed with a variety of thermal SiO2, PECVD SiNx and SiOx
thicknesses. The first simulation presented in Figure 6.3a varied the thermal SiO2 and SiNx
thicknesses while maintaining SiOx thickness at 90 nm. The second simulation had an optimum
88
SiOx thicknesses ranging between 69–110 nm, for all simulated thermal SiO2 and SiNx
thicknesses.
Two trends were observed in Figures 6.3a-b. The first trend shows nearly identical counter
plots with various simulated thermal SiO2 and SiNx thicknesses. The largest difference in the
JGen for both plots of 0.23 mA/cm2 occurred at thermal SiO2 and SiNx thicknesses of 0 nm.
However, at thermal SiO2 and SiNx thicknesses above 6 nm, the differences in JGen reduced to
<0.08 mA/cm2. This demonstrates that a fixed SiOx thickness of 90 nm is nearly optimum for
the simulated range of thermal SiO2 and SiNx thicknesses above 6 nm.
The second trend observed in both graphs shows that for an optimum SiNx thickness, the JGen
reduces with the increasing thickness of the thermal SiO2. The initial thermal SiO2 layer on the
ONO stack behaves parasitically from an optical perspective. This is as expected since the
refractive index of thermal SiO2 is lower than that of simulated SiNx and is therefore
detrimental to the transmission of light into the silicon. Since the best optical performance is
achieved in the absence of the interfacial thermal SiO2, the optimal ARC is simulated with
thermal SiO2, PECVD SiNx and SiOx thickness of 0 nm, 65 nm and 90 nm (SiNx-SiOx),
respectively. However, as presented in Section 5.4.1, the surface passivation on the light
phosphorus diffused rantex wafer improved with the increasing oxide thickness, possibly
saturating above 12 nm. This creates an optimisation problem that balances the trade-off
between the optical transparency of the front ARC versus the passivation quality.
43.65 43.20
43.60
43.50
43.40
43.20
43.0042.80
43.65
43.60
43.50
43.40
43.20
43.00
0 5 10 15 20 25 300
10
20
30
40
50
60
Thic
kne
ss o
f S
iNx
(nm
)
Thickness of thermal SiO2 (nm)
42.00
42.40
42.80
43.20
43.60
JGen
(mA/cm2)(a)
0 5 10 15 20 25 300
10
20
30
40
50
60
(b)
Thic
kne
ss o
f S
iNx
(nm
)
Thickness of thermal SiO2 (nm)
42.00
42.40
42.80
43.20
43.60
JGen
(mA/cm2)
Fig 6.3: Simulation of ONO stack with varying thermal SiO2 and SiNx thicknesses using OPAL 2. (a) The SiOx thickness is 90 nm. (b) The SiOx thickness is optimum for each thermal SiO2 and SiNx thickness pair.
89
While this balance introduces some complications, it coincides with the thickness for which
the passivation quality is nearly optimal for both the rear boron and phosphorus diffusions - a
thermal SiO2 thickness of 11–16 nm, as presented in Section 5.4.1 while an excellent front
optical performance with a JGen reduction of merely 0.15 mA/cm2 is expected.
0.0
0.5
1.0
1.5
2.0
Sp
ectr
al in
t. (
W/m
2/n
m)
400 600 800 10000
5
10
15
20
25
30
35
40 Simulated SiN
x
Simulated NO
Simulated ONO
AM1.5G
Rantex ONO
Wavelength (nm)
Re
flecta
nce (
%)
Fig 6.4: Reflection measurements of the ONO rantex wafer with layer thickness for the thermal SiO2 of 18 nm, PECVD SiNx of 48 nm and SiOx of 90 nm compared to the simulated optimised nitride-oxide and single layer SiNx ARC.
In Figure 6.4, the measured reflectance of an ONO rantex wafer is compared with a simulated
double layer SiNx-SiOx and single layer SiNx ARC. The input parameters used to fit the
measured reflectance of the fabricated ONO rantex in OPAL2 had a thermal SiO2 thickness of
18 nm and PECVD SiNx n632 of 1.92 and SiOx thicknesses of 48 and 90 nm, respectively. The
simulated double ARC from the SiNx-SiOx performed better at shorter wavelengths compared
to the ONO stack. Within the range of optimal thermal oxide thicknesses for passivation, the
ONO stack performed almost as well as the DARC SiNx-SiOx (NO), and both are capable of
achieving an overall lower reflection compared to a single layer SiNx ARC n632 of 1.92. The
measured JGen for each condition of NO, ONO and SiNx in Figure 6.5 with the parameters listed
in Table 6.2 were 43.71, 43.55 and 43.30 mA/cm2, respectively.
90
6.2.3 Free carrier absorption
Free carrier absorption (FCA) occurs commonly within the highly doped regions of silicon
solar cells. The photon energy is absorbed by the free carriers, which are excited to higher
energy levels within a similar band state. The FCA does not generate additional electron-hole
pairs to assist in the current generation.
Transmission and reflectance measurements were performed on a heavily phosphorus diffused
polished silicon wafer with a resistivity of 14 Ω/. In Figure 6.5a, the FCA can be observed
for wavelengths greater than 1000 nm.
1000 1200 14000
10
20
30
40
50
60
70
80
800 1000 1200 140010-1
100
101
102
103
(b)
Reflectio
n /
1-t
ransm
issio
n (
%)
Wavelength (nm)
R Diffused
(1-T) Diffused
R Undiffused
(1-T) Undiffused
(a)
1020
cm-3
1019 cm-3
1018
cm-3
Absorp
tion C
off
icie
nt
α (c
m-1)
Wavelength (nm)
Intrinsic Si
Fig 6.5: (a) Measured transmission and reflectance of a heavily phosphorus diffused wafer with a resistivity of ~14 ohms/ and (b) the modelled absorption coefficient.
The parameterised absorption coefficient proposed by Baker-Finch et al. for phosphorus and
boron doping densities can be calculated using Eq 6.3 and 6.4 [253].
oe, = 1.68 × 10M_=. (6.3)
oe,p = 1.82 × 10>e=.9 (6.4)
αFCA,P: Absorption coefficient for phosphorus αFCA,B: Absorption coefficient for boron N: Dopant concentration
The FCA plotted in Figure 6.5b using Eq 6.3 shows the absorption coefficients for various
phosphorus concentrations. Increasing the phosphorus concentration increased the absorption
91
at longer wavelengths and, therefore, fine tuning the diffusion profile to minimise FCA is
required to reduce the losses from photogeneration at these lower photon energies.
Substituting Eq 6.3 or 6.4 into Eq 6.5, the FCA for either phosphorus or boron diffusion profiles
can be calculated as a function of the wavelength. This provides the fraction of long wavelength
photons (≥1000 nm) absorbed by free carriers.
ko = 1 − exp(−o(3) J)320l39
(6.5)
imax: The node at which Ndop(z) falls below 1014 cm-3 z: diffusion profile depth θ: angle of transmission through the silicon
The simulations for the FCA in a cell can be accounted for by calculating the FCA absorption
for a specific diffusion profile and defining a wavelength-dependent reflection layer using the
SunSolve software package.
6.2.4 Simulation of FCA using SunSolve
Simulations for the FCA were performed using the IBC solar cell structure shown in Figure
6.6. The diffusion profiles were simulated as Gaussian functions with defined surface doping
peaks to achieve the intended sheet resistivity. Heavy phosphorus diffusion for contact dots
were simulated with a surface doping peak of 1.5 × 1020 cm-3 with a sheet resistivity of 15 Ω/.
Two other phosphorus diffusion profiles for the front and rear surface fields were simulated
with surface doping peaks of 1 × 1019 cm-3 to obtain resistivities of 450 Ω/ and 800 Ω/,
respectively. The diffusion profile of the boron diffusion with a surface doping peak of 2 × 1019
cm-3 was modelled using a Gaussian function to obtain a sheet resistivity of 160 Ω/.
The FCA absorption for the diffusions were calculated using Eq 6.5 with a wavelength from
1000–1300 nm. The calculated absorption was implemented into a wavelength-dependent
reflection, absorption and transmission layer, and simulated with the IBC solar cell structure
(Figure 6.6) using the SunSolve ray tracing simulator. SunSolve implements a Monte Carlo ray
tracing method to solve Jsc for various dielectric layers and solar cell surfaces. The simulations
with and without the FCA were performed on an IBC solar cell structure (front rantex, rear
planar) with ARC using the ONO stack on both front and rear surfaces.
92
The calculated FCA in Table 6.3 for an IBC solar cell shows a total loss of ~0.06 mA/cm2. The
FCA for the defined IBC solar cell design (chapter 7) with ONO stack is negligible and
contributes to only ~0.14% of the total Jsc without FCA.
Table 6.3: Simulation for the FCA using the SunSolve ray tracing software.
6.3 Recombination losses of ONO IBC solar cell
The recombination losses component in a solar cell include those from the surface (surface
SRH), the emitter (surface SRH, emitter SRH and Auger), the bulk (bulk SRH, Auger and
radiative) and metal contact surfaces (surface SRH). One method to quantify each component
of the recombination losses is with the saturation current (J0), where J0 can be determined either
through experiments or control wafers during cell processing. The total cell recombination can
be calculated based on the total area weighted J0 for each component or region.
In this section, simulations for an ONO IBC solar cell were conducted using three-dimensional
modelling in Quokka3. The cross-section of a simulated IBC solar cell is presented in Figure
6.6, and the baseline simulation parameters are given in Table 6.3.
Fig 6.6: Schematic diagram for an IBC solar cell simulated using Quokka3 (not to scale).
Simulation of ONO IBC solar cell structure Simulated Jsc
(mA/cm2)
Weighted area
(%)
Reduction in Jsc
(mA/cm2)
No FCA 42.65 - -
Full front area phosphorus diffusion (450 Ω/) 42.61 100 0.04
Full rear area phosphorus diffusion (15 Ω/) 42.19 1.3 0.006
Full rear area boron diffusion (160 Ω/) 42.61 8.9 0.004
Full rear area phosphorus diffusion (750 Ω/) 42.64 89.8 0.006
Surface passivation and ARC
Boron diffusion
Heavy phosphorus diffusion
Light phosphorus diffusion
Metal Pitch
93
Table 6.3: Simulation parameters for the Quokka3 simulation were based on experimental values from findings mostly presented in this thesis [14, 254]. Pitch size of cell is 500 µm. Optical simulations that were incorporated into Quokka3 were obtained using OPAL2. The path enhancement parameters used were from a previously characterised IBC solar cell [249].
Area Side Properties Reference Values
Rantex light phosphorus 100% FSF Sheet resistance 450 Ω/
J0e 10 fA/cm2
Planar light phosphorus BSF Sheet resistance 750 Ω/
J0e 2.5 fA/cm2
Localised phosphorus dot
contact
1.3% Rear Sheet resistance 15 Ω/
J0e 230 fA/cm2
Finger size 150 µm
Localised boron dot emitter 8.9% Rear Sheet resistance 160 Ω/
J0e 20 fA/cm2
Dot pitch 140 µm
Finger size 350 µm
Metallised contact 0.34% Rear Contact resistivity Chapter 7 2 × 10-5
Ω.cm2
Metallised phosphorus dot
contact
Rear J0e Chapter 7 500 fA/cm2
Metallised boron contact dot Rear J0e Chapter 7 1300
fA/cm2
Bulk 100 ms
Resistivity n-type 100 Ω.cm
Cell thickness 230 µm
Series resistance External circuit series
resistance
Chapter 7 0.21 Ω.cm2
Shunt resistance External circuit shunt
resistance
Chapter 7 10 kΩ.cm2
Ideality factor 1.0
Optical modelling Front ONO [19] OPAL2
Z parameterization [255] Z0, Zinf, Zp
94
The subsequent subsections describe the performance of cell devices simulated using Quokka3
over a range of cell parameters. The performed simulations include:
- Front and rear surface recombination with light phosphorus diffusion.
- Boron emitter recombination and the dot area fraction.
- Heavy phosphorus recombination and the dot area fraction.
- Different pitch lengths while maintaining similar boron emitters, heavy phosphorus and
metal contact fraction.
- Bulk lifetime, bulk resistivity and edge recombination.
- Series and shunt resistances.
6.3.1 Simulation of front and rear surface recombinations with phosphorus
surface field
The implementation of light phosphorus diffusion as a surface field has shown to benefit cell
processing and the solar cell structure. This includes a reduced sensitivity for the front surface
recombination with the surface field, bulk gettering, contaminant inhibition during cell
processing and assistance in the lateral current transport [232, 256]. In Chapter 7, light
phosphorus diffusion was implemented on both the front and rear surfaces of the IBC solar cell
to inhibit contamination and reduce the sensitivity of the front surface recombination.
The phosphorus diffusion at the front surface creates an electric field that repeals minority
carriers (holes) from recombining at the surface [20]. However, the phosphorus diffusion
profile has to be sufficiently light and shallow to limit both Auger recombination and FCA.
Therefore, this section first investigates and simulates the different diffusion profiles and
surface recombination in terms of the performance for IBC solar cells. The cell performance
was investigated using various front and rear surface recombination, and, finally, the cell
performance was investigated by varying the rear surface recombination and sheet resistivity.
Simulation details:
The simulation details for the front and rear surface recombinations are divided into three
subsections.
95
Different diffusion profiles – Four phosphorus diffusion profiles were simulated in EDNA2
using a Gaussian function with the first three surface dopant concentration of 4 × 1019 cm-3,
1019 cm-3 and 1018 cm-3 with a depth factor (Zf) of 0.117 µm, and the final diffusion profile with
a dopant concentration of 1019 cm-3 and a Zf of 0.354 µm. The J0e of the defined diffusion
profiles were simulated with a range of surface recombinations (Seff). The performance of IBC
solar cells was simulated using baseline parameters in Quokka3, however, the front J0e and
sheet resistivity were varied based on the EDNA2 simulation results.
Front and rear surface recombination – Simulations for an IBC solar cell were performed
using the baseline parameters, except the front and rear surface recombinations were varied
with J0e from 1 to 20 fA/cm2.
Rear surface recombination and sheet resistivity – Simulations for an IBC solar cell were
performed using the baseline parameters, except the rear surface recombination and sheet
resistivity were varied between 3 to 20 fA/cm2 and 200 to 2400 Ω/, respectively. A surface
recombination lower limit was defined with a J0e of 3 fA/cm2 (Seff ~0 cm/s) and sheet resistivity
of 200 Ω/. The lower limit was validated using a Gaussian function for the boron diffusion
profile using EDNA2 with a surface dopant concentration of 5 × 1018 cm-3.
Results and discussion:
The results for each condition are discussed in the following subsections.
Different diffusion profiles - The simulated J0e with different diffusion profiles and Seff are
plotted in Figure 6.7a. It was found that the J0e is dependent on the surface recombination,
surface dopant concentration and junction depth. The simulation shows that the surface
recombination becomes less substantive with an increased surface dopant concentration.
However, a sheet resistivity of 155 Ω/ with a shallower profile (smaller Zf) has higher J0e
recombination due to an increased Auger recombination within the diffusion profile.
The range of J0e for the phosphorus diffusion profiles from EDNA2 was utilised in Quokka3
simulations. The simulation results shown in Figure 6.7b show that the efficiency of the IBC
solar cell is increasingly sensitive to the quality of the front surface passivation as the surface
dopant concentration and sheet resistance decrease. However, the cell efficiency becomes
limited with an increasing surface dopant concentration and sheet resistance. Therefore, having
96
a fine-tuned light diffusion can improve the robustness of the front surface passivation without
being detrimental to the overall cell performance.
100
101
102
103
0
10
20
30
40
50
60
100
101
102
103
23.0
23.5
24.0
24.5
25.0
25.5
26.0
155 Ω/
(a)
155 Ω/
1870 Ω/
468 Ω/
J0e (
fA/c
m2)
Seff
(cm/s)
Zf of 0.177 µm
Npeak
4×1019
Npeak
1×1019
Npeak
1×1018
Zf of 0.354 µm
Npeak
1×1019
Eff
icie
ncy (
%)
Seff
(cm/s)
1870 Ω/ 468 Ω/ 155 Ω/ 155 Ω/
No FSF
(b)
Fig 6.7: (a) Simulations for various diffusion profiles using EDNA2 as a function of Seff. The diffusion profile was simulated using a Gaussian function with a similar depth factor. (b) Simulations for cell efficiency using Quokka3 with a select range of Seff
Front and rear surface recombination - The simulation results of an IBC solar efficiency,
Voc, Jsc and fill factor for the front and rear surface recombinations are presented in Figure 6.8.
The cell efficiency results in Figure 6.8 shows that increasing the overall surface recombination
reduces the cell efficiency. It is observed that the effect of the cell efficiency is more prominent
for the front surface J0e as compared to the rear.
The main impact on the cell efficiency was due to the surface recombination, which is reflected
in the Voc. The efficiency and Voc both decrease as the surface J0e increases. The second
observed impact in cell efficiency is due to the decreased Jsc with increasing surface
recombination. Most carriers are generated closer to the front surface and high front surface
recombination can substantially reduce the amount of minority carriers collected at the rear
junction. These effects are more pronounced for the front J0e compared to the rear with
decreases in both Jsc and FF, as plotted in Figures 6.8c-d.
97
82.20
82.40
82.60
82.80
83.00
42.50
42.52
42.54
712
718
724
728
732
736
742
24.80
25.00
25.20
25.40
25.60
25.80
26.00
5 10 15 20
5
10
15
20
Rea
r J
0e (
fA/c
m2)
Front J0e
(fA/cm2)
76.0
77.0
78.0
79.0
80.0
81.0
82.0
83.0
FF (%)(d) (c)
(b) (a)
5 10 15 20
5
10
15
20
Rea
r J
0e (
fA/c
m2)
Front J0e
(fA/cm2)
40.00
40.50
41.00
41.50
42.00
42.50
43.00J
sc (mA.cm
-2)
5 10 15 20
5
10
15
20
Re
ar
J0e (
fA/c
m2)
Front J0e
(fA/cm2)
700
705
710
715
720
725
730
735
740
745
Voc
(mV)
5 10 15 20
5
10
15
20R
ear
J0e (
fA/c
m2)
Front J0e
(fA/cm2)
22.00
22.50
23.00
23.50
24.00
24.50
25.00
25.50
26.00
26.50
Eff (%)
Fig 6.8: Simulation results for the (a) efficiency, (b) Voc, (c) Jsc and (d) FF for a range of J0e on both the front and rear surface passivations.
Rear surface recombination and sheet resistivity – Driving dopants deeper into the silicon
bulk requires relatively high temperatures and long annealing processing. In Chapter 7, which
discusses the fabrication process of IBC solar cells, the rear phosphorus diffusion for the back
surface field (BSF) is introduced at the beginning of the cell fabrication process. Introducing
the BSF at early stages of the fabrication process allows the phosphorus diffusion dopants to
be driven deeper into the silicon with subsequent high-temperature processing. Therefore, the
simulations presented in the following section investigate the different rear sheet resistivities
and J0e in terms of the IBC solar cell performance.
The simulation results for the IBC solar efficiency, Voc, Jsc and FF for the rear surface
recombination are presented in Figure 6.9. The simulation did not input specific diffusion
profiles, but employed lumped parameters for Rsheet and J0,skin to solve for the lateral conduction
98
within the phosphorus diffusion [16, 257]. At a fixed rear J0e recombination value, the
simulation results in Figure 6.9 show improvements in the efficiency and FF with a heavier
rear sheet resistance.
82.30
82.40
82.50
82.60
82.70
714
718
722
726
25.00
25.10
25.20
25.30
25.40
25.50
42.526
42.530
500 1000 1500 2000
5
10
15
20
Re
ar
Ph
osp
horu
s J
0e (
fA/c
m2)
Sheet Resistance (Ω/ )
82.00
82.20
82.40
82.60
82.80
FF (%)
500 1000 1500 2000
5
10
15
20
Re
ar
Ph
osp
ho
rus J
0e (
fA/c
m2)
Sheet Resistance (Ω/ )
712
716
720
724
728
Voc
(mV)
500 1000 1500 2000
5
10
15
20
Re
ar
Ph
osp
ho
rus J
0e (
fA/c
m2)
Sheet Resistance (Ω/ )
24.80
25.00
25.20
25.40
25.60
25.80
Eff (%)
500 1000 1500 2000
5
10
15
20
Re
ar
Ph
osp
horu
s J
0e (
fA/c
m2)
Sheet Resistance (Ω/ )
42.40
42.44
42.48
42.52
42.56
42.60
Jsc
(mA.cm-2)
(a) (b)
(c) (d)
Fig 6.9: Simulation results for the (a) efficiency, (b) Voc, (c) Jsc and (d) FF for various sheet resistivities and J0e for a rear phosphorus diffused surface.
A heavier rear phosphorus sheet resistance is desirable to improve lateral conduction provided
that J0e remains sufficiently low, as shown in Figure 6.9a and 6.9d. Furthermore, a heavier rear
phosphorus diffusion is preferable to having one in the front as this minimizes the loss of short
wavelengths from Auger recombination.
99
6.3.2 Simulation of rear boron-doped emitter
As discussed briefly in Chapter 5, the formation of a boron emitter forms a p-n junction, which
is needed for the fundamental operations of n-type IBC solar cells. The boron emitter provides
a region of high hole and low electron conductivity enabling it to selectively collect
photogenerated holes [258]. The minority carriers generated within the n-type bulk are
collected into the boron emitter during the n-type IBC solar cell operation. Chapter 5 showed
that the surface recombination of the ONO stack on boron diffusion is comparatively higher
than light phosphorus diffusion. The balance of the J0e and emitter fraction must be simulated
to optimise the collection efficiency and resistive effects with the other solar cell parameters.
The collection efficiency is defined as the number of minority carriers collected at the junction
to the number of photons entering the silicon.
This section investigates and simulates the performance of an IBC solar cell as a function of
J0e and boron emitter area fraction.
Simulation details
Simulations of an IBC solar cell were performed with the baseline parameters, except the J0e
for the boron diffusion emitter was varied between 6–100 fA/cm2 and the rear coverage of the
boron emitter was varied between 2–30%. The simulated J0e range is comparable to the
experimental surface passivation results of the ONO stack for boron diffused surfaces (Chapter
5).
Results and discussion
The simulation results for the IBC solar efficiency, Voc, Jsc and FF of the boron emitter
recombination are presented in Figure 6.10. Two trends were observed in Figure 6.10a. First,
the cell efficiency increased with a reduced J0e. Second, an increased boron emitter area with a
sufficiently low J0e was required to reach higher efficiencies. Moreover, the cell efficiency with
a smaller boron diffusion area (2–12%) was observed to have a higher tolerance to J0e as
compared to a larger rear boron diffusion area (>12%). In Figure 6.10c, the increased boron
diffusion area was observed to cause an increase in the Jsc, regardless of the J0e behaviour.
100
As the J0e decreased and boron emitter area increased, Figure 6.10d shows that the fill factor
improved due to the lower resistive effects and improved collection of minority carriers. The
resistive effects observed in Figure 6.10d were verified using the Suns-Voc simulation with
Quokka3 (results not presented here), which showed the fill factor to be similar for a given J0e
across different boron diffusion areas from 2–30%.
82.80
82.60
82.70
82.60
42.54
42.52
710
715
720
722
726
728
25.00
25.60
25.20
25.50
25.40
5 10 15 20 25 30
20
40
60
80
100
J0e (
fA.c
m-2)
Rear Boron Area (%)
82.0
82.2
82.4
82.6
82.8
FF (%)
5 10 15 20 25 30
20
40
60
80
100
J0e (
fA.c
m-2)
Rear Boron Area (%)
40.00
40.50
41.00
41.50
42.00
42.50
43.00J
sc (mA.cm
-2)
5 10 15 20 25 30
20
40
60
80
100
J0e (
fA.c
m-2)
Rear Boron Area (%)
700
704
708
712
716
720
724
728
732
Voc
(mV)
(d)(c)
(b)(a)
5 10 15 20 25 30
20
40
60
80
100
J0e (
fA.c
m-2)
Rear Boron Area (%)
24.80
25.00
25.20
25.40
25.60
25.80
Eff (%)
Fig 6.10: Simulations for the (a) efficiency, (b) Voc, (c) Jsc and (d) fill factor as functions of the boron emitter area fraction (%) and boron emitter J0e values.
The simulated J0e for the boron diffused region contributes to much higher recombination (>6
fA/cm2) as compared to most of the other defined cell region parameters given in Table 6.3.
Therefore, the simulation results presented in Figure 6.10b show that an increasing boron
diffusion area causes a decreased Voc.
101
6.3.3 Simulations for rear phosphorus-doped contact region
The heavily doped phosphorus diffusion on the n-type IBC solar cell is primarily to achieve a
low contact resistivity between the silicon and metal contacts and improve the collection of
majority carriers. It is more difficult to achieve ohmic contact towards an n-type silicon wafer
due to the potential barrier from the bandgap offset and high defect interface states from the
silicon-metal interface (see Appendix B). Heavily doped phosphorus diffusion reduces the
potential barrier between metals and silicon to more easily allow electrons to tunnel through.
Thus, this section shows the investigations and simulations for the IBC solar cell performance
over a range of J0e and area fractions for heavily diffused phosphorus region.
Simulation details
Simulations for an IBC solar cell were performed with the baseline parameters, except the J0e
for heavy phosphorus diffusion was varied between 80–300 fA/cm2, and the rear coverage of
the phosphorus diffusion area was varied between 0.4–5%. A lower area fraction of 0.4% was
not simulated due to the limitations of the fabrication process that limit achieving such a
resolution.
Results and discussion
The simulation results for the IBC solar efficiency, Voc, Jsc and FF of the heavy phosphorus
recombination are presented in Figure 6.11. It was observed that the efficiency in Figure 6.11a
decreased with an increased J0e and rear phosphorus diffusion area.
The Voc decreased with an increasing heavy phosphorus diffusion area, as presented in Figure
6.11b. The fill factor shown in Figure 6.11d for a given J0e may improve marginally with an
increasing phosphorus area due to an increased majority carrier collection. However, the
recombination of heavy phosphorus diffusion dominates with simulated J0e >80 fA/cm2, which
causes the efficiency to decrease with the increased heavy phosphorus diffusion area. Only a
small fraction of the heavy phosphorus diffusion area (0.4–0.8%) is needed to achieve high
efficiency.
102
82.60
82.75
82.7042.528
42.532
720
722
724
726
728
730
25.30
25.40
25.50
25.60
25.65
1 2 3 4 5
100
150
200
250
300
J0e (
fA.c
m-2)
Rear Phos Area (%)
82.0
82.2
82.4
82.6
82.8
FF (%)
1 2 3 4 5
100
150
200
250
300
J0e (
fA.c
m-2)
Rear Phos Area (%)
42.00
42.20
42.40
42.60
42.80
Jsc
(mA.cm-2)
1 2 3 4 5
100
150
200
250
300
J0e (
fA.c
m-2)
Rear Phos Area (%)
710
714
718
722
726
730
Voc
(mV)
1 2 3 4 5
100
150
200
250
300J
0e (
fA.c
m-2)
Rear Phos Area (%)
24.00
24.50
25.00
25.50
26.00
Eff (%)(a) (b)
(c) (d)
Fig 6.11: Simulations for the (a) efficiency, (b) Voc, (c) Jsc and (d) fill factor on heavy phosphorus area fraction (%) with a range of phosphorus J0e values.
6.3.4 Simulation of different pitch sizes for the ONO IBC solar cell
The pitch of an ONO IBC solar cell in this work is defined between the adjacent phosphorus
contact dots, as illustrated in Figure 6.6. The pitch length of an IBC solar cell affects the
efficiency of the carriers collected. A larger pitch would require the carriers to travel further
before collection.
In this section, different IBC solar cell pitches were simulated while maintaining the area ratio
of all other parameters (boron emitter, heavy phosphorus and metal dot opening).
103
Simulation details
Simulations for an IBC solar cell were performed with the baseline parameters, except the pitch
of the cell was varied between 400 to 1000 µm while maintaining a similar area ratio for all
other parameters.
Results and discussion
The simulation results for the IBC solar efficiency, Voc, Jsc and FF of different pitch sizes are
presented in Figure 6.12. The plotted cell efficiencies in Figure 6.12a decreased as the pitch
size increase.
The decreased cell efficiency is mostly due to the decreased fill factor, as shown in Figure
6.12b. The Voc of the cell is maintained for different pitch sizes due to the similar fractional
area of the defined parameters. However, the fill factor and Jsc decreased due to increased series
resistance. As the pitch size increased, the carriers that are generated at the front surface have
to travel further before being collected at the rear junction of the device [259].
400 500 600 700 800 900 100081
82
83
Jsc
FF
(b)
FF
Jsc
Pitch (µm)
Fill
Facto
r (%
)
42.40
42.44
42.48
42.52
42.56
42.60
Jsc (
mA
/cm
2)
400 500 600 700 800 900 1000724
726
728
730
732
Eff
Voc
Eff
Pitch (µm)
Voc
(mV
)
(a)
Voc
25.0
25.1
25.2
25.3
25.4
25.5
25.6
25.7
Eff
icie
ncy(
(%)
Fig 6.12: Simulations for the (a) efficiency and Voc and the (b) Jsc and fill factor as functions of the pitch size while maintaining similar features for the area ratio.
Reducing the pitch size improved the cell efficiency due to lower series resistance effect.
However, limitations in the cell fabrication process place a lower limit on the pitch size as this
requires greater precision in the cell alignment process.
104
6.3.5 Simulation of bulk lifetime, resistivity and edge recombination
High bulk lifetimes in wafers are required for high-efficiency IBC solar cells. The carriers
generated at the front are must travel through the thickness of the wafer to be collected at the
rear junction. High resistivity wafers can readily achieve higher bulk lifetimes due to the lower
Auger recombination. However, edge recombination is reported to have a larger effect for
wafers with higher resistivities [11].
In this section, n-type 1–100 Ω.cm resistivity wafers with various bulk lifetime were
investigated with and without edge recombination.
Simulation details
Two sets of simulations were performed for IBC solar cells in this section. The first simulation
was performed using the baseline parameters, except the wafer resistivity and bulk lifetime
were varied between 1–100 Ω.cm and 1–100 ms, respectively. No edge recombination was
considered in the simulation.
The second simulation was performed with a quarter of a full area IBC solar cells accompanied
by two extended regions away from the active cell area of 3 cm. The extended region was
shaded to simulate edge recombination. The simulations performed were similar to the baseline
parameters; however, three changes were made to the cell design. First, the diffusion and metal
opening contacts were defined as a line as compared to dots before. Second, the defined lines
had similar area ratio as the defined dots and open dot contacts. Third, for each bulk resistivity,
the bulk lifetime was set using the parametrised Auger limit [17].
Results and discussion
The first simulation results for the IBC solar efficiency, Voc, Jsc and FF of different wafer
resistivities and bulk lifetimes are presented in Figure 6.13. The wafer resistivities in Figure
6.13 are given in terms of the doping concentration. The simulated results in Figure 6.13a show
two trends. First, the efficiency improved with higher bulk lifetimes. Second, wafers with
higher resistivities were capable of achieving a higher cell efficiency, Voc and Jsc.
Wafers with higher resistivities can achieve higher lifetimes and longer diffusion lengths due
to the lower Auger recombination within the bulk. The longer diffusion lengths increased the
105
Jsc, and the higher bulk lifetimes increased the Voc. The simulation results show that higher
bulk lifetimes for wafers with higher resistivities should improve cell efficiency. However, the
simulation results did not include edge recombination of the cell.
Fig 6.13: Simulations for the (a) efficiency, (b) Voc, (c) Jsc and (d) fill factor as functions of the wafer resistivity and bulk lifetime.
The simulation results for IBC solar cells with defined edge recombination at different wafer
resistivities are plotted in Figure 6.1a. The results show that efficiency was reduced from
between 0.28–0.40%. The differences in efficiency were observed to decreases as the bulk
resistivity decreased. This is due to the fill factor having less of an influence on the edge
recombination and the carriers are more easily collected with lower bulk resistivities, as shown
with simulation results in Figure 6.14b. The bulk lifetime for the parameterised Auger limit
and a specific cell thickness of 230 µm allowed the high resistivity wafers of 100 Ω.cm to
achieve higher efficiency for the IBC solar cell as compared to lower resistivities [17].
106
1014
1015
81.5
82.0
82.5
83.0(b)
FF no edge
Jsc
no edge
FF edge
Jsc
edge
ND Doping Density (cm
-3)
Fill
Fa
cto
r (%
)
41.5
42.0
42.5
Jsc (
mA
/cm
2)
1014
1015
715
720
725
730
Eff with edge
Eff no edge
Voc
no edge
Eff edge
Voc
edge
Eff no edge
ND Doping Density (cm
-3)
Vo
c (
mV
)(a)
24.5
25.0
25.5
Eff
icie
ncy(
(%)
Fig 6.14: Simulations for the (a) efficiency and Voc and the (b) Jsc and fill factor as functions of the wafer resistivity with and without edge recombination.
6.3.6 Simulation of series and shunt resistance
Series and shunt resistance in a solar cell reduce the efficiency by dissipating power in the
resistances. The total series resistance within the cell can be ascertained from the current
resistance through the emitter and bulk, the contact resistance of the metal contact on silicon
(reviewed in Appendix B) and the grid resistance of the metal fingers and busbar. The shunt
resistance persists due to current leakage within the device from fabrication defects, such as
overlapping metallisation on the diffusion overlap regions.
In this section, a range of series and shunt resistances were simulated to evaluate the
performance of an IBC solar cell. As part of the solar cell design, only contributions to the
series resistance from the fingers and busbar were assessed.
Simulation and calculation details
Simulations for the IBC solar cell were performed using the baseline parameters, except the
series and shunt resistances were varied between 0.1 to 2.0 Ω.cm2 and 100 to 100k Ω.cm2,
respectively.
The rear metal grid resistance of an IBC solar cell was calculated using Eq 6.6.
z. = 13 oo uo= (6.6)
107
WF: Width of metallised finger HF: Thickness of metallised finger LF: Length of metallised finger P: Pitch size of the cell
Results and discussion
The simulation results for the IBC solar efficiency, Voc, Jsc and FF with different series and
shunt resistances are presented in Figure 6.15. The increased series resistance and reduced
shunt resistance caused a decrease in cell efficiency. The series and shunt resistances affected
both the Jsc and fill factor, as shown in Figures 6.15c-d, respectively. However, the series
resistance did not affect the Voc as no net current flow was obtained during the operation of the
cell at Voc. The cause of the high series and low shunt resistances in a solar cell are normally
due to poor cell design or fabrication defects.
The grid resistance from fingers and busbar contributes in part to the total series resistance of
a solar cell. The calculated metal grid resistance shown in Figure 6.15a with a ~92% rear
coverage on a 4 cm2 cell and 3 µm thickness of Al on the rear is ~0.07 Ω.cm2, which contributes
to a loss in fill factor of ~0.35% according to Eq 6.7. Other metals, either Ag or Cu, with similar
area coverages and thicknesses show a grid resistance of ~0.04 Ω.cm2, with a lower loss in the
fill factor of ~0.2% as plotted in Figure 6.15.
∆ = ; z.c.1n@1 (6.7)
The use of Ag for metallisation at the rear is preferred when compared to Al and Cu due to the
low resistivity and lower absorption at longer wavelengths when used concurrently as a back
reflector. However, the adhesion of specific metals to silicon or dielectrics must be considered
during the cell fabrication process.
108
83.00
82.50
82.00
81.00
80.00
75.00
42.50
25.50
25.00
24.50
23.50
0.1 1.0102
103
104
105
Sh
un
t R
esis
tan
ce
(Ω
.cm
2)
Series Resistance (Ω.cm2)
65
70
75
80
(d) (c)
(b)(a)
0.1 1.0102
103
104
105
42.30
Sh
un
t R
esis
tan
ce
(Ω
.cm
2)
Series Resistance (Ω.cm2)
40.00
41.00
42.00
43.00
0.1 1.0102
103
104
105
725
726Sh
un
t R
esis
tan
ce
(Ω
.cm
2)
Series Resistance (Ω.cm2)
710
715
720
725
730
727
0.1 1.0102
103
104
105S
hu
nt
Re
sis
tan
ce
(Ω
.cm
2)
Series Resistance (Ω.cm2)
19.00
21.00
23.00
25.00
Fig 6.15: Simulations for the (a) efficiency, (b) Voc, (c) Jsc and (d) fill factor as functions of the series and shunt resistances.
10-1 100 101
10-2
10-1
100
101
10-1 100 101
75
76
77
78
79
80
81
82
83(a)
Meta
llisa
tion s
erie
s r
esis
tance
(Ω
.cm
2)
Metallisation finger thickness (µm)
Aluminium Silver
Copper
Fill
facto
r (%
)
Metallisation finger thickness (µm)
Aluminium
Silver
Copper
(b)
Fig 6.16: (a) Series resistance as calculated for an IBC solar cell with a pitch size of 500 µm for a cell size of 4 cm2, and (b) the behaviour of the fill factor as a function of the metallisation finger thickness.
109
6.4 Chapter Summary
This chapter covers the detailed effects of the optical losses, recombination losses, series
resistances and shunt resistances. The calculated and modelled solar cell parameters present an
in-depth analysis for the ways to improve cell performance by individually reducing each of
the losses.
Thermal SiO2 within the ONO stack behaves parasitically from an optical perspective due to
the thermal SiO2 refractive index mismatch between the silicon and the PECVD SiNx. However,
considering the passivation of the ONO stack on diffused surfaces, the optimum ONO stack
for an ARC with a thermal SiO2 thickness of 11–16 nm has a PECVD SiNx n632 of ~1.94 with
a thickness between 53–48 nm and a PECVD SiOx thickness of ~92 nm.
Device simulations for the ONO IBC solar cell were performed over a range of surface and
bulk recombination, diffusion fractions, pitch sizes, bulk resistivities and series and shunt
resistances. The information obtained was applied to the cell design and fabrication processes,
which are discussed in Chapter 7. The contact resistivity of metal to silicon contacts was not
covered in this chapter, but is reviewed in Appendix B.
110
Chapter 7
7.1 Introduction
Building on the simulation results presented in Chapter 6, the fabrication, characterization and
analysis of high-efficiency n-type ONO IBC solar cells are detailed and discussed in this
chapter. The fabrication of ONO IBC solar cells involves the use of photolithography and
numerous high-temperature processing steps. Four key aspects of the cell design and
fabrication are also investigated, including the implementation of the boron-rich layer gettering,
design of the ONO surface passivation on the IBC solar cell, effects of positive corona charging
on the completed cells and an alternative metallisation method based on lift-off processing.
Lastly, the improvements culminated in a champion ONO IBC solar cell with a certified cell
efficiency of 25.0%.
7.2 Fabrication sequence
The ONO IBC cells were fabricated using n-type FZ 100 Ω.cm silicon wafers. The fabrication
process involved multiple processes, including chemical cleaning, pre-oxidation of the wafer,
gettering of the metal contaminants, diffusion, chemical masking, photolithography patterning
of localised diffusions, surface texturing, ONO surface passivation and metallisation of the
fingers and busbar. Each of the processing steps are discussed in the following section. An
overall visual illustration and flow chart of the ONO IBC solar cell fabrication process are
presented in Figures 7.1 and 7.2.
Fabrication and analysis of ONO IBC solar
cells
111
Fig 7.1: Visual illustration of the fabrication sequence for an ONO IBC solar cell with rear localised n+ and p+ emitters with localised contacts.
7.2.1 Chemical cleaning
The fabrication of IBC cells involves multiple high-temperature steps (>700 ˚C). Subjecting
the wafers to repeated high-temperature furnaces and photoresist spinning steps poses the risk
of metal and organic contamination on the wafer. Metal contaminants unintentionally diffuse
into the bulk and act as active recombination centres to reduce the bulk lifetime of the wafer
[260, 261]. The exposure of organic contaminants can potentially reduce the electronic
performance on the silicon surface [262]. To reduce the contamination risk of both organic and
metallic impurities, RCA cleaning is commonly used within the silicon semiconductor industry
to chemically clean silicon wafers [263].
The RCA cleaning consists of two chemical cleaning stages. The first, commonly known as
RCA1, removes organics and several species of metal contaminants. Silicon wafers are
subjected to a RCA1 solution, which consists of DI H2O, electronic grade NH3OH and H2O2.
The H2O2 grows a thin layer of oxide on the silicon and removes organic surface films, while
the NH3OH dissolves and removes metal impurities such as gold, copper and chromium [263].
The wafers were cleaned in the RCA1 solution for approximately ten minutes at 55–65 ˚C. The
1) Pre-oxidation
2) POCl3 gettering
3) Etch wafer
4) L POCl3 diffusion
5) SiO2-Si3N4 mask
6) Photolithography
7) H POCl3 diffusion
8) SiO2-Si3N4 mask
9) Photolithography
10) BBr3 diffusion
11) SiO2-Si3N4 mask
12) Random Texture
13) L POCl3 diffusion
14) ONO passivation
15) Photolithography
16) Al evaporation
17) Photolithography and
Al etch
112
silicon wafers were then rinsed and dipped into a mixture of HCl, HF and H2O to remove the
sacrificial oxide layer [264].
Fig 7.2: Flow diagram of the fabrication sequence for an ONO IBC solar cell.
The second cleaning stage, commonly known as RCA2, removes the remaining metal
contaminants [263]. The wafers are subjected to a RCA2 solution, which consists of DI H2O,
electronic grade HCl and H2O2. Similar to the first cleaning, the H2O2 grows a thin layer of
oxide, while the HCl removes the alkali ions (Al+3, Fe+3 and Mg+2), which were insoluble in
the first NH3OH solution. The wafers were cleaned in RCA2 for approximately ten minutes at
55–65 ˚C. Finally, the wafers were subjected to another mixture of HF, DI H2O and HCl to
remove the second sacrificial oxide [264].
Photolithography
2. Pre-oxidation
of wafer
1. Damage etch
4. Thinning of
wafer by etching
5. Light
phosphorus
diffusion
RCA Clean
RCA Clean
3. Phosphorus
gettering
6. Masking
RCA Clean
RCA Clean
7. Define
phosphorus
dots
Photolithography
8. Heavy
phosphorus
diffusion
TMAH RCA Clean
9. Masking
RCA Clean
10. Define boron
dots opening
11. Boron
diffusion
TMAH RCA Clean
12. Masking
13. Random
Texturing
TMAH RCA Clean
14. Light
phosphorus
diffusion
RCA Clean
RCA Clean
15. Thermal
oxidation
16. PECVD SiNx
17. PECVD SiOx
RCA Clean
18. Define metal
dot opening
19. Metal
evaporation
Photolithography
RIE
20. Metal
separation
Photolithography
21. Sintering of
metal contacts
Phosphorus Dots
Boron Dots ONO
Metallisation
113
7.2.2 Pre-oxidation of wafers
FZ wafers may have defects within the bulk as either interstitials or vacancies, which develop
during the ingot growth. These point defects are dependent on the growth rate (V) and thermal
gradient (G) of the ingot. Silicon interstitials are formed with a slow growth rate (below the
critical value of V/G), while vacancies are formed at a fast growth rate (above the critical value
of V/G) [265].
(a) (b)
Fig 7.3: Photoluminescence (PL) images of ring defects on FZ wafers during the IBC solar cell fabrication. (a) Lifetime calibrated PL image of a wafer taken after phosphorus diffusion. (b) Uncalibrated PL image of a wafer with ring defect taken after completing high temperatures wafer processing.
To suppress the interstitial and vacancy-related defects and strengthen the ingot, wafer
manufacturers introduce N2 doping during the growth of the silicon ingot crystal [266, 267],
with most of the N2 retaining its molecular form because it is a more favourable configuration
within the crystal [266]. However, N2 doping also introduces electrically active point defects
at deep levels, which lowers the bulk lifetime of the wafers and often exhibits radially-
symmetric low lifetime regions on the wafer [268]. The PL imaging for these wafer defects are
presented in Figure 7.3 as taken during the IBC cell fabrication process. Abe et al. and Grant
et al. reported that annealing FZ wafers at temperatures above 1000 ˚C for 10 minutes or more
in O2 can permanently deactivate these defects and restore the bulk lifetime [199, 200, 266].
Therefore, the FZ silicon wafers selected for cell processing were pre-oxidized to prevent these
deep level active point defects from forming during cell processing [200]. The established
process for cell fabrication in this work was to perform a silicon etch in TMAH for ten minutes
at 85 ˚C, followed by RCA cleaning and loading into the oxidation furnace at 900 ˚C for
114
oxidation at 1050 ˚C for an hour in O2 ambient with a 3% mixture of Trans 1,2-
dicholoroethylene (TLC).
7.2.3 Gettering
Gettering is the process of removing impurities or contaminants from an active region to a pre-
defined region in a silicon wafer. The basic gettering mechanisms can be defined as either
‘relaxation’ or ‘segregation’ gettering [269].
Relaxation gettering involves the precipitation of impurities at regions with high precipitation
site densities, such as surfaces or dislocations. As relaxation gettering is limited by the
solubility limit of the contaminants, lower annealing temperatures are required to reduce the
solubility limit and increase the maximum gettering effectiveness. However, the gettering
process may then require longer anneal times at these lower temperatures due to the reduced
diffusivity of the contaminants.
Segregation gettering is due to differences in the solubility of the impurities present within a
region of the bulk. For example, contaminants are driven towards the heavily phosphorus
diffusion due to higher solubility limit for metal contaminants within the diffused region.
Segregation gettering is not limited by the solubility limit of the wafer bulk and, therefore, can
reduce the contaminant’s concentration below its solubility limits, even at high temperatures.
Phosphorus diffusion gettering may involve a much more complicated mechanism depending
on the processing conditions. High phosphorus concentrations that are insoluble at the surface
of the wafers during diffusion causes the formation of SiP precipitates. These precipitates have
been reported to be very effective gettering sites for Ni and Pt [270, 271]. Schröter et al.
demonstrated that phosphorus diffusion gettering is dependent on the formation of PSG and
the plateau region of the diffusion [272]. The injection of silicon interstitials is thought to be
the mechanism by which the gettering occurs. Syre et al. reported that another possible
phosphorus gettering mechanism during phosphorus diffusion is due to the growth of SiO2
precipitates at vacancy rich regions, in which the SiO2 precipitates act as gettering centres [273].
The conditions for phosphorus gettering may consist of multiple complex mechanisms that are
dependent on the diffusion process. However, the general consensus is that heavy phosphorus
diffusion can effectively getter metal contaminants [272, 274].
115
The fabrication of IBC solar cell wafers has two phosphorus diffusion gettering steps. The first
gettering was performed after the pre-oxidation, which was subsequently etched in TMAH.
The second gettering was implemented during the formation of the heavy phosphorus diffusion.
The front surface of the wafers, which was intentionally exposed to heavy phosphorus diffusion,
had a sheet resistivity of ~15 Ω/. The heavy phosphorus diffused layers on the front surfaces
were retained until the cells reached the front surface texturing stage. During the boron emitter
formation on the rear patterned dots, BRL were maintained for gettering purposes [275]. The
implementation and analysis of the BRL gettering are discussed in Section 7.3.1.
7.2.4 Masking layer
Thermal SiO2 is commonly used as a masking layer for both boron and phosphorus diffusions
due to the slow diffusivity of the dopants. A 10 nm thermal SiO2 is reportedly required to mask
the boron diffusion for approximately 2 hours at 1000 ˚C [276]. However, it was found that
such a thin thermal SiO2 was unable to mask the boron diffusion required for cell fabrication.
A thermal SiO2 thickness of ~120 nm grown in the lab was required to mask the boron diffusion
performed at 940 C for 40 minutes. Two possible explanations for the required thicker thermal
oxide may be due to the presence of H2 within the SiO2. The literature has shown that dry SiO2
containing H2 increases the diffusivity of both boron and phosphorus [277]. Another possible
reason may be that the boron reacts with SiO2 to form B2O3, which causes boron to diffuse into
the silicon.
As the fabrication of an ONO IBC solar cell requires three masking steps, repeated growths of
multiple thermal dry or wet SiO2 layers for long durations at high temperatures would
drastically change the diffusion profiles. To minimise the thermal budget required for growing
the masking layers, a thin SiO2 and LPCVD Si3N4 stack was implemented to mask the thermal
diffusions.
Thermally grown Si3N4 has been reported to be an effective pinhole-free barrier against boron
diffusion [278]. The combination of thermal SiO2 capped with LPCVD Si3N4 was tested and
found to mask both boron and phosphorus diffusions more effectively than the oxide alone. A
thin thermal SiO2 layer of 2–5 nm was initially grown on the wafer to prevent contamination
from the LPCVD SiN3N4 deposition while minimising changes to the diffusion profile. The
thermal SiO2 was grown with cell wafers loaded into the furnace at 700 ˚C and ramped up to
850 ˚C in O2. As soon as the temperature reached the set point of 850 ˚C, the wafers were
116
ramped down in O2 and unloaded at 700 ˚C. The oxidized wafers then had LPCVD Si3N4
deposited to thicknesses of 50–70 nm. The wafers loaded into the LPCVD chamber were
deposited at 780 ˚C with a DCS and NH3 flow of 40 and 120 sccm, respectively, and a chamber
pressure of 450 mTorr. In addition to testing against boron and phosphorus diffusions, the
stacks were subjected to further testing with TMAH chemical etching. The SiO2-Si3N4 stack
was etched in TMAH at 85 ˚C for an hour and showed no etched pits, indicating that the SiO2-
Si3N4 stack was free of pinholes and capable of masking the TMAH etch and texturing solution.
7.2.5 Photolithography patterning
MicroChemicals positive photoresists of AZ1518 and AZ4562 were used to pattern the rear
dots and protect the surface passivation from exposure to buffer HF (BHF). The differences
between the two photoresists are in their viscosity and thickness after spin coating. The AZ1518
is a thin photoresist capable of achieving thicknesses between 1.5–2.5 µm, whereas the AZ4562
is a thicker photoresist capable of achieving thicknesses between 6–15 µm. The AZ1518
photoresist was used specifically to define the rear patterning, whereas the thicker AZ4562
photoresist was used to protect the peaks and troughs of the textured surfaces from chemical
etching.
A successful spin coating process for the photoresist requires the following: good adhesion
between the photoresist and the dielectric surface, the photoresist is free of particles and air
bubbles, a clean formation and opening for the patterns and clean removal of the photoresist.
The photolithography was performed using the sequence of steps described below:
1. First prebake: prior to spinning, the wafers were baked in an oven at 100–110 ˚C for
10–15 minutes to remove any moisture.
2. Photoresist spin cast: a slow continuous flow of photoresist was squeezed from a pipet
to avoid the formation of bubbles. The wafers with photoresist were spun at 2500 –
3000 rpm for 45 seconds. After spinning, the uniformly coated wafers were rested in a
fume hood for ten minutes.
3. Second Prebake: the wafers were baked at 90 ˚C for 10–20 minutes in an oven to reduce
the solvent concentration. After unloading, the cells rested for an additional ten minutes
at room temperature.
4. UV exposure: the wafers were loaded onto the mask aligner and a chrome photomask
was used to define the regions for UV exposure for 45 seconds.
117
5. Development: The AZ326 MIF developer was used to develop the exposed regions.
The wafers were agitated in the developer for 90 seconds and spin rinsed at 2000 rpm.
A visual inspection was performed to ensure the adhesion of the photoresist to the
wafers.
6. Hard bake: the wafers were hard baked in an oven at 110 ˚C for 20 minutes to increase
the chemical and physical stability of the photoresist.
7. Etching of the exposed dielectric layers: RIE was performed on the wafers to remove
the exposed SiO2-Si3N4 layer. The wafers were then submerged in a 25% BHF solution
until the features became hydrophobic.
8. Removal of the photoresist: a sequence of three acetone baths and spin rinsing were
used to remove the photoresist layers.
In a high humidity environment conditions (rainy day), the photoresist was found to adhere
poorly onto the SiOx layer. In such cases, the MicroChemicals TI PRIME adhesion promoter
was spun on to the SiOx prior to the photoresist to mitigate the poor adhesion.
7.2.6 Diffusions process
All diffusions were performed in a Tempress 6-inch tube furnace with boron tribromide (BBr3)
and phosphorus oxychloride (POCl3) as the dopant sources for boron and phosphorus
diffusions, respectively. As indicated in Figure 7.2, the diffusions required for the cell
fabrication included heavy phosphorus diffusion for gettering, heavy phosphorus diffusion for
the localised contact, localised boron diffusion for the emitter formation, and light phosphorus
diffusion for the front and back surface fields.
Prior to thermal diffusion, all wafers were cleaned with freshly prepared RCA and HF dips.
The wafers were loaded at 700 ˚C in O2 and ramped up to the set temperatures at a rate of 10
˚C/min in ambient O2. Phosphorus diffusions and the phosphorus gettering process were
performed with gas flow rates of 2.5 slm of N2, 130 sccm of the N2 carrier gas with POCl3 and
65 sccm of O2. The boron emitter diffusion had a gas flow rate of 2.5 slm N2, 18 sccm for N2
as the carrier gas for BBr3 and 18 sccm of O2. After the diffusion, the furnaces were ramped
down to 700 ˚C in O2 at a rate of 10 ˚C/min, except for the boron and phosphorus gettering
processes. Phosphorus gettering diffusions were ramped down in ambient N2 at a rate of 5
˚C/min and unloaded at 600 ˚C, whereas the boron diffusions were ramped down in either
118
ambient O2 or N2 at a rate of 10 ˚C/min. Figure 7.4 plots the thermal profiles for each of the
performed diffusions.
0 20 40 60 80 100 120 140500
600
700
800
900
1000
780 °C
850 °C
860 °C
Te
mp
era
ture
(°C
)
Time (min)
Boron
POCl Gettering
Heavy POCl Light POCl
940 °C
Fig 7.4: Thermal profiles for the heavy phosphorus, front surface field (FSF) and back surface field (BSF) with light phosphorus, boron emitter and phosphorus gettering.
7.2.7 Texturing
Random alkaline texturing can be performed using a mixture of TMAH, H2O, orthosilicic acid
and isopropanol (IPA) [279-281]. During the initial development of the ONO IBC solar cells,
a series of experiments were performed to optimise the texturing process over a range of
solution temperatures, IPA surfactants, orthosilicic acid crystals, TMAH concentrations and
silicon surface conditions. However, no conclusive outcomes were drawn from the various
experiments. Repeating similar texturing conditions on the IBC cells had poor consistency and
occasionally incomplete texturing with the observed planar regions examined under the
microscope. The average variation in the reflection measured across 600–900 nm varies from
10–15%. The poor consistency and texturing uniformity were postulated to be due to IPA
evaporation and the detachment of hydrogen bubbles.
The formation of hydrogen in the TMAH texturing solution has been reported to be both
important for and a hindrance to the formation of randomly textured pyramids. The formation
of pyramids is thought to be due to the generation of hydrogen bubbles that act as a shield
during the TMAH-Si etching and with the preferential etching of the 100 plane over the 111
plane [282, 283]. However, there are reports that suggest the accumulation of large hydrogen
119
bubbles (2–3 mm) adhering to the surface of the wafer for too long may inhibit pyramid
nucleation and uniformity [284, 285]. Therefore, adding an appropriate amount of IPA has
been understood to improve the wettability of silicon [283], hinder the etching rates of certain
crystallographic planes [286] and remove the hydrogen bubbles from the surface during
texturing to improve the uniformity with alkaline textured solutions [284, 287, 288].
Moreover, Amouzgar et al. reported that the additional gas lift effect, which removes hydrogen
bubbles on the surface, reduces the required etch time and improves the uniformity of the
random texture [285]. However, the addition of IPA does not guarantee a uniformly random
texture. The evaporation of IPA over the duration of the texturing process may cause uniformity
issues [289]. As the boiling temperature of IPA is ~82 ˚C, Jiang et al. observed non-uniformity
of a planarized surface when texturing was performed at 80 ˚C [289]. They therefore suggested
a two-step temperature process to avoid IPA evaporation; loading the wafers at 75 ˚C followed
by a slow increase at 1 ˚C/min to 80 ˚C. They proposed that a low temperature of 75 ˚C
promotes a large amount of pyramid nucleation sites, and increasing the etching temperature
to 80 ˚C improves the growth of the formed pyramids [289]. However, no satisfactory and
consistent texturing results were achieved after considering and implementing most of the
procedures suggested in the literature. To improve the texturing repeatability, the IPA
surfactant was substituted for an industrial additive, monoTEX-F with TMAH.
(a) (b)
Fig 7.5: SEM images taken from Liang et al. [290] of the pyramids formed using the TMAH texturing solution with the (a) monoTEX addictive and the (b) IPA surfactant.
120
The industrial monoTEX-F additive has been reported to provide repeatable and consistent
textured reflectances of ~11% at wavelengths from 400–1100 nm [243]. The surface
preparation for texturing with monoTEX-F requires a native RCA1 chemical oxide, whereas
the conventional IPA texturing solution requires wafers to be hydrophobic. The pyramidal
formation in Figure 7.5 shows that smaller pyramids are formed with the monoTEX-F and that
the texturing process etches less silicon relative to the IPA surfactant. The measured reflectance
of the monoTEX-F wafers was on average of 10–12% at wavelengths from 400–900 nm with
no flat surfaces observed under the microscope.
7.2.8 Metal contact and finger patterning
The baseline fabrication process to form metal contact and finger patterns on the ANU IBC
solar cell are based on the etching of thermally evaporated Al layers. First, the dielectric layers
are locally etched using a photolithography mask. After removing the photoresist, Al is
thermally evaporated onto the rear of the cell, followed by photoresist patterning for the p and
n fingers and a final etch of the exposed Al using a mixture of phosphoric acid to form the
defined p and n fingers.
Although this same process was successfully implemented for previous record-breaking cells
[14], the process was marred by the occasional formation of poor contacts. The prevailing
hypothesis for the source of randomly occurring poor contacts are the formation of native
oxides prior to metal evaporation or the surface contamination of the contact surfaces from
exposure to the photoresist and organic solvents during resist removal immediately prior to
metal evaporation. In an attempt to resolve this ongoing issue, two different metallisation
processes were tested for the fabrication of the ONO IBC solar cells.
The first method is the baseline method. Prior to metal evaporation, all wafers were subjected
to either a BHF or a quick diluted HF-dip to remove the native oxides that formed on the
exposed Si surfaces. The metallisation was performed in a modified Varian thermal bell jar
evaporator, capable of evaporating three boats individually in a single run without breaking the
chamber vacuum. Al pellets with a purity of 99.999% (5N) were loaded onto the three boats
and wafers placed one meter above the metal source to avoid unnecessary heating from the
evaporation. A supplied power of 550–650 W was applied across the metal boat after the
chamber was pumped down to 7.5 × 10-5 Torr. An initial pre-melt of the metal was performed
while the shutter was closed. The pre-melt stage is important as it has been observed to achieve
121
a low contact resistivity [254]. This is thought to be due to contaminants from the metal source
or tungsten boat and surrounding crucible shield that evaporates before the targeted metal has
melted [254]. Therefore, the shutter remains closed to prevent these initial evaporations with
possible contaminants from being deposited onto the wafer. After the metal on the boat had
melted sufficiently over a defined period, the shutters were opened and deposition began with
an average rate of 6–10 Å/sec. This process was similarly performed for the remaining two
boats with the other materials. The temperature measured at the control wafer placed nearly a
meter high from the sources did not exceed 80 ˚C after all three depositions were performed.
The chamber was vented in N2 gas after reaching the set targeted thickness of ~1 µm. Two
subsequent runs were performed on the cell to reach a total Al thickness of ~3 µm.
The second “lift-off” metallisation method, which attempts to resolve the contact problem, is
discussed in a later section.
7.3 Improvements to the ONO IBC cells fabrication process
This section describes the process and performance of the various fabricated IBC solar cells.
Firstly, we examine BRL as a source for gettering during cell processing. Previously developed
surface passivations for the front SiNx-SiOx and rear SiO2-Si3N4 stacks on IBC solar cells were
analysed and compared with the developed ONO surface passivation [14]. The effect of corona
charging on the completed cells was examined and is presented. Finally, the performance of
different metallisation schemes on similar ONO IBC solar cells was evaluated.
7.3.1 Boron-rich layer gettering
The boron-rich layer (BRL) gettering process is less established compared with phosphorus
diffusion gettering for cell fabrication. However, the implementation of a BRL gettering
sequence in this IBC cell fabrication process substantially reduces the amount of additional
high-temperature processing steps required for phosphorus gettering and removes the slow
diffused contaminants within the boron diffused region.
The BRL is a silicon boride layer with electrically inactive boron atoms that form between the
boron silicate glass (BSG) and the heavily boron-doped region in the silicon. The mechanism
of BRL gettering was suggested by Phang et al. as being caused by the segregation effect of
122
impurities into the BRL [275]. A total of 99.9% of Fe defects in intentionally contaminated
monocrystalline FZ silicon wafers were reported to be gettered into the BRL without significant
bulk degradation [274, 275]. However, the gettered impurities were released back into the
silicon bulk if the BRL was oxidised into BSG at high temperatures [275]. Moreover, the
surface passivation quality was limited due to the high surface concentration of boron, which
is coupled with the formation of the BRL. To retain the gettering effectiveness of the BRL and
improve the surface passivation quality, the BRL can be chemically removed using boiling
HNO3. The surface concentration can then be lowered for surface passivation by driving the
diffusion profile deeper into the bulk.
In this section, the lifetime of the wafers with the BRL and phosphorus gettering was
investigated for various type of wafers and resistivities.
Experimental details
To investigate the impact of BRL gettering, different dopant types (n- and p-type), growth
conditions (FZ and Cz), and resistivities (1 and 100 Ω.cm) were subjected to (i) a boron
diffusion without a BRL, (ii) a boron diffusion with a BRL and (iii) a heavy phosphorus
diffusion. A set of control wafers were considered without any diffusion. The conditions under
which the experiments for boron diffusion with and without a BRL and phosphorus diffusion
were performed similar to the cell fabrication process (Section 7.2.6). The ramp down from
940 to 700 ˚C was performed in either pure ambient N2 to retain the BRL or in pure ambient
O2 to oxidise the BRL. The measured sheet resistivity of the boron diffusions with and without
the BRL were approximately 60 and 120 Ω/, respectively, and sheet resistivity for the
phosphorus diffusion was ~30 Ω/.
All diffused and control wafers were chemically oxidised with boiling nitric acid and etched in
TMAH. Thereafter, they were passivated with an identical ONO dielectric stack, and the
injection carrier lifetime was measured at ∆n = 1014 cm-3.
Results and discussion
The results presented in Figure 7.6a show that regardless of the doping concentration and
growth method of the wafers, the boron diffusion without the BRL leads to a lower lifetime
123
than with the BRL, heavy phosphorus diffusion or for the control wafer without diffusion. All
wafers with the ONO surface passivation had a J0s ≤ 1 fA/cm2. Hence, the lifetimes reported
here can be considered as representative of the bulk lifetime. In the case of the n-type 100 Ω·cm
FZ wafers used for the IBC cells, boron diffusion without BRL degraded the lifetime from the
58 ms measured in the control wafer to 15 ms. In contrast, boron diffusion with BRL improved
the lifetime to 84 ms. No bulk degradation was observed for the boron diffusions with a BRL
(contrary to other reports [291, 292]), possibly due to differences in the deposition conditions.
1013 1014 1015 1016
0
10
20
30
40
50
60
70
No BRL BRL Phos Control10-1
100
101
102
Life
tim
e a
t ∆n
= 1
01
4 c
m-3
(m
s)
n-type FZ 100 Ω.cm
n-type CZ 1 Ω.cm
p-type FZ 1 Ω.cm(a)
No BRL
BRL
Total cell J0e
~10 fA/cm2
τbulk
~35ms
Eff
ective
Life
tim
e (
ms)
Excess Carrier Density (cm-3)
Batch 4
Batch 3
Fitting
Total cell J0e
~10 fA/cm2
τbulk
~63 ms
(b)
Fig 7.6: (a) Boron diffusion with and without a BRL and phosphorus diffusion gettering were compared for various samples with identical ONO surface passivations with J0s ≤1 fA/cm2. (b) Photoconductance measurements on the two of the best performing ONO IBC solar cell from batch 3 and batch 4 (details of batches in Section 7.3.2). The cell from batch 3 had no BRL gettering whereas the cell from batch 4 had BRL gettering. An implied Voc at 10 fA/cm2 was simulated to be >740 mV.
On a batch of IBC cells incorporating BRL gettering (batch 4, which will be discussed in
Section 7.3.2), very high bulk lifetimes were achieved at the end of the cell fabrication process.
The lifetimes as measured using a Sinton PCD system with the coil over an active cell area are
presented in Figure 7.6b, which demonstrates a τeff above 50 ms at excess carrier density (∆n)
approximately 1014 cm3. The average bulk lifetime measured across 6 completed cell wafers
before metallisation was ~46 ms. Such high bulk lifetimes were not observed in previous cell
fabrication batches. This strongly suggests that the BRL gettering in combination with heavy
phosphorus diffusion gettering layers, which were maintained throughout most of the high-
temperature fabrication processes, played a major role in maintaining and improving the bulk
lifetimes.
124
7.3.2 Surface passivation on IBC solar cell
The ONO dielectric stack provided improved passivation on the light phosphorus diffusion
rantex, as presented in Chapter 5. However, the fabricated IBC solar cells have boron diffusion
rear area coverage of 5–17%. Four batches of cells were fabricated to evaluate the performance
of the ONO surface passivation and ARC on the IBC solar cells.
The first and second batches of cells were passivated using a technique previously developed
at ANU for IBC solar cells where a front surface was passivated with a PECVD SiNx-SiOx
stack and the rear passivation thermal SiO2 and LPCVD Si3N4 stack [14]. The first batch had
no light phosphorus diffusion on either the front or rear surfaces. The second batch had a light
phosphorus diffusion only at the rear surface. The third batch had similar ONO passivation on
both the front and rear surfaces, with a SiNx refractive index of ~1.93. The fourth batch had
ONO passivation on both the front and rear; however, the front SiNx had a refractive index n632
of ~1.93 and the rear had a SiNx refractive index n632 of ~2.10. Positive charges largely come
from SiNx at low refractive indexes of 1.85–1.93, which may cause poor passivation on the
boron diffused region (Chapter 5). Therefore, the higher SiNx refractive index is utilised at the
rear to improve the passivation on the boron diffused region.
Experimental details
The first batch had a similar fabrication sequence as that shown in Figure 7.2; however, light
phosphorus diffusion (steps 5 and 14) and ONO (steps 15–17) were not implemented.
Texturing was performed with TMAH and IPA solution mixture. The front SiNx-SiOx and rear
SiO2-Si3N4 surface passivation stacks were generated as described in a previous publication
[14].
The fabrication of the second batch had a similar fabrication sequence as that shown in Figure
7.2, however, the rear had a full area heavy phosphorus diffusion, the front had a light
phosphorus diffusion (step 14) and the ONO was not implemented (steps 15–17). The rear
heavy phosphorus diffusion was etched back with a single-sided etching mask (between steps
12–13) while retaining the heavy diffusion dots. Texturing was performed with TMAH and
IPA solution mixture. The front SiNx-SiOx and rear SiO2-Si3N4 surface passivation stacks were
generated similarly to a previous publication [14].
125
The fabrication of the third and fourth batches had similar fabrication sequences as shown in
Figure 7.2. However, there are three differences between the two batches in the rear SiNx on
the ONO stack and the texturing surfactant that was used. The third batch used TMAH with
IPA for the texturing solution, a SiNx refractive index n632 of ~1.93 was used for the rear ONO
stack and no BRL gettering was performed. The fourth batch used TMAH with MonoTex
additives for the texturing solution, a SiNx refractive index n632 of ~2.10 for the rear ONO stack
and BRL gettering was performed.
None of the cells described in this section had corona charging, and differences in the cell
fabrication processes are summarised in Table 7.1.
Table 7.1: The different fabrication processes and cell designs from the baseline sequence given in Section 7.2
Batches Differences in the cell process and design
Batch 1 No light phosphorus diffusion on the front or rear surfaces of the cell
Front passivation and ARC: PECVD SiNx-SiOx
Rear passivation: Thermal SiO2 – LPCVD Si3N4
Batch 2 No light phosphorus diffusion on the front surface of the cell
Front passivation and ARC: PECVD SiNx-SiOx
Rear passivation: Thermal SiO2 - LPCVD Si3N4
Batch 3 Front and rear passivation ONO with SiNx n ~1.93
Batch 4 BRL gettering
Texturing solution using MonoTex and TMAH
Front ONO passivation with SiNx n ~1.93
Rear ONO passivation with SiNx n ~2.10
The fabricated cells measured with dark and light I-V were analysed and simulated with an
‘enhanced’ equivalent circuit to measure the non-ideal recombination. In an ideal solar cell, the
basic equivalent circuit consists of a diode, which represents the p-n junction, a current
generation component and series and shunt resistances. The basic equivalent circuit model of
a solar cell was modified to describe the non-ideal recombination using two diodes with an
occasional third diode and a resistor in series, which is defined as the resistance-limited
enhanced recombination [293].
126
Results and discussion
Test wafers were processed simultaneously for each cell batches. The area weighted J0 of the
cell’s diffusions and surfaces were calculated based on the J0 of test wafers and area coverage
summarised in Tables 7.2–7.5.
Table 7.2: Measured surface passivation for an IBC solar cell using test wafers from batch 1. Front surface with SiNx-SiOx and rear surface with SiO2-Si3N4. Cell wafer thicknesses of ~220 µm.
Region Passivation Coverage (%)
Sheet Resistivity (Ω/)
J0 (fA/cm2)
Area Weighted J0 (fA/cm2)
Boron Planar SiO2-Si3N4 Rear ~9.5 80 37.5 3.6
Heavy Phosphorus Planar
SiO2-Si3N4 Rear ~1.6 11 194 3.1
Undiffused Planar SiO2-Si3N4 Rear ~88.9 - 16.5 14.7
Undiffused Texture SiNx-SiOx Front 100 - 8.3 8.3
Table 7.3: Measured surface passivation for an IBC solar cell using test wafers from batch 2. Front surface with SiNx-SiOx and rear surface with SiO2-Si3N4. Cell wafer thicknesses of ~220 µm.
Region Passivation Coverage (%)
Sheet Resistivity (Ω/)
J0 (fA/cm2)
Area Weighted J0 (fA/cm2)
Boron Planar SiO2-Si3N4 Rear ~9.5 82 35.8 3.4
Heavy Phosphorus Planar
SiO2-Si3N4 Rear ~1.6 37 80 1.3
Light Phosphorus Planar
SiO2-Si3N4 Rear ~88.9 ~310 8.0 7.1
Undiffused Texture SiNx-SiOx Front 100 - 6.7 6.7
Table 7.4: Measured surface passivation for an IBC solar cell using test wafers from batch 3. Front and rear surfaces with ONO (n SiNx ~1.93). Cell wafer thicknesses of ~270 µm.
Region Passivation Coverage (%)
Sheet Resistivity (Ω/)
J0 (fA/cm2)
Area Weighted J0 (fA/cm2)
Boron Planar ONO Rear ~9.5 140 21 2.0
Heavy Phosphorus Planar
ONO Rear ~1.6 15 194 3.1
Light Phosphorus Planar
ONO Rear ~88.9 ~440 3.8 3.4
Light Phosphorus Texture
ONO Front 100 ~466 10 10*
*Measurement prior to corona charging
127
Table 7.5: Measured surface passivation for an IBC solar cell using test wafers from batch 4. Front surface with ONO (n SiNx ~1.93) and rear surface with ONO (n SiNx ~2.10). Cell wafer thicknesses of ~235 µm.
Region Passivation Coverage (%)
Sheet Resistivity (Ω/)
J0 (fA/cm2)
Area Weighted J0 (fA/cm2)
Boron Planar ONO Rear ~9.5 150 20 1.9
Heavy Phosphorus Planar
ONO Rear ~1.6 15 219 3.5
Light Phosphorus Planar
ONO Rear ~88.9 ~680 4.4 3.9
Light Phosphorus Texture
ONO Front 100 ~550 11.8 11.8*
*Measurement prior to corona charging
Differences in the diffusions and sheet resistivities make it difficult to have a fair comparison
between the J0 from all batches. Comparing the experimental data of the ONO presented in
Chapters 4 and 5 to SiO2-Si3N4, the ONO passivation performed better in most cases. No
experimental data for ONO surface passivation are available for comparison in the case of
heavily doped phosphorus diffusion with resistivities lower than 60 Ω/. However, the J0 for
both ONO and SiO2-Si3N4 stacks are thought to be similar as the quality of surface passivation
for such heavily diffused regions becomes less critical. The PECVD SiNx-SiOx on an
undiffused rantex surface had a much lower J0 compared to the lightly diffused phosphorus
texture surface with the ONO stack. Therefore, a large contribution to the improvement of J0
on ONO cell batches is considered to be due to the rear surface passivation.
The ONO stack has better passivation results on undiffused (Chapter 4) and light phosphorus
diffused surfaces compared with the SiO2-Si3N4 stack, which is probably due to the differences
in the hydrogen concentration of the PECVD SiNx and LPCVD Si3N4. The higher hydrogen
concentration commonly found in PECVD SiNx may have hydrogenated the Si-SiO2 interface
[294]. Moreover, a lower J0 with the ONO surface passivation was obtained with SiNx at a
higher refractive index of ~2.10 on a boron diffusion surface due to the lower positive charges
in the SiNx layer. The measured efficiency, Voc, Jsc, FF and shunt and series resistances for
batches 1 to 4 are plotted in Figure 7.7. The batches had efficiencies ranging between 22.8–
24.8%. It is observed from Figure 7.7a that the ONO with rear SiNx n ~1.93 had a higher
efficiency on average compared to the other batches. However, the highest cell efficiency was
found in batch with the ONO having an SiNx with n632 ~2.10.
128
Batch 1 uses the previous passivation scheme and has a Voc ranging between 708–716 mV. The
Jsc was measured to be much lower as compared to passivating both surface with the ONO
stack with an average of ~40.95 mA/cm2. The low Jsc was caused by incomplete texturing at
the front surface. Microscope imagery captured for one of the cells from batch 1 in Figure 7.8
shows incomplete texturing at the front surface with a high fraction of planar regions. This
coincides with the lower average Jsc observed for batch 1 as compared to both ONO batches.
The filtered image in Figure 7.8b was processed using ImageJ. The calculated white region in
the filtered image shows the planar regions covers ~12%. Simulation using OPAL2 show that
the ~12% planar region can lead to a JGen loss of 0.4–0.5 mA/cm2, assuming identical
enhancements to the path length. The large distribution for Voc can be explained by the non-
uniform surface passivation from the PECVD SiNx on the undiffused front surface. As
discussed in Section 6.3.1, the surface recombination is much more sensitive to the passivation
quality without a diffusion.
Fig 7.8: (a) Microscope image was taken with one of the cells from batch 1. The planarized region is presented as bright blue areas. (b) Processed images used to measure the planarised region were created using ImageJ.
The performance of cells in batch 2 are similar to those of batch 1. Batch 2 uses the previous
passivation scheme and has a large range for Voc from 698–716 mV, whereas Jsc had an average
of ~41.23 mA/cm2. The low Jsc is due to the high planar region (similar issue to batch 1). The
lower fill factor observed as compared to Batch 1 may be due to the low bulk lifetimes of 6–9
ms as measured from the photoconductance at the cell region. The bulk lifetime is thought to
have degraded after the high-temperature processing, as other similar wafers prior to multiple
high-temperature processing achieved bulk lifetimes that were on average ~30 ms.
(a) (b)
129
As previously stated, batch 3 had the highest average cell efficiency among all the batches,
however, batch 4 contained a single cell with the highest overall cell efficiency. Batch 3 had a
Voc range of 710–714 mV with an average Jsc of ~41.98 mA/cm2. Batch 4 had a higher Voc
range of 715–720 mV with an average Jsc of ~42.19 mA/cm2. Comparing both ONO batches
shows that batch 4 had both a higher Voc and Jsc compared to the cells in batch 3. This was
mainly due to the higher bulk lifetimes and thinner cell wafers for batch 4 as well as the
planarised region on the textured surface covering ~5% in batch 3. The average bulk lifetime
measured across the 6 wafers in batches 3 and 4 were 36 and 46 ms, respectively. The lower
efficiency of most cells in batch 4 was largely due to the poor fill factor with an average of
~78%. The low fill factor was due to non-ideal recombination, which is described later in this
section.
The series and shunt resistances given in Figures 7.7e-f were obtained using the dark-light I-V
method discussed in Chapter 2. Relatively similar series resistances were obtained from all four
batches using conventional metallisation of Al. However, the shunt resistances were much
lower for batch 4.
All four batches of cells were further analysed using the dark I-V measurements, which
provides the local ideality factor at Vmpp. The local ideality factor (m) is defined as the slope
of the ln(I)-V curve described in Eq 7.1. The different recombination types that contribute to
the m make it difficult to associate its value with a single specific recombination mechanism.
However, plotting an m-V curve allows the detection of small changes within the I-V curve to
indicate resistivity effects or non-ideal recombination within the operation of the cell. Batches
1, 2 and 3 had an ideal m of <1.4 at the maximum power point (Mpp). The cells in batch 4 had
a wide range of m from 1.7–3.0, which correlates to the lower fill factor observed within the
batch from Figure 7.7d.
K = 1nV Y (n((ln )\ (7.1)
The best performing cells within each batch were modelled using an equivalent circuit model
with either two diodes or resistance-limited enhanced recombination [293]. The recombination
ideality factors are normally associated with a specific recombination mechanism. The values
presented in Table 7.5 show the fit to the dark I-V curve for the best performing cell from each
batch.
130
Batch 1 Batch 2 Batch 3 Batch 4
695
700
705
710
715
720
725
(b)
VO
C (
mV
)
Batch 1 Batch 2 Batch 3 Batch 440.4
40.8
41.2
41.6
42.0
42.4
42.8
43.2
JS
C (
mA
/cm
2)
(c) (d)
(a)
(e) (f)
Batch 1 Batch 2 Batch 3 Batch 474
76
78
80
82
84
FF
(%)
Batch 1 Batch 2 Batch 3 Batch 4
23
24
25E
ffic
ien
cy (
%)
Batch 1 Batch 2 Batch 3 Batch 4
103
104
105
106
107
Sh
unt
Resis
tan
ce
(Ω
.cm
2)
Batch 1 Batch 2 Batch 3 Batch 4
0.20
0.24
0.28
0.32
0.36
0.40
Se
ries R
esis
tan
ce
(Ω
.cm
2)
Fig 7.7: The performance of four batches of IBC solar cells. Batch 1 used a previous passivation scheme of rear SiO2-Si3N4 and front SiNx-SiOx [14]. Batch 2 had a similar passivation scheme as batch 1 with rear phosphorus diffusion. Batch 3 had an ONO cell with a SiNx n ~1.93 and is passivated both at the front and rear surfaces of the cell. Batch 4 had an ONO cell with SiNx n ~1.93 on the front and n ~2.10 at the rear. The (a) open circuit voltage, (b) short circuit current, (c) fill factor, (d) efficiency, (e) shunt resistance and (f) series resistance were measured at 25 ± 1 ˚C using a combination of dark and light I-V curves.
Front SiNx-SiOx
Rear SiO2-Si3N4
Front Rear ONO
131
There are a few other reasons the cells may exhibit non-ideal recombination and low fill factors,
including pin holes in the ONO dielectric stack, metal spiking through the p-n junction,
metallisation on the diffusion overlap region, a contiguous boron and phosphorus region,
change in injection dependence of wafer surface, etc. [189, 293, 295]. Depending on the type
of recombination, the equivalent circuit with a second diode associated with either the SRH or
Auger recombination at high injection levels exhibited m2 values within the range of 1–2 [293,
295].
No clear conclusions from Table 7.5 could be drawn on which specific loss mechanism may
be involved in the non-ideal recombination and low fill factors, as this would require a more
detailed experimental design. Three changes to the cell fabrication process may overcome the
non-ideal recombination and improve the fill factor and m, which are discussed in the following
sections. The ONO IBC solar cell has a very light and shallow boron diffusion of ~150 Ω/. A
simulation performed by Edler et al. showed that increasing the depth of metal spiking through
the p-n junction drastically increases the metal recombination [296]. Moreover, metallisation
with Al is known to form an alloy at temperatures from 200˚C to the eutectic point of 577 ˚C
[297]. The annealing of Al onto silicon may cause its dissolution and create voids within the
crystal to allow Al to precipitate and form Al spikes into the silicon bulk. Therefore, having a
heavier and deeper boron diffusion junction depth may prevent metal spiking through the p-n
junction. This may additionally reduce the metal recombination by providing a ‘field-effect’
on the minority carriers that reach the metal contacts [293, 295, 296].
0 200 400 600 80010-8
10-6
10-4
10-2
100
102
104
Batch 1 Batch 2 Batch 3 Batch 4
0.5
1.0
1.5
2.0
2.5
3.0
3.5
(a)
Idealit
y F
acto
r (m
)
Batch 1 Mpp
~620 mV
Batch 2 Mpp
~618 mV
Batch 3 Mpp
~624 mV
Batch 4 Mpp
~628 mV
Mpp
Batch 1
Batch 2
Batch 3
Batch 4
Simulation
Curr
ent
Density (
mA
/cm
2)
Voltage (mV)
(b)
Fig 7.9: The measured (a) local ideality factor and (b) dark I-V curve obtained from the best performing cells within the three batches without any corona charging.
Front SiNx-SiOx
Rear SiO2-Si3N4
Front Rear ONO
132
Table 7.5: Parameters used to fit the dark I-V curve with the two diode model and resistance-limited enhanced recombination [293]
The adjacent boron-doped dots and light phosphorus BSF region can lead to tunnelling
recombination, which causes current leakage and a non-ideality factor [298, 299]. Isolating the
diffusions with additional photolithography steps may eliminate such recombinations. In
addition, metallisation with different metal doped silicon approaches or stacks may prevent
spiking, such as Al doped silicon or TiN as diffusion barriers [300].
7.3.3 Positive corona charging on the front surface of ONO IBC solar cells
Positive corona charging reduces the surface recombination on undiffused and light phosphorus
rantex surfaces, as presented in Chapters 4 and 5. This implementation can potentially increase
the efficiency of ONO IBC solar cells. In this section, ONO IBC solar cells were measured
before and after positive corona charging on the front surfaces and were further annealed to
render the charge stable.
Experimental details
Two fabricated ONO IBC solar cells were positively corona charged at the front rantex surface
for 100 seconds at 5 kV. The corona charged cells were subsequently annealed at either 250 ˚C
Conditions Batch 1 Batch 2 Batch 3 Batch 4
Saturation Current J0 32 fA/cm2 32 fA/cm2 42 fA/cm2 35 fA/cm2
Ideality factor m2 2 2 - -
Saturation Current J02 5.7 nA/cm2 8.4 nA/cm2 - -
Ideality factor mH - - 1.38 1.55
Saturation Current J0H - - 1000 pA/cm2 4300 pA/cm2
Resistance H - - 1000 Ω.cm2 180 Ω.cm2
Dark I-V Shunt Resistance 55 kΩ.cm2 19 kΩ.cm2 50 MΩ.cm2 9.0 kΩ.cm2
Dark I-V Series Resistance 0.06 Ω.cm2 0.1 Ω.cm2 0.1 Ω.cm2 0.1 Ω.cm2
Local Ideality Factor at Vmpp 1.20 1.20 1.32 1.76
R2 0.9982 0.9994 0.9986 0.9973
133
or 400 ˚C with forming gas for ten minutes to embed the charges. Dark and light I-V
measurements were performed on the cells before and after the corona charge and FGA.
Results and discussion
Sintering ONO IBC solar cells at 400 ˚C - The dark and light I-V measurement of the first
ONO IBC cell before and after corona charging are provided in Table 7.6. Corona charging on
the front surface of the IBC cell improved the efficiency from 23.6 to 24.2%. The increased
efficiency was mainly due to the improvement in the Voc from 720 mV to 723 mV, and fill
factor from 78.2 to 79.6%. The dark I-V measurement performed on the cell in Figure 7.10a
reveal that the improvements occurred mostly at lower voltages after corona charging due to
the accumulation of majority carriers on the front surface. This is similarly reflected with the
corona charged ONO high resistivity rantex wafers with improvement to the lifetime, which
were much more significant at lower injection levels, as described in Section 4.5. However,
further annealing at 400 ˚C in ambient forming gas, unfortunately, degraded the cell. The dark
I-V measurements revealed a much higher shunt resistance after annealing. However, the
efficiency of the cell drastically decreased, with both the Voc and the fill factor, which declined
to 683 mV and 74%, respectively. The increased shunt resistance indicates that the
improvements are observed at a lower ∆n injection level. Nevertheless, the drop in efficiency
is due to an increase in the non-ideal recombination that occurs at higher voltages, higher J0,
and higher series resistances, as presented in Table 7.6.
0 100 200 300 400 500 600 700 800
10-4
10-3
10-2
10-1
100
101
102
103
0 100 200 300 400 500 600 700 800
0
2
4
6
8
10
12
14
Curr
ent
(mA
/cm
2)
Voltage (mV)
Mpp
Before CC
After CC
After CC & Annealing
Simulation
(a) (b)
Local Id
ea
lity F
acto
r
Voltage (mV)
Fig 7.10: The measured (a) dark I-V and (b) local ideality factor for the ONO IBC solar cell before and after corona charging and annealing at 400 ˚C in FGA for ten minutes.
134
Table 7.6: Dark and light I-V measurements before and after corona charging, and with further annealing at 400 ˚C to embed charges into the ONO IBC solar cell.
Sintering ONO IBC solar cells at 250 ˚C - The dark and light I-V measurement results for
the second ONO IBC cell before and after corona charging are provided in Table 7.7. The
efficiency after corona charging for the second cell increased from 24.3% to 24.5%. The
improvement was mainly due to an increased Voc from 711 to 714 mV and a fill factor that
improved from 81.5% to 81.9%. Unfortunately, dark I-V measurements were not recorded after
corona charging.
Instead of annealing at 400 ˚C, the cell was subsequently annealed at 250 ˚C for ten minutes.
The additional low-temperature annealing did not degrade the Voc with an extracted dark J0 of
35 fA/cm2. Moreover, the cell efficiency improved further and increased to 24.7% due to the
higher shunt resistance, higher fill factor and lower series resistance, as shown in Table 7.7 and
Figure 7.11. This suggests that the lower annealing temperature of 250 ˚C is suitable for our
cell design without causing additional increases in the non-ideal recombination at the Mpp. It is
noted that the non-ideal recombination, which was once hidden for lower shunt resistances,
was revealed after corona charging and annealing.
Dark I-V Conditions Before corona After corona After corona and annealing
Saturation current J0 26 fA/cm2 24 fA/cm2 86 fA/cm2
Ideality factor m2 2.0 2.0 2.0
Saturation current J02 6.22 nA/cm2 6.77 nA/cm2 36 nA/cm2
Ideality factor mH - - 1.8
Saturation current J0H - - 82 nA/cm2
Resistance H - - 180 Ω.cm2
Shunt resistance 1 kΩ.cm2 3.5 kΩ.cm2 7 kΩ.cm2
Series resistance 0.3 Ω.cm2 0.3 Ω.cm2 0.35 Ω.cm2
Local ideality Factor at Mpp 1.97 1.82 2.17
R2 0.9992 0.9965 0.9997
Light I-V Conditions
Voc 720.4 mV 723.4 mV 683.34 mV
Jsc 41.95 mA/cm2 42.05 mA/cm2 41.78 mV
FF 78.15% 79.55% 73.86%
Eff 23.6% 24.2% 21.1%
Light and Dark Rs 0.415 0.396 0.603
135
0 100 200 300 400 500 600 700 800
10-6
10-5
10-4
10-3
10-2
10-1
100
101
102
103
0 100 200 300 400 500 600 700 800
0
2
4
6
8
10
12
14C
urr
ent
(mA
/cm
2)
Voltage (mV)
Mpp
Before CC
After CC & Annealing
Simulation
(a) (b)
Local Id
ea
lity F
acto
r
Voltage (mV)
Fig 7.11: The measured (a) dark I-V and (b) local ideality factor of the ONO IBC solar cell before and after corona charging with an additional anneal at 250 ˚C in FGA for ten minutes.
Table 7.7: Dark and light I-V measurement before and after corona charging and with further annealing at 250 ˚C to embed charges into the ONO IBC solar cell.
Dark I-V Conditions Before corona After corona After corona and annealing
Saturation current J0 38 fA/cm2 - 35 fA/cm2
Ideality factor m2 2.0 - 2.0
Saturation current J02 6.55 nA/cm2 - 6 nA/cm2
Ideality factor mH - - 1.4
Saturation current J0H - - 1.6 nA/cm2
Resistance H - - 1500 Ω.cm2
Shunt resistance 2 kΩ.cm2 - 0.4 MΩ.cm2
Series resistance 0.08 Ω.cm2 - 0.05 Ω.cm2
Local ideality factor at Mpp 1.27 - 1.14
R2 0.9992 - 0.9941
Light I-V Conditions
Voc 711.47 mV 713.62 mV 714.77 mV
Jsc 42.0 mA/cm2 42.0 mA/cm2 42.0 mA/cm2
FF 81.46% 81.88% 82.10%
Eff 24.34% 24.54% 24.65%
Light and Dark Rs 0.231 - 0.189
136
Initial CC FGA 250 °C21
22
24
25
Initial CC FGA 250 °C40
41
42
Initial FGA 250 °C Initial FGA 250 °C0.8
0.9
1.0
1.1
1.2
1.3
2.0
2.1
2.2
21
22
24
25E
ffic
iency (
%)
Initial CC FGA 250 °C 708
710
712
714
716
(d)
(a)
Voc (
mV
)
(b)
40
41
42
Jsc (
mA
/cm
2)
Initial CC FGA 250 °C 73
77
78
79
80
81
82
83(c)
FF
(%
)
0.0
0.2
0.4
0.6
0.8
1.0
1.6
1.8
2.0(e) (f)
Fig 7.12: ONO IBC solar cells were measured before and after positive corona charging with further annealing in forming gas at 250 ˚C. The (a) efficiency, (b) open circuit voltage, (c) short circuit current, (d) fill factor, (e) series resistance and (f) local ideality factor were measured at 24 ± 1 ˚C.
137
A batch of cells was fabricated, corona charged and annealed at 250 ˚C. The measured
efficiency, Voc, fill factor and series and shunt resistances are plotted in Figure 7.12. All I-V
curves in this batch had their Jsc corrected due to fluctuations in the light intensity from an
outdated halogen light source. The Jsc for a calibrated reference cell was simultaneously
monitored during the IBC solar cell measurements. However, even after correction, there is
still uncertainty within the corrected Jsc due to the poor light uniformity across the measurement
area. The voltages for all cells improved after the corona charging and further annealing.
However, the efficiency only improved for some of the cells. The improvements in the fill
factors for cells 38A, 38B, 38C and 38D were observed due to the lower series resistance and
increased Voc. The degradations for cells 38E and 38F were due to sudden increases in the
series resistance (from ~0.2 to 0.8–1.0 Ω.cm2), as caused by the metallised fingers on the cells
peeling off after the subsequent annealing in the forming gas. The poor metal and dielectric
adhesions were postulated to be due to residue from the acetone rinses before the metal
evaporation.
138
7.3.4 Lift-off metallisation on ONO IBC solar cells
The formation of Al contacts on a cell have occasionally been imperfect, which causes the cell
to suffer from a high contact resistivity, low fill factor and reduced efficiency. The lift-off
metallisation was developed to lower the contact resistivity during cell processing and reduce
the potential for metal spiking by using different metallisation stacks [301].
The second metallisation method involved a lift-off process and is as shown in Figure 7.13b.
The potential advantage of the lift-off process is the avoidance of both native oxide growth and
organic contaminants between the evaporated metal and silicon dot contacts. Conventional
metal evaporation has metal contact dots that are exposed to acetone and photoresist prior to
metal evaporation. The ‘lift-off’ process avoids such exposures and the metal evaporation can
proceed immediately after the BHF. However, for the lift-off process to be successful, the
outermost layer of the metal stack deposited prior to the photoresist lift-off must either be stable
at room temperature (non-oxidising) or must form a low resistivity conductive oxide.
A thin metal stack is evaporated onto the open metal dot contacts with the patterned photoresist
that adheres to the dielectric layer. The wafers were then submerged in an ultrasonic bath to
remove the evaporated metal together with underlying photoresist while retaining the metal
deposited on the silicon wafers. Subsequently, Al was evaporated over the entire surface,
stacking onto and connecting the individual metal dots.
In this section, the transfer length measurement (TLM) structures were fabricated on boron
diffused wafers to measure the different contact resistivities with various metallisation stacks.
In addition, dark and light I-V measurements were performed on the IBC solar cells with a
selection of metallisation stacks developed using these lift-off process and were compared to
conventional metallisation.
Experimental details
To fabricate the TLM structures, high resistivity 100 Ω.cm n-type silicon wafers were boron
diffused at 910 ˚C for 40 minutes to achieve a sheet resistivity of ~210 Ω/. The BSG was then
removed and the wafer was oxidised at 1000 ˚C and annealed in N2 for 45 minutes.
Photolithography was used to define the TLM patterns for the lift-off metallisation. Seven
metal stacks, which include chromium-palladium-silver (CrPdAg), aluminium-silver-
aluminium (AlAgAl), aluminium-palladium-aluminium (AlPdAl), palladium-aluminium
139
(PdAl), aluminium-palladium (AlPd), silver-aluminium (AgAl) and chromium-aluminium
(CrAl) were selected for metal evaporation. The metallisation was performed as described in
Section 7.2.8 with a boat/rod power supplied at 550–800 W onto the patterned photoresist. The
total thickness of each stack on the TLM pads were ~165 nm. The metal evaporated onto the
exposed silicon and AZ4562 photoresist was subjected to an ultrasonic bath in acetone to lift-
off the undesired metallised area. Two TLM pads were fabricated for each metal stack. The
TLM structures were cut with a dicing saw, sintered in forming gas at 250 ˚C for 20 minutes
and measured with a Keithly source meter ranging from -0.3 to 0.3 V.
Two batches of cells were also fabricated using lift-off metallisation of chromium-palladium-
silver-aluminium (CrPdAg-Al) and aluminium-palladium-aluminium (AlPd-Al). The selected
metallisation stack for the cells were based on low contact resistivity for AlPd-Al and
frequently used metallisation stack at the ANU with CrPdAg. The cell fabrication process is
similar to the baseline; however, both metal stacks were performed using lift-off metallisation.
For example, the CrPdAg-Al stack used a Cr rod that was loaded onto the first boat followed
by Pd and Ag pellets into the second and third tungsten boats, respectively. The metal purity
selected was in the range of 3–5N. The wafers were placed one metre above the metal source
to avoiding unnecessary heating from the evaporation. As the chamber was pumped down to
7.5 × 10-5 Torr, a supplied power of 600–800W was applied across the metal boat/rod. An
initial pre-melt of the metal was performed with the shutter closed. After the metal on the boat
melted over a defined period, the shutters were opened with a deposition rate of ~6 Å/sec. This
was similarly performed for the other two metals, Pd and Ag. The chamber was vented in N2
gas after reaching the targeted thicknesses of Cr ~15 nm, Pd ~15 nm and Ag ~40 nm.
The wafers for the first stack of metal evaporation (CrPdAg) with the thin AZ1518 photoresist
were submerged in acetone and subjected to an ultrasonic bath for 10–15 minutes. After
visually inspecting that all of the photoresist was removed, the wafers were rinsed with DI H2O
and fresh acetone once more. The wafers were spin rinsed, dried and loaded into the chamber
for the thermal evaporation of ~3 µm of Al as previously described.
For both metallisation methods, the photoresist was then spun onto the front and rear of the
wafers for metal separation after the evaporation of the blanket Al layer. After exposing the
gaps between the p and n fingers, the wafers were submerged into an Al etch solution, which
consisted of H3PO4, H2O and HNO3 with a volume ratio of 20:4:1 at 40–50 ˚C. The separation
140
of the metal was checked using a microscope and PL imaging to ensure the cells were not
shunted by fine metal bridges that connected the p and n fingers.
Similarly, for AlPd-Al, lift-off metallisation was performed on the AlPd stack followed by a
full blanket Al metal evaporation. The evaporation of the Al and Pd stack had thicknesses of
~50 nm and ~20 nm, respectively, followed by the final Al evaporation of ~3 µm. The I-V
measurement for both the lift-off metallisation cell results was compared to cells from batch 4.
Fig 7.13: Metallisation process for the ONO IBC solar cell: (a) conventional and (b) lift-off process
(a) Conventional process (b) Lift-off process
ONO Dielectric Stack
Photoresist
Lift-Off Metal
Aluminium
Silicon
Photoresist
Develop
RIE - BHF
141
Results and discussion
The average contact resistivity from TLM structures prepared using the lift-off processes is
plotted in Figure 7.14a. The TLM measurements obtained with AlPdAl showed the lowest
contact resistivity of 1.55 × 10-6 Ω.cm2, whereas the Al and CrPdAg contact resistivity were
measured to be 1.24 × 10-4 Ω.cm2 and 9.4 × 10-5 Ω.cm2, respectively. The electrochemical
capacitance-voltage (ECV) measurements performed on the boron diffused wafers had a
surface concentration of ~9 × 1018 cm-3 with sheet resistivity of 210 Ω/. The measured contact
resistivities for all the metal stacks were considerably lower as compared to the Al with the lift-
off processing.
50 100 150 200 250 30010
-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
0 100 200 300 400 500
0
5
10
15
20
Al (Franklin et al.)
Cr-Pd-Ag
Pd-Al
Al-Pd-Al
Al-Ag-Al
Cr-Al
Al
Al-Pd
Al-Ag
Co
nta
ct
Re
sis
tivity (
Ω.c
m2)
Sheet Resistivity (Ω/sq)
(a)
y = 0.0371x + 0.083
R2 = 0.9999
Rsheet ~223 Ω/
(b)
y = 0.0369x + 0.511
R2 = 0.9999
Rsheet ~215 Ω/
Al
Al-Pd-Al
Cr-Pd-Ag
Resis
tan
ce
(Ω
)
TLM spacing (µm)
y = 0.0359x + 0.517
R2 = 0.9999
Rsheet ~215 Ω/
Fig 7.14: (a) The measured contact resistivity for various metal stacks on light boron diffusion. The metallisation was performed with lift-off except for the Al performed by Franklin et al. [14]. (b) The TLM measurement for the Al, AlPdAl and CrPdAg structures.
Photoconductance measurements and PL imaging were performed on a cell after the lift-off
metallisation for CrPdAg. Photoconductance measurements on the cell showed an increased J0
of ~5 fA/cm2 whereas the PL imaging measured a lifetime drop of ~1.6 ms at 3 × 1015 cm-3
across the cell region.
The cell efficiencies, Voc, Jsc and fill factors for both the lift-off metallisations were plotted
together with conventional Al evaporation in Figure 7.15. Metallisation with AlPd-Al has the
lowest average efficiency of ~22.14% among the three batches, whereas Al and CrPdAg-Al
had average efficiencies of ~23.6% and ~23.7%, respectively. All three batches of cells were
measured to have relatively similar Voc and Jsc. Moreover, the photoconductance measurements
142
performed on these cells before metallisation had a J0 of 7–10 fA/cm2. The comparatively
similar Voc observed across the batches suggests that the metal contact recombination for all
three metallisations are too small to cause any differences. The similar Jsc observed across the
batches could be justified with the relatively small difference in the overall rear reflectivity, as
the back reflector of the cell consists mostly of Al of ~99.65% and the metal stack of only
~0.35%.
A much lower fill factor of the AlPd-Al cells was observed as compared to the CrPdAg-Al and
Al cells. Unfortunately, the lower fill factor is due to a higher series resistance that ranged from
0.6–2.3 Ω.cm2. Moreover, the AlPd-Al cells have large variations in their shunt resistances.
The contributions of both the low shunt and high series resistances were the main cause for the
low fill factor, causing the low efficiency of the cells. There are a few plausible reasons for the
high series resistances caused by the AlPd-Al stack. Firstly, the evaporation of palladium had
a much slower deposition rate compared to the TLM test structures. The TLM test structures
had palladium evaporation recorded at ~6 Å/sec as compared to the cells with deposition rates
recorded at ~2 Å/sec just after the shutter was opened. The low evaporation rate suggests that
the Pd in the boat may not have pre-melted fully and that other contaminates with similar and
lower melting points as Pd may have been deposited onto the sample as well [254]. Secondly,
contamination of the metal contacts between the AlPd and Al after the lift-off processes could
be another plausible cause for the high contact resistivities. The measured metallised stacks on
the TLM structure were performed with a single run without breaking the chamber vacuum.
However, the cell structure for the lift-off metallisation required a total of two metal depositions,
exposing the metal to air and wet chemicals before evaporating the final Al layer. Moreover,
photoresist and acetone residue may have resided on the AlPd metal dots during the lift-off
process, which could contribute to increased contact resistance. Of the three metals used for
the cell fabrication process, the baseline metallisation process with Al remains the best method
to make good contact with silicon.
The cells metallised with CrPdAg-Al had a slightly higher series resistance of 0.34–0.60 Ω.cm2
compared to the cells with Al metallisation. Due to the number of cells fabricated for CrPdAg-
Al, it is inconclusive but plausible that CrPdAg-Al may prevent spiking through the p-n
junction due to the observed higher shunt resistance compared to the Al and AlPd-Al
metallisation stack in Figure 7.15e. However, the conventional metallisation process with Al
achieves lower contact resistivities as compared to the fabricated metallisation stacks.
143
AlPd-Al Al CrPdAg-Al710
715
720
725
VO
C (
mV
)
(b)
AlPd-Al Al CrPdAg-Al40
41
42
43(c)
JS
C (
mA
/cm
2)
AlPd-Al Al CrPdAg-Al66
68
70
72
74
76
78
80
82(d)
FF
(%)
AlPd-Al Al CrPdAg-Al
19
20
21
22
23
24
25(a)
Eff
icie
ncy (
%)
AlPd-Al Al CrPdAg-Al
103
104
Sh
un
t R
esis
tan
ce
(Ω
.cm
2)
(e)
AlPd-Al Al CrPdAg-Al0.0
0.5
1.0
1.5
2.0
2.5(f)
Se
rie
s R
esis
tan
ce
(Ω
.cm
2)
Fig 7.15: Three batches of ONO IBC solar cells were created that are identical except for the rear metallisation on the diffusion region. The cells have metallisation stacks of aluminium-palladium-aluminium (AlPd-Al), aluminium (Al) and chromium-palladium-silver-aluminium (CrPdAg-Al). The (a) Voc, (b) Jsc, (c) fill factor and (d) efficiency were measured at 25 ± 1 ˚C. The box represents the range of data between 25 – 75% with the line showing the mean, and the whiskers represent the maximum and minimum values obtained.
144
7.4 ONO IBC cell with certified conversion efficiency of 25%
The best performing ONO IBC solar cell was achieved using the batch 4 cell fabrication
process (Section 7.3.2) and the conventional Al metallisation. The champion cell fabricated at
ANU as part of this work was independently certified at the Commonwealth Scientific and
Research Organisation (CSIRO) in Newcastle using our custom designed measurement jig and
an aperture mask.
Fig 7.18: (a) Rear image of champion ONO IBC solar cell (b) Calibrated lifetime image of ONO IBC solar cell measured at carrier injection ∆n of ~2.5 × 1015 cm-3 before metallisation.
Prior to corona charging, in house measurements from batch 4 reached an efficiency of 24.8%.
However, the similar cell measured at CSIRO achieved a certified efficiency of 25.0 ± 0.6%
(report no: A0014-ANU-D02_001). The certified cell attained a Voc of 716 ± 11 mV, fill factor
of 81.0 ± 1.9% and Jsc of 43.0 ± 0.78 mA/cm2, by considering the spectral mismatch of the
current as defined under a solar spectral irradiance at AM1.5G and an aperture mask area of ~4
cm2 [302]. The discrepancy in cell efficiency measured at ANU and CSIRO was largely due to
the underestimation in Jsc.
Due to the annealing limitations at CSIRO, the cell was only corona charged on the front rantex
surface without further annealing. The cell efficiency was measured as having a similar value
of 24.95 ± 0.61% after corona charging, as indicated by the I-V curve plotted in Figure 7.17a.
Although the cell had a slight increase in the Voc of 717 ± 11 mV and fill factor of 81.1 ± 1.9%,
the measured Jsc was slightly lower at 42.9 ± 0.75 mA/cm2. Figure 7.17b shows the normalised
reflectance and external and internal quantum efficiency curves of the ONO IBC solar cell. The
(a) (b)
145
measured reflectance and external quantum efficiency (EQE) show an excellent internal
quantum efficiency (IQE) with an average of 99.1% across the 600–900 nm wavelength range.
0 200 400 600 800
0
10
20
30
40
(a)
Curr
ent
(mA
/cm
2)
Voltage (mV)
Cell aperture area: 3.99 ± 0.02 cm2
JSC
: 42.9 ± 0.75 mA/cm2
VOC
: 717 ± 1.1 mV
FF: 81.1 ± 1.9 %
η: 25.0 ± 0.6 %0.0
0.5
1.0
1.5
2.0
Spectr
al in
t. (
W/m
2/n
m)
AM 1.5 G
400 600 800 10000.0
0.2
0.4
0.6
0.8
1.0(b)
Measured ONO
Simulated ONO
ONO EQE
ONO IQE
Wavelength (nm)
Reflecta
nce, E
QE
, IQ
E
Fig 7.17: Measurements of the (a) I-V curve and (b) reflectance, EQE, and IQE of the champion ONO IBC solar cell after corona charging. The independent measurements were performed at CSIRO in Newcastle.
Simulations were performed using Quokka3, OPAL2 and SunSolve on the champion cell
before corona charging to quantify the primary loss mechanism by utilising the free energy loss
analysis (FELA). The thicknesses of the ONO simulated in the SunSolve ray tracing and
OPAL2 packages show the thermal SiO2, SiNx and SiOx were approximately 17, 53 and 100
nm, respectively. A similar cell structure was simulated using SunSolve with an ONO stack on
both front and rear surfaces, a rear Al of 1000 nm and a Lambertian scattering fraction of 0.63
to achieve a Jsc of ~43.0 mA/cm2. The generation profile simulated using SunSolve was loaded
into Quokka3 together with the J0 recombination as measured from test structures (shown in
Table 7.5 - metallisation recombination J0 of 5 fA/cm2 as discussed in section 7.3.4) and series
and shunt resistances of 0.21 Ω.cm2 and 9000 Ω.cm2, respectively.
The simulated “25.0% cell” modelled before corona charging had a Voc, Jsc, fill factor and
efficiency of 719 mV, 42.98 mA/cm2, 81.38% and 25.17%, respectively, which is well within
the measurement errors. The loss analysis breakdown of the champion cell is shown in Figure
7.18.
146
25.17
0.41
0.140.19
0.69
0.20
0.78
23.5
24.0
24.5
25.0
25.5
26.0
26.5
27.0
27.5
28.0
28.5C
ell
Effic
ien
cy a
nd
Effic
ien
cy L
osse
s (
%)
Resistive loss - Internal, 0.78%
Resistive loss - Contacts, 0.045%
Resistive loss - Fingers, 0.11%
Resistive loss - Shunt, 0.04%
Recombination - Contacts, 0.20%
Recombination - Bulk, 0.09%
Recombination - Front pass. light phos diff, 0.69%
Recombination - Rear pass. light phos diff, 0.19%
Recombination - Rear pass. heavy phos, 0.14%
Recombination - Rear pass. boron diff, 0.04%
Perimeter/edge losses, 0.41%
Modelled Cell Efficiency, 25.17%
Fig 7.18: Modelled cell efficiency and breakdown of losses for the champion cell. Modelling was performed using Sunsolve and Quokka3 to simulate the free energy loss analysis method.
Excluding the optical losses, adding the modelled losses in Figure 7.18 yields an efficiency of
27.8% for the 230 µm thick 100 Ω.cm n-type cell. The resistive losses accounted for
approximately 0.98%, which is mostly dominated by the bulk resistance. Recombination within
the cell accounted for approximately 1.35%, where a large portion was due to the front surface
passivation and the rear heavy phosphorus diffusion dots. The simulated edge recombination
contributed to approximately 0.41% of loss in the efficiency. The cell performance has the
potential to further improve by reducing the recombination on the front rantex surface.
Simulation of champion IBC solar cell structure with ONO stack rantex surface J0 of ~4 fA/cm2
(attainable J0 value as presented in Chapter 5) without non-ideal recombination shows
simulated efficiency of 25.6% is achievable.
147
7.5 Chapter Summary
High-efficiency IBC solar cells were achieved by introducing numerous improvements over
previous cell fabrication processes.
High bulk lifetimes for the cells was maintained by having a heavy phosphorus diffusion layer
at the front surface and BRL gettering. The gettering steps were simplified as the process was
implemented during the formation of the p-n junction and diffusion for the contact dots without
requiring additional processing steps.
The ONO surface passivation has been demonstrated to provide excellent passivation on both
the boron and phosphorus diffusion regions. However, having a higher SiNx refractive index
layer of 1.93 to 2.10, as achieved in batches 3 and 4, did not provide a significant improvement
in the boron diffused surface passivation.
Corona charging at the front surface improved cell efficiency. However, annealing the cells at
400 ˚C to trap the charges decreased the cell performance due to an increase of the non-ideal
recombination. A lower annealing temperature of 250 ˚C could trap the charges into the ONO
stack while preventing non-ideal recombination.
Lift-off metallisation did not achieve a lower contact resistivity on the fabricated IBC solar
cells as compared with conventional metallisation using Al. However, the lift-off process has
the potential to achieve consistently low contact resistivities. A much more rigorous experiment
should be conducted to evaluate the potential of such a process.
By incorporating all the processing improvements, an independently measured efficiency of
25.0% was achieved on a ~4 cm2 aperture mask with a custom-designed measurement jig.
Direct metal contact to the silicon absorber and front surface recombination remains one of the
major recombination centres to the cell design. Further reducing the front rantex surface
passivation to J0 of ~4 fA/cm2 and without non-ideal recombination can further increase the
cell efficiency to 25.6%.
148
Chapter 8
This thesis investigated the application and optimisation of ONO dielectric stacks onto IBC
solar cells at one-sun illumination. The focus was on improving the fabrication process to
develop high-efficiency IBC solar cells in conjunction with the optimised ONO dielectric
stacks. The specific conclusions for each chapter from this thesis are summarised below.
In Chapter 2, various types of surface passivation commonly used in silicon solar cells were
reviewed. Thermal SiO2, PECVD SiNx and ALD Al2O3 surface passivation dielectrics were
evaluated and compared to the optimised respective surface passivations achieved at ANU.
Chapter 3 presents the different measurements employed to quantify the quality of the surface
passivation, dielectric charge and the performance of the solar cell. The measured effective
lifetime and J0 on undiffused and diffused wafers were detected primarily using
photoconductance measurements. The effective charges were determined using C-V
measurements with a MOS structure. Stringent light I-V measurements were performed on
solar cells to accurately measure the performance and the extraction of the series resistance,
which were measured and compared to the light and dark I-V measurements.
In Chapter 4, the conditions presented on each dielectric layer of the ONO stack were assessed.
The main conclusions were as follows:
- Thermal SiO2 provides chemical passivation, SiNx hydrogenates the Si-SiO2 interface
and induces a field-effect with positive charges and the SiOx traps corona charges and
improves the overall stack for the ARC.
- An ONO stack with a thermal SiO2 thickness greater than 7 nm without POA provided
excellent surface passivation on undiffused planar n-type wafers.
- The SiNx deposition temperature and SiH4:NH3 gas ratio were identified as the most
sensitive parameters for surface passivation.
- Corona charging of the ONO stack reduces the surface recombination substantially for
planar 111 and rantex surfaces as compared to planar 100 surfaces.
- Further annealing of positive corona charges at 400 ˚C into the ONO stack traps the
charges and renders it stable over a two-year period.
Conclusion
149
- High record lifetimes on various n-type wafers were achieved, which surpassed those
of recent parameterisation Auger lifetimes [17].
In Chapter 5, the conditions for each dielectric layer of the ONO stack for phosphorus and
boron diffused surfaces were investigated. The main conclusions were as follows:
- The ONO stack on the light phosphorus diffused wafers showed excellent surface
passivation without the need for POA. The phosphorus diffused rantex wafers required
an overall thicker thermal SiO2 compared to the planar wafers were likely due to the
concave and convex corners on its surface.
- The ONO stack on the boron diffused wafers improved with an increased POA of N2
due to the reduced positive charges within the SiO2 after annealing, lower surface
concentration and deeper diffusion profile with a prolong POA N2 drive-in. An
increased thermal SiO2 thickness improved the surface passivation due to a lower Auger
recombination within the diffusion and the charge centroid of the SiNx being further
from the surface.
- ONO passivation improved on the boron diffused surface with higher refractive indexes
n632 from 1.94–2.10 and the lower positive charges measured within the SiNx.
- Corona charging can both improve and damage the Si-SiO2 interface. The deposition
of corona charging improved with the field-effect passivation; however, ion
bombardment of charges may cause dangling bonds towards the interface.
In Chapter 6, the three common losses in a solar cell were studied, including optical,
recombination and resistance losses. Simulations were performed using Quokka3 to review the
efficiency, Voc, Jsc and fill factor. Numerous design improvements were made over the 24.4%
IBC cell design based on the findings from the simulation and modelling work [14].
In Chapter 7, the cell fabrication processes were determined based on the simulation results in
Chapter 6 while also considering the inevitable fabrication limitations. The main conclusions
of Chapter 7 are summarised below.
The improvement in the cell fabrication processes compared to previous IBC cell designs
include:
- Loading n-type 100 Ω.cm FZ wafers at high-temperature of 900 ˚C and oxidizing at
1000 ˚C was performed for one hour to permanently remove any low lifetime defects
caused by N2 doping.
150
- A thinner AZ1518 photoresist offers limited protection to the ONO rantex surfaces as
the tip of the pyramids are occasionally etched after BHF. A thicker photoresist was
used to protect the surface passivation at the front rantex surface from exposure to both
BHF and RIE.
- BRL gettering was implemented during the formation of the boron dot emitter to
maintain the bulk lifetime of wafers.
- TMAH with MonoTEX additives have shown consistent random texture etching results
across multiple test runs and cell wafers.
The following conclusions were made about the fabrication of the ONO IBC solar cells:
- No significant improvements to the surface passivation were observed on the boron
diffused test wafers as the SiNx refractive index n632 increased from 1.93 to 2.10.
- Positive corona charging on the front surface improved the cell Voc by 1–3 mV.
Annealing to embed the charges at 400 ˚C increased the local ideality factor and non-
ideal recombination within the cell. The annealing temperature was lowered to 250 ˚C
to embed the charges and improve the performance of the solar cell. This additional
annealing at 250 ˚C marginally affected the local ideality factor and non-ideal
recombination.
- In our experiments, the lift-off metallisation did not provide any means of lowering the
contact resistivity for ONO IBC solar cells. Conventional metallisation using thermal
evaporated Al on an ONO IBC solar cell achieved a low Rs of ~0.2 Ω.cm2.
The optimisation of the ONO dielectric stack, including the improved design from the previous
cell structure and refined fabrication process on an IBC solar cell, achieved an independent
measure efficiency of 25.0%. The ONO dielectric stack together with current cell designs is
capable of achieving an even higher cell efficiency as simulation results demonstrated an
efficiency reaching potentially 25.6% by reducing the J0 of the front surface recombination and
without non-ideal recombination.
151
152
A - Reflection of symmetrical pyramids
Symmetrical pyramids were investigated by defining the limits of light ray bounces within the
pyramid. The light ray for two identical pyramids with an angle of α can be calculated as shown
in Figure A.1 together with Eq A.1 and A.2, for ω between 31˚ and 54˚. For the rays to be
reflected twice, the minimum required angle of σ would have to be above 30˚. As σ increases
to above 45˚, all the rays are reflected twice. Table A.1 shows the reflected rays for the
symmetrical pyramids and the conditions required to attain lower reflections. As the angle of
the pyramid increased, the number of reflected rays on the pyramid increased, which reduced
the overall surface reflectance.
Fig A.1: Symmetrical pyramids with two rays reflecting at an angle of ω
= sin(3ω − 90)sin(90 − ω) (A.1)
180˚ − 2ω = 3ω − 90˚ (A.2)
The two-dimensional reflection calculations overlook the polarisation effects in a three-
dimensional textured surface. Moreover, most lab scale and industrial solar cells have
randomly textured surfaces.
The simulation for three-dimensional and irregular random textured surfaces requires ray
tracing to determine the possible path and fractions of light. As a result, the reflectivity can be
simulated using the optical simulator OPAL2, which considers various possible ray paths on
the random pyramids and accounts for the polarisation of the rays [19, 303].
Appendix
ω ω
2ω
90˚ - ω
360˚ - 6ω
180˚- 2ω
3ω - 90˚
Light ray
153
Table A.1: The reflection conditions and calculations for symmetrical pyramids in two-dimensions
Reflected Rays
(bounces)
Condition Fraction Reflectance Equation
1 ω≤30˚ 1 z4@40, 1:22
30˚<ω ≤ 45˚45˚<ω ≤ 54˚
(1-σ):σ1
z4@40, = (1 − )z + z=z4@40, = (1 − )z= + z=
= sin(3ω − 90)sin(90 − ω)
2:3 54˚<ω≤60˚
(1-β):β
z4@40, = (1 − ª)z= + ªz « = sin(5ω − 270)sin(270 − 3ω)
ª = « sin(3ω − 90)sin(90 − ω)
154
B - Metal-Semiconductor Contact
Metal contacts towards the silicon can be described as either ohmic or rectifying contacts. An
Ohmic contact has a linear response to the voltage and current, allowing charges to flow at
negative and positive bias polarities. In contrast, a rectifying contact allows either the current
to flow mostly in one direction with some leakage, or no current in the opposite direction.
Figure B.1 shows the band diagram for metal deposited onto a clean silicon surface under ideal
conditions. The Ohmic contact on an n-type silicon wafer can be achieved by selecting a metal
with a small ϕm, which reduces the barrier height of ϕBn. However, the opposite (a large ϕm)
would be required to make good Ohmic contact to the p-type silicon.
Fig B.1: Band diagram of the (a) rectifying and (b) Ohmic metal contact on an n-type silicon wafer.
A thin layer of native oxide commonly exists during the deposition of metal onto silicon, as
shown in Figure B.2. The thin oxide causes the interface density states (Dit) to exist due to
dangling bonds between the native oxide and silicon. The relationship between the Dit on the
surface and its effect on the pinning of the metal is described by Eq 6.17.
As Dit approaches infinite, γ becomes 0 (Bradeen limit) [304]. In this condition, the observed
barrier height of the ϕBn to n-type silicon is approximately 2/3 of the bandgap, while the ϕBp is
1/3 of the bandgap to p-type silicon [305], regardless of the ϕm. Turner et al. showed the barrier
height to be independent of the metal work function on a cleaved surface, which has a large Dit
[306]. However, when Dit approaches zero, and γ becomes 1 (Schottky-Mott limit) with δ being
0, the ϕBn and ϕBp become very dependent on ϕm [306]. Tao et al. showed that Cr and Al have
Ef,m
ϕm
Ef,Si
n-type
Metal
Evac
EC
EV
(a) Rectifying contact
χ Vbi ϕBn ϕBp
ϕs E
f,m ϕm
Ef,S
n-type
Metal
Evac
EC
EV
(b) Ohmic contact
χ ϕs
155
barrier heights that are closely related to the ideal conditions [307] when metallised onto an n-
type Si surface with a monolayer of selenium passivation with silicon χ at 4.29 eV [308].
ϕp = γ(ϕ2 − x) + (1 − «) Z± − ϕ;# − γm_i3 (6.17)
« = 11 + ²b34v;v/
(6.18)
QD: Charge in depleted region Ci: Capacitance of interface layer of native oxide δ: Native oxide thickness εr: Dielectric constant of native oxide
Fig B.2: Band diagram for the MOS on an n-type silicon wafer.
Another way to achieve Ohmic contacts is by contacting metal onto the heavily doped silicon.
There are three known conduction mechanisms on a diffused region: thermionic emission,
thermionic-field emission and field emission [309]. Thermionic emission occurs when the
silicon is lightly doped. The conduction processes will require the electrons to jump across the
potential barrier due to the large depletion region. The fourth characteristic for thermionic
emission is found to be similar to a rectifying contact. However, when the silicon is heavily
doped, the potential barrier is narrowed, and the electrons can tunnel through. This mode is
defined as ‘field emission’ and creates an Ohmic contact with the metal. When the silicon is
moderately doped, only a certain number of electrons can tunnel through the narrower region
of the potential barrier (such as the midsection of the potential barrier). This conduction is
Ef,m
ϕmE
f,Si
n-type Si
Metal
EC
EV
Metal Contact with interface states
χ Vi ϕBnϕ0E0
Qit Depletion
region
156
defined as ‘thermionic-field emission.’ The contact resistivities of these mechanisms are
modelled using different potential barriers, as plotted in Figure B.3 [309].
1018 1019 1020 102110
-8
10-6
10-4
10-2
100
102
104 TE 0.8 φBn
TE 0.7 φBn
Co
nta
ct R
esis
tan
ce
(Ω
/sq
)
Carrier Concentration (cm-3)
φBn
0.6
φBn
0.7
φBn
0.8
TE 0.6 φBn
Fig B.3: Model of emissions from Xu et al. with different potential barriers [309]. The model is generated using Al and Pt with ϕBn assumed at be 0.6–0.8 eV. The thermionic-field emission region is modelled at 1018 to 1020 cm-
3. The field emission dominates with carrier concentrations above 1020 cm-3. The thermionic emission is not dependent on the carrier concentration, which occurred at lower carrier concentrations, as shown by the dotted lines.
The various contact resistivities for the direct metal contacts and passivated contacts with TiO2
on heavy phosphorus diffusion are plotted in Figure B.4. Thermal evaporation of Al performed
in our laboratory is known to achieve the lowest contact resistivity by far. Hao et al. compared
the Ti deposition using a low-bias physical vapour deposition with the TiO2 passivated contacts
using ALD [310]. The passivated contacts with a TiO2 of 1.4 nm have shown lower contact
resistivities at low surface concentrations compared to direct Ti metallisation. This is due to
the Fermi level pinning with the surface passivation (Dit < infinite) [310]. Hao et al. found that
at lower surface concentrations (ND <4×1019 cm-3), the thermionic-field emission dominates,
with ϕBn on the Ti-TiO2-Si as measured to be ~0.14 eV compared to ~0.5 eV with Ti-Si [310].
Therefore, an Ohmic contact can be achieved either by lowering the Dit interface between the
metal and silicon by selecting an appropriate work function for both the dielectric and metal,
or by direct metal contact onto the heavily diffused regions [311].
157
1018
1019
1020
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
Model
φBn
0.7
φBn
0.6 φ
Bn 0.5
Al - Kean et al.
Al - Schroder et al.
Al - Yu et al.
Ti - Ashish et al.
TiO2-x
/ Ti - Ashish et al.
Ti - Hao et al.
TiO2 / Ti - Hao et al.
Conta
ct
Resis
tivity (
Ω.c
m2)
Surface Carrier Concentration (cm-3)
Fig B.4: Contact resistivity of the direct metal contact and passivated contacts with TiO2 on phosphorus-doped silicon.
158
Refereed journal papers:
1. Teng Choon Kho, Kean Fong, Keith McIntosh, Evan Franklin, Nicholas Grant,
Matthew Stocks, Sieu Pheng Phang, Yimao Wan, Er-Chien Wang, Kaushal Vora, Zin
Ngwe, Andrew Blakers. ‘Exceptional silicon surface passivation by an ONO dielectric
stack’, Volume 189, Pages 245–253, Solar Energy Materials and Solar Cells, 2019.
2. Kean Chern Fong, Teng Choon Kho, WenSheng Liang, Teck Kong Chong, Marco Ernst,
Daniel Walter, Matthew Stocks, Evan Franklin, Keith McIntosh, Andrew Blakers.
‘Phosphorus diffused LPCVD polysilicon passivated contacts with in-situ low pressure
oxidation’, Volume 186, Pages 236–242, Solar Energy Materials and Solar Cells, 2018.
3. T Niewelt, A Richter, TC Kho, NE Grant, RS Bonilla, B Steinhauser, J-I Polzin, F
Feldmann, M Hermle, JD Murphy, SP Phang, W Kwapil, MC Schubert. ‘Taking
monocrystalline silicon to the ultimate lifetime limit’, Volume 185, Pages 252–259,
Solar Energy Materials and Solar Cells, 2018.
4. Katherine A Collett, Ruy S Bonilla, Phillip Hamer, Gabrielle Bourret-Sicotte, Richard
Lobo, Teng Kho, Peter R Wilshaw. ‘An enhanced alneal process to produce SRV<1
cm/s in 1 Ω cm n-type Si’, Volume 173, Pages 50–58, Solar Energy Materials and Solar
Cells, 2017.
International conference papers:
5. Kean Chern Fong, Teng Choon Kho, WenSheng Liang, Teck Kong Chong, Marco
Ernst, Daniel Walter, Matthew Stocks, Evan Franklin, Keith McIntosh, Andrew
Blakers. ‘Optimization and Characterization of Phosphorus Diffused LPCVD
List of publications
159
Polysilicon Passivated Contacts with Low Pressure Tunnel Oxide’, Pages 2002–2005,
IEEE 7th World Conference on Photovoltaic Energy Conversion, 2018.
160
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