high current driver amplifier and digital vga/preamplifier with 3 … · 2019. 9. 14. · the...

High Current Driver Amplifier and Digital VGA/Preamplifier with 3 dB Steps

Data Sheet AD8260

Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES High current driver

Differential input—direct drive from DAC Preset gain: 1.5× −3 dB bandwidth: 195 MHz Large output drive: >±300 mA

VGA/preamplifier Low noise

Voltage noise: 2.4 nV/√Hz Current noise: 5 pA/√Hz

−3 dB bandwidth: 230 MHz Gain range: 30 dB in 3 dB steps

−6 dB to +24 dB (for preamplifier gain of 6 dB) Single-ended preamplifier input and differential VGA

output Supplies: 3.3 V to 10 V (with VMID enabled)

±3.3 V to ±5 V (with VMID disabled) Power: 93 mW with 3.3 V supplies

Power-down for VGA, driver amplifier, and system

APPLICATIONS Digital AGC systems Tx/Rx signal processing Power line transceivers

FUNCTIONAL BLOCK DIAGRAM

32

2

3

6

31 30

1.5kΩ 1kΩ

29 28 27 26 25

1kΩ 1.5kΩ

GM

HIGH CURRENT DRIVER

9

24

23

22

21

VMID4

1

AD8260

VMDO

TXEN

VMDI

VNCM

VPSB

ENBL

VGAP

VGAN

VNGR VPSR GNS3 GNS2 GNS1 GNS0 PRAO VNGR

VOCM INPP INRP INRN INPN TXFB VNEG VNEG

TXOP

TXOP

VPOS

VPOS

VPSR

VMDO

PRAI

FDBK

0719

2-00

1

5

7

8

10 11 12 13 14 1615

17

18

19

20

BIAS

VGA/PREAMPLIFIER

ATTENUATOR

GM STAGES

LOGIC

×1+ –

Figure 1. Functional Block Diagram

GENERAL DESCRIPTION The AD8260 includes a high current driver, usable as a transmitter, and a low noise digitally programmable variable gain amplifier (DGA), useable as a receiver.

The receiver section consists of a single-ended input preampli-fier, and linear-in-dB, differential-output DGA. The receiver has a small signal –3 dB bandwidth of 230 MHz; the driver small signal bandwidth is 195 MHz. The driver delivers ±300 mA, well suited for driving low impedance loads, even when connected to a 3.3 V supply.

The AD8260 DGA is ideal for trim applications and has a gain span of 30 dB, in 3 dB steps. Excellent bandwidth uniformity is maintained across the entire frequency range. The low output-referred noise of the DGA is advantageous in driving high speed ADCs. The differential output facilitates the interface to modern low voltage high speed ADCs.

Single-supply and dual-supply operation makes the part versatile and enables gain control of negative-going pulses, such as those generated by photodiodes or photo-multiplier tubes, as well as processing band-pass signals on a single supply. For maximum

dynamic range, it is essential that the part be ac-coupled when operating on a single supply.

The AD8260 preamplifier (PrA) is configured with external resistors for gains greater than 6 dB and can be inverting or noninverting. The DGA is characterized with a noninverting preamplifier gain of 2×. The attenuator has a range of 30 dB and the output amplifier has a gain of 8× (18.06 dB). The lowest noninverting gain range is −6 dB to +24 dB and shifts up with increased preamplifier gain. The gain is controlled via a parallel port (Pin GNS0 to Pin GNS3) with 10 gain steps of 3 dB per code. The preamplifier and DGA are disabled for any code that is not assigned a gain step.

The AD8260 can operate with single or dual supplies from 3.3 V to ±5 V. An internal buffer normally provides a split supply reference for single-supply operation; an external reference can also be used when the VMID buffer is shut down.

The operating temperature range is −40°C to +105°C. The AD8260 is available in a 5 mm × 5 mm, 32-lead LFCSP.

https://form.analog.com/Form_Pages/feedback/documentfeedback.aspx?doc=AD8260.pdf&product=AD8260&rev=Bhttp://www.analog.com/en/content/technical_support_page/fca.htmlhttp://www.analog.com/http://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.comhttp://www.analog.com/AD8260?doc=AD8260.pdf

AD8260 Data Sheet

Rev. B | Page 2 of 32

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Test Circuits ..................................................................................... 16 Theory of Operation ...................................................................... 20

Overview ...................................................................................... 20 High Current Driver Amplifier ................................................ 21 Precautions to Be Observed During Half-Duplex Operation ....................................................................................................... 22

VMID Buffer ............................................................................... 22 Preamplifier ................................................................................. 22 Preamplifier Noise ...................................................................... 22 DGA ............................................................................................. 23 Gain Control ............................................................................... 23 Output Stage ................................................................................ 23 Attenuator.................................................................................... 23 Single-Supply Operation and AC Coupling ........................... 24 Power-Up/Power-Down Sequence .......................................... 24 Logic Interfaces ........................................................................... 24

Applications Information .............................................................. 25 Evaluation Board ............................................................................ 26

Connecting the Evaluation Board ............................................ 27 Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY 5/16—Rev. A to Rev. B Change CP-32-8 to CP-32-21 ...................................... Throughout Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 2/11—Rev. 0 to Rev. A Added EPAD Notation .................................................................... 7 Changes to Figure 70 ...................................................................... 29 5/08—Revision 0: Initial Version

Data Sheet AD8260


SPECIFICATIONS VS (supply voltage) = 3.3 V, TA = 25°C, preamplifier gain = 2× (RFB1 = RFB2 = 100 Ω), VVMDO = VS/2, f = 10 MHz, CL = 5 pF, RLOAD = 500 Ω, DGA differential output. All dBm values are referenced to 50 Ω, gain code 1011, unless otherwise specified.

Table 1. Parameter Test Conditions/Comments Min Typ Max Unit

DRIVER AMPLIFIER—GENERAL PARAMETERS −3 dB Small Signal Bandwidth VOUT = 10 mV p-p, RLOAD = 500 Ω 195 MHz VOUT = 10 mV p-p, RLOAD = 50 Ω 120 MHz VOUT = 10 mV p-p, RLOAD = 10 Ω 85 MHz −3 dB Large Signal Bandwidth VOUT = 1 V p-p 195 MHz VOUT = 2 V p-p 190 MHz VOUT = 2 V p-p, RLOAD = 50 Ω 180 MHz Slew Rate VOUT = 1 V p-p 730 V/µs VOUT = 2 V p-p 725 V/µs VOUT = 2 V p-p, RLOAD = 50 Ω 620 V/µs Gain Nominal gain with internal gain setting resistors 3.0 3.52 dB Input Voltage Noise f = 10 MHz 9.5 nV/√Hz Noise Figure RS = 100 Ω (differential, 2 × 50 Ω that convert

differential DAC output currents to differential voltage) 17.6 dB

Output-Referred Noise Gain = 3.52 dB (1.5×), includes internal gain setting resistors

14.3 nV/√Hz

Output Impedance DC to 10 MHz, VS = ±3.3 V ≤1.7 Ω Output Current RLOAD = 1 Ω, VIN = ±0.5 V ±310 mA Output Signal Range RLOAD ≥ 500 Ω VMDO ± 1.5 V VS = +5 V VMDO ± 2.3 V VS = ±5 V ±4.7 V Input Signal Range Differential input signal 2 V p-p Output Offset Voltage Gain = 3.52 dB (1.5×), maximum and minimum limits

are 3σ −20 ±5 +20 mV

DRIVER AMPLIFIER—DYNAMIC PERFORMANCE Harmonic Distortion VOUT = 1 V p-p

HD2 f = 1 MHz −84 dBc HD3 −85 dBc HD2 f = 10 MHz −83 dBc HD3 −70 dBc

Harmonic Distortion VOUT = 2 V p-p HD2 f = 1 MHz −78 dBc HD3 −76 dBc HD2 f = 10 MHz −70 dBc HD3 −58 dBc

Input 1 dB Compression Point 13 dBm Multitone Power Ratio (MTPR, In-Band) RLOAD = 50 Ω, VOUT = 1.4 V p-p max, 10 tones, 2 MHz to

22 MHz with missing tone at 12 MHz (spacing 2 MHz) −49 dBc

RLOAD = 50 Ω, VOUT = 1.4 V p-p max, 16 tones, 2 MHz to 38 MHz with missing tones at 10 MHz, 20 MHz, 30 MHz, and 40 MHz (spacing 2 MHz)

−43 dBc

Two-Tone Intermodulation Distortion (IMD3) VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz −90 dBc VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz −71 dBc VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz −60 dBc VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz −48 dBc Output Third-Order Intercept VOUT = 1 V p-p, f = 10 MHz 43 dBm VOUT = 2 V p-p, f = 10 MHz 40 dBm VOUT = 1 V p-p, f = 45 MHz 28 dBm VOUT = 2 V p-p, f = 45 MHz 28 dBm Two-Tone Intermodulation Distortion (IMD3),

RLOAD = 50 Ω VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz −69 dBc

VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz −72 dBc VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz −51 dBc VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz −48 dBc

AD8260 Data Sheet


Parameter Test Conditions/Comments Min Typ Max Unit Output Third-Order Intercept, RLOAD = 50 Ω VOUT = 1 V p-p, f = 10 MHz 33 dBm VOUT = 2 V p-p, f = 10 MHz 40 dBm VOUT = 1 V p-p, f = 45 MHz 23 dBm VOUT = 2 V p-p, f = 45 MHz 28 dBm

PREAMPLFIER AND VGA—GENERAL PARAMETERS −3 dB Small Signal Bandwidth VOUT = 10 mV p-p, gain code = 0110 230 MHz −3 dB Large Signal Bandwidth VOUT = 1 V p-p, gain code = 0110 165 MHz VOUT = 2 V p-p, gain code = 0110 135 MHz Slew Rate VOUT = 1 V p-p, gain code = 0110 330 V/µs VOUT = 1.6 V p-p, gain code = 0110 335 V/µs Input Voltage Noise f = 10 MHz (shorted input) 2.4 nV/√Hz f = 10 MHz (input open) 6.2 nV/√Hz Noise Figure Maximum gain (gain code = 1011), RS = 50 Ω,

unterminated 10.2 dB

Maximum gain (gain code = 1011), RS = 50 Ω, shunt terminated with 50 Ω

15.5 dB

Output-Referred Noise Maximum gain (gain code = 1011), gain = 24 dB (input short)

38 nV/√Hz

Maximum gain (gain code = 1011), gain = 24 dB (input open)

98.1 nV/√Hz

Minimum gain (gain code = 0001), gain = −6 dB 25 nV/√Hz Output Impedance DC to 10 MHz ≤3 Ω Output Signal Range (per Pin) RLOAD ≥ 500 Ω VMDO ± 0.7 V VS = +5 V VMDO ± 1.4 V VS = ±5 V ±3.6 V Input Signal Range Preamplifier input VMDO ± 0.3 V Output Offset Voltage Maximum gain (gain code = 1011), gain = 24 dB, 3 σ

limits −50 ±20 +50 mV

PREAMPLIFIER AND VGA—DYNAMIC PERFORMANCE Harmonic Distortion Gain code = 0110, gain = 9 dB, VOUT = 1 V p-p

HD2 f = 1 MHz −90 dBc HD3 −87 dBc HD2 f = 10 MHz −75 dBc HD3 −58 dBc

Harmonic Distortion Gain code = 1011, gain = 24 dB, VOUT = 2 V p-p HD2 f = 1 MHz −94 dBc HD3 −90 dBc HD2 f = 10 MHz −61 dBc HD3 −84 dBc

Input 1 dB Compression Point Minimum gain (gain code = 0001), gain = −6 dB (preamplifier limited)

1.9 dBm

Maximum gain (gain code = 1011), gain = 24 dB (VGA limited)

−9.2 dBm

MTPR (In-Band) VOUT = 1.4 V p-p maximum, 10 tones, 2 MHz to 22 MHz with missing tone at 12 MHz (spacing 2 MHz), gain code = 1011, gain = 24 dB

−68 dBc

VOUT = 1.4 V p-p maximum, 16 tones, 2 MHz to 38 MHz with missing tones at 10 MHz, 20 MHz, 30 MHz, and 40 MHz (spacing 2 MHz)

−61 dBc

Two-Tone Intermodulation Distortion (IMD3) Gain code = 1011, gain = 24 dB VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz −92 dBc VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz −77 dBc VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz −50 dBc VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz −36 dBc Output Third-Order Intercept Gain code = 1011, gain = 24 dB

VOUT = 1 V p-p, f = 10 MHz 44 dBm VOUT = 2 V p-p, f = 10 MHz 43 dBm VOUT = 1 V p-p, f = 45 MHz 27 dBm VOUT = 2 V p-p, f = 45 MHz 22 dBm

Data Sheet AD8260


Parameter Test Conditions/Comments Min Typ Max Unit Overload Recovery Maximum gain (gain code = 1011), gain = 24 dB,

VIN = 50 mV p-p to 500 mV p-p 50 ns

Group Delay Variation 1 MHz < f < 50 MHz, full gain range 2 ns

ACCURACY Absolute Gain Error All gain codes, limits are 3σ −0.5 ±0.15 +0.5 dB Gain Law Conformance (DNL) Differential gain error, code to code −0.3 ±0.15 +0.3 dB

GAIN CONTROL Gain Step per Code 3.0 dB Gain Range Default = −6 dB to +24 dB 30 dB Response Time 30 dB gain change (gain code stepped from 0001 to 1011) 50 ns

LOGIC INTERFACES High Level Input Voltage 1.4 VS V Low Level Input Voltage 0 0.8 V Logic Input Bias Current Logic high, VLOGIC = 3.3 V 0.2 µA Logic low 18 nA

POWER SUPPLY Supply Voltage Single supply 3.3 10 V Dual supply ±3.3 ±5 V Quiescent Current Full chip enabled (TXEN = 1, ENBL = 1, gain code = 0001) 28.3 mA

TXEN = 0, ENBL = 1, gain code = 0001, driver off, DGA on 19.1 mA TXEN = 1, ENBL = 1, gain code = 0000, driver on, DGA off 10.8 mA Chip disabled (TXEN = 0, ENBL = 0, gain code = 0000) 35 µA VS = ±5 V, no signal 34.2 mA

PSRR Maximum gain (gain code = 1011), gain = 24 dB, 1 MHz −30 dB Driver amplifier, 1 MHz −48 dB Power Dissipation No signal 93 mW

No signal, VPOS − VNEG = 10 V 342 mW

ENABLE TIMES Chip Enable Time Bias only, TXEN = 0, gain code = 0000, ENBL = 0 to 1 0.4 µs All at once, TXEN = 0 to 1, gain code = 0000 to 0001,

ENBL = 0 to 1 0.3 µs

Preamplifier and DGA Enable Time ENBL = 1, TXEN = 0, gain code = 0000 to 0001 0.3 µs Driver Enable Time ENBL = 1, gain code = 0001, TXEN stepped from 0 to 1 0.2 µs

DISABLE TIMES Chip Disable Time TXEN = 1 to 0, gain code = 0001 to 0000,

ENBL = 1 to 0, ISUPPLY = 100 µA 20 µs

All at once, TXEN = 1 to 0, gain code = 0001 to 0000, ENBL = 1 to 0, ISUPPLY = 35 µA

50 µs

Preamplifier and DGA Disable Time ENBL = 1, TXEN = 0, gain code = 0001 to 0000 0.4 µs Driver Disable Time ENBL = 1, gain code = 0000, TXEN = 1 to 0 2.2 µs

AD8260 Data Sheet


ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Voltage

Supply Voltage (VPOS, VNEG) ±6 V Input Voltage (INxx, PRAI, FDBK, VMDI,

VOCM) VPOS, VNEG

Logic Voltages VPOS, ground Temperature

Operating Temperature Range –40°C to +105°C Storage Temperature Range –65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C

Thermal Data1 Maximum Junction Temperature 125°C θJA 47.3°C/W θJC 6.9°C/W θJB 28.6°C/W ΨJT 0.6°C/W ΨJB 27.4°C/W

1 Thermal data at zero airflow with exposed pad soldered to four-layer JEDEC board with vias per JESD51-5.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Data Sheet AD8260


PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

0719

2-00

2

VPSR

FDBKPRAIVMDO

VPOSVPOSTXOPTXOP

INPN

VNEG

VNEG

TXFB

INR

NIN

RP

INPP

VOC

M

PIN 1INDICATOR

VMDO

NOTES1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. THE GROUND PLANE PATTERN SHOULD INCLUDE A PATTERN OF VIAS TO INNER LAYERS.

TXENVMDI

VNCMVPSBENBLVGAPVGAN

VNG

RVP

SRG

NS3

GN

S2G

NS1

GN

S0PR

AO

VNG

R

2423222120191817

12345678

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

AD8260TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 191 VMDO VMID Buffer Output. Requires robust ac decoupling with a capacitance of 0.1 μF capacitor or greater. 2 TXEN Driver Enable. Logic threshold = 1.1 V with ±0.2 V hysteresis. 3 VMDI VMID Input Voltage. Normally decoupled with a 0.1 μF capacitor. When pulled to VNCM, the VMID buffer shuts

down. This can be useful when using the part with dual supplies or when an external midpoint generator is used. 4 VNCM Negative Supply for Bias Cell, VMID Cell, and Logic Inputs. (Ground this pin in applications.) 5 VPSB Positive Supply for Bias Cell and VMID Cell. 6 ENBL Enable. Logic threshold = 1.1 V. When low, the AD8260 is disabled and the supply current is 35 μA when TXEN

and all GNSx pins are also low. 7 VGAP Positive VGA Output (Needs to Be Ac-Coupled for Single Supply). 8 VGAN Negative VGA Output (Needs to Be Ac-Coupled for Single Supply). 9, 161 VNGR Negative Supply for Preamplifier and DGA (Set to −VPOS for Dual Supply; GND for Single Supply). 10, 201 VPSR Positive Supply for Preamplifier, DGA, and GNSx Logic Decoder. 11 GNS3 MSB for Gain Control. Logic threshold = 1.1 V. 12 GNS2 Gain Control Bit. Logic threshold = 1.1 V. 13 GNS1 Gain Control Bit. Logic threshold = 1.1 V. 14 GNS0 LSB for Gain Control. Logic threshold = 1.1 V. 15 PRAO Preamplifier Output. 17 FDBK Negative Input of Preamplifier. 18 PRAI Positive Input of Preamplifier. 21, 221 VPOS Positive Supply for Driver Amplifier. 23, 241 TXOP Driver Output. 25, 261 VNEG Negative Supply for Driver Amplifier (Set to −VPOS for Dual Supply; GND for Single Supply). 27 TXFB Feedback for Driver Amplifier. 28 INPN Negative Driver Amplifier Input. 29 INRN Negative Gain Resistor Input for Driver Amplifier. 30 INRP Positive Gain Resistor Input for Driver Amplifier. 31 INPP Positive Driver Amplifier Input. 32 VOCM Output Common Mode Pin. Normally connected to Pin VMDO. EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and

maximum thermal capability it is recommended that the pad be soldered to the ground plane. The ground plane pattern should include a pattern of vias to inner layers.

1 Pins with the same name are connected internally.

http://www.analog.com/AD8260?doc=AD8260.pdf

AD8260 Data Sheet


TYPICAL PERFORMANCE CHARACTERISTICS VS (supply voltage) = 3.3 V, TA = 25°C, CL = 5 pF, f = 10 MHz, preamplifier gain = 2×, RFB1 and RFB2 of the preamplifier = 100 Ω, RLOAD of the driver amplifier = 500 Ω, TX and RX enabled, unless otherwise specified.

5

1

0

2

3

4

GA

IN (d

B)

FREQUENCY (Hz)200M100M10M1M100k

T = –40°C

VOUT = 200mV p-p

T = +105°C

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3

T = +25°C

Figure 3. Small-Signal Frequency Response at Three Temperatures of the High Current Driver—See Figure 51

5

1

0

2

3

4

GA

IN (d

B)


VS = +5V

VOUT = 200mV p-pVS = +3.3V

VS = ±5V

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4

Figure 4. Small-Signal Frequency Response of the High Current Driver for Three Supply Voltages—See Figure 51

5

1

0

2

3

4

GA

IN (d

B)


0719

2-00

5

VLOAD = 1V p-p; RLOAD = 50ΩVLOAD = 1V p-p; RLOAD = 500ΩVLOAD = 2V p-p; RLOAD = 50ΩVLOAD = 2V p-p; RLOAD = 500Ω

Figure 5. Large-Signal Frequency Response of the High Current Driver for Two Values of Output Voltage and Two Values of Load Resistance—See Figure 51

20

0

5

10

15

NO

ISE

(nV/√H

z)

FREQUENCY (Hz)50M10M1M100k

RTO

RTI

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2-00

6

Figure 6. Input-Referred and Output-Referred Noise of the High Current Driver—See Figure 52

10

OU

TPU

T IM

PED

AN

CE

(Ω)

FREQUENCY (Hz)100M10M1M100k

100

0.1

1

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7

Figure 7. Output Impedance of the High Current Driver See Figure 53

–100

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

LOAD RESISTANCE (Ω)1k10010

–40

–20

–60

–80

–90

HD3HD2

–70

–50

–30

2V p-p

1V p-p

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8

Figure 8. Harmonic Distortion (HD2, HD3) vs. Load Resistance for the High Current Driver—See Figure 54

Data Sheet AD8260


–100

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

LOAD CAPACITANCE (pF)100400

–40

–20

–60

–80

–90

802010 60

f = 10MHz

–70

–50

–30

50 9030 70

HD2, VOUT = 1V p-pHD3, VOUT = 1V p-pHD2, VOUT = 2V p-pHD3, VOUT = 2V p-p

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9

Figure 9. Harmonic Distortion (HD2, HD3) vs. Load Capacitance at Two Values of Output Voltage for the High Current Driver—See Figure 54

–100

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

OUTPUT VOLTAGE (V p-p)3.01.50

–40

–20

–60

–80

–120

0

2.51.00.5 2.0

HD3 HD2

f = 10MHz

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0

Figure 10. Harmonic Distortion (HD2, HD3) vs. Output Voltage for the High Current Driver—See Figure 54

–100

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

FREQUENCY (Hz)100M10M1M

–40

–20

–60

–80

–90

HD3

HD2

–70

–50

–30

1V p-p

2V p-p

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1

Figure 11. Harmonic Distortion (HD2, HD3) vs. Frequency of the High Current Driver at Two Values of Output Voltage—See Figure 54

100MFREQUENCY (Hz)

2M

IMD

3 (d

Bc)

10M–100

–80

–60

–40

–20

0

RLOAD = 50Ω, VOUT = 1V p-pRLOAD = 50Ω, VOUT = 2V p-pRLOAD = 500Ω, VOUT = 1V p-pRLOAD = 500Ω, VOUT = 2V p-p

0719

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2

Figure 12. IMD3 vs. Frequency for Two Values of Output Voltage and Two Values of Load Resistance for the High Current Driver—See Figure 55

100MFREQUENCY (Hz)

2M

OIP

3 (d

Bm

)

10M

50

40

30

20

10

0

RLOAD = 50Ω, VOUT = 1V p-pRLOAD = 50Ω, VOUT = 2V p-pRLOAD = 500Ω, VOUT = 1V p-pRLOAD = 500Ω, VOUT = 2V p-p

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3

Figure 13. Third-Order Intercept (OIP3) vs. Frequency for the High Current Driver See Figure 55

0

20

IP1d

B (d

Bm

)


5

15

10

RLOAD = 50ΩRLOAD = 500Ω

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4

Figure 14. Input-Referred 1 dB Compression (IP1dB) vs. Frequency for Two Values of Load Resistance for the High Current Driver

AD8260 Data Sheet


–80

FREQUENCY (MHz)2422182 100 6 124 201614

0

8

OU

TPU

T (d

Bm

)

–60

–40

–90

–70

–20

–50

–30

–10

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5

Figure 15. Missing Tone Power Ratio for the High Current Driver

0

0.15

–0.15

0 .05

0.10

OU

TPU

T VO

LTA

GE

(V)

TIME (ns)807060

–0.05

–0.10

–20 10–30 0 30–10 20 5040–0.20

0.20

RLOAD = 10ΩRLOAD = 50ΩRLOAD = 100ΩRLOAD = 500Ω

CLOAD = 5pFNONINVERTING

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6

Figure 16. Small-Signal Pulse Response of the High Current Driver for Various Values of Load Resistance, RLOAD—See Figure 56

0

0.15

–0.15

0.05

0.10

OU

TPU

T VO

LTA

GE

(V)

TIME (ns)807060

–0.05

–0.10

–20 10–30 0 30–10 20 5040–0.20

0.20

CLOAD = 5pF

CLOAD = 47pFCLOAD = 10pF

RLOAD = 500ΩNONINVERTING

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7

Figure 17. Small-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, CLOAD, and RLOAD = 500 Ω—See Figure 56

0

0.15

–0.15

0.05

0.10

OU

TPU

T VO

LTA

GE

(V)

TIME (ns)807060

–0.05

–0.10

–20 10–30 0 30–10 20 5040–0.20

0.20

CLOAD = 5pF



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2-01

8

Figure 18. Small-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, CLOAD, and 50 Ω Load—See Figure 56

OU

TPU

T VO

LTA

GE

(V)

TIME (ns)80706020 1030 0 3010 20 5040

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

RLOAD = 10ΩRLOAD = 50ΩRLOAD = 100ΩRLOAD = 500Ω

CLOAD = 5pFNONINVERTING

0719

2-01

9

Figure 19. Large-Signal Pulse Response of the High Current Driver for Various Values of Load Resistance, RLOAD—See Figure 56

0

1.5

–1.5

0.5

1.0

OU

TPU

T VO

LTA

GE

(V)

TIME (ns)807060

–0.5

–1.0

–20 10–30 0 30–10 20 5040–2.0

2.0

CLOAD = 5pF



0719

2-02

0

Figure 20. Large-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, CLOAD, and RLOAD = 500 Ω—See Figure 56

Data Sheet AD8260


OU

TPU

T VO

LTA

GE

(V)

TIME (ns)

CLOAD = 5pFCLOAD = 10pFCLOAD = 47pF

807060–20 10–30 0 30–10 20 5040


2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0719

2-02

1

Figure 21. Large-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, CLOAD, and 50 Ω Load—See Figure 56

27

24

21

18

15

12

9

6

3

0

–3

–6

–9

GAIN SELECT CODE

GA

IN (d

B)

0719

2-02

2

10111010100110000111011001010001 010000110010

AVERAGE OF 3 SAMPLESf = 1MHz, 10MHz, AND 40MHz

Figure 22. Gain vs. Gain Select Code for Three Samples for the VGA/Preamplifier at Three Frequencies—See Figure 57

4.00

3.75

3.50

3.25

3.00

2.75

2.50

2.25

2.00

GA

IN S

TEP

(dB

)

0719

2-02

3


GAIN SELECT CODE1011101010011000011101100101010000110010

Figure 23. Gain Step vs. Gain Select Code for Three Samples for the VGA/Preamplifier at Three Frequencies—See Figure 57

1.00

0.75

0.50

0.25

0

–0.25

–0.50

–0.75

–1.000001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011

GAIN SELECT CODE

AB

SOLU

TE G

AIN

ER

RO

R (d

B)

0719

2-02

4


Figure 24. Absolute Gain Error vs. Gain Select Code for Three Samples for the VGA/Preamplifier at Three Frequencies Normalized to 1 MHz and Code 0110

See Figure 57

1.00

0.75

0.50

0.25

0

–0.25

–0.50

–0.75

–1.000001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011

GAIN SELECT CODE

GA

IN E

RR

OR

(dB

)

0719

2-02

5

AVERAGE OF 3 SAMPLES ATEACH TEMPERATURE

T = +105°CT = +25°CT = –40°C

Figure 25. Gain Error vs. Gain Select Code at Three Temperatures for the VGA/Preamplifier—See Figure 57

0

–40

–30

–20

50

20

30

40

–50

OFF

SET

VOLT

AG

E (m

V)

GAIN SELECT CODE1010100110000111011001010001 010000110010

AVERAGE OF 3 SAMPLES ATEACH TEMPERATURE

1011

10

–10

T = +105°CT = +25°CT = –40°C

0719

2-02

6

Figure 26. Output Offset Voltage vs. Gain Select Code at Three Temperatures for the VGA/Preamplifier—See Figure 58

AD8260 Data Sheet


27

24

21

18

15

12

9

6

3

0

–3

–12

–6

–9

100k 1M 10M 100M 200MFREQUENCY (Hz)

DIF

FER

ENTI

AL

GA

IN (d

B)

0719

2-02

7

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

Figure 27. Frequency Response for a Supply Voltage (VS) of 3.3 V for all Codes of the VGA/Preamplifier—See Figure 59

27

24

21

18

15

12

9

6

3

0

–3

–12

–6

–9


DIF

FER

ENTI

AL

GA

IN (d

B)

0719

2-02

8

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

VS = 5V

Figure 28. Frequency Response for a Supply Voltage (VS) of 5 V for All Codes for the VGA/Preamplifier—See Figure 59

27

24

21

18

15

12

9

6

3

0

–3

–12

–6

–9


DIF

FER

ENTI

AL

GA

IN (d

B)

0719

2-02

9

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

VS = ±5V

Figure 29. Frequency Response for a Dual Supply (VS) = ±5 V for All Codes for the VGA/Preamplifier—See Figure 59

10

8

6

4

2

01M 10M 100M

FREQUENCY (Hz)

GR

OU

P D

ELA

Y (n

s)

0719

2-03

0

Figure 30. Group Delay vs. Frequency for the VGA/Preamplifier See Figure 59

100

OU

TPU

T R

ESIS

TAN

CE

(Ω)

FREQUENCY (Hz)100M

0.11M100k 10M

VGAP

10

1

VGAN

0719

2-03

1

Figure 31. Output Resistance vs. Frequency for the VGA/Preamplifier See Figure 60

10

50

20

30

40

GAIN SELECT CODE

OU

TPU

T-R

EFER

RED

NO

ISE

(nV/√H

z)

1010100110000111011001010001 010000110010 1011

0719

2-03

2

Figure 32. Output-Referred Noise vs. Gain Select Code for the VGA/Preamplifier—See Figure 61

Data Sheet AD8260


10

100

FREQUENCY (Hz)

OU

TPU

T-R

EFER

RED

NO

ISE

(nV/√H

z)

10M100k 1M 50M

GAIN CODE = 1011

0719

2-03

3

Figure 33. Output-Referred Noise vs. Frequency for the VGA/Preamplifier at Maximum Gain—See Figure 61

1

100

10

GAIN SELECT CODE

INPU

T-R

EFER

RED

NO

ISE

(nV/√H

z)

1010100110000111011001010001 010000110010 1011

0719

2-03

4

Figure 34. Input-Referred Noise vs. Gain Select Code for the VGA/Preamplifier See Figure 61

1

10

FREQUENCY (Hz)

SHO

RT-

CIR

CU

IT IN

PUT-

REF

ERR

ED N

OIS

E(n

V/√H

z)

10M100k 1M 50M

GAIN CODE = 1011

0719

2-03

5

Figure 35. Short-Circuit Input Noise vs. Frequency for the VGA/Preamplifier See Figure 61

50

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

LOAD RESISTANCE (Ω)1800160014001200200 10008004000 2000

30

40

60

80

70

600

HD2HD3

0719

2-03

6

VOUT = 1V p-pGAIN CODE = 0110

Figure 36. Harmonic Distortion (HD2, HD3) vs. Load Resistance for the VGA/Preamplifier—See Figure 62

LOAD CAPACITANCE (pF)

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

–70

–60

–50

–40

–30

–8010 400 3020 50

VOUT = 1V p-pGAIN CODE = 0110

HD2HD3

0719

2-03

7

Figure 37. Harmonic Distortion (HD2, HD3) vs. Load Capacitance for the VGA/Preamplifier—See Figure 62

–120

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)

GAIN SELECT CODE101010011000011101100101 1011

–20

–40

–60

–80

–100

0

MEASUREMENT OFDISTORTION IS

LIMITED BY THEMAXIMUM DYNAMIC

INPUT RANGE OFTHE PREAMPLIFIER

HD2, fC = 1MHz

VOUT = 1V p-p

HD3, fC = 1MHzHD2, fC = 10MHzHD3, fC = 10MHz

0719

2-03

8

Figure 38. Harmonic Distortion (HD2, HD3) vs. Gain Select Code at 1 MHz and 10 MHz for the VGA/Preamplifier—See Figure 62

AD8260 Data Sheet


0

–100

HA

RM

ON

IC D

ISTO

RTI

ON

(dB

c)


–40

–20

–60

–80

–120

HD2HD3

GAIN CODE = 1011VOUT = 1V p-p

0719

2-03

9

Figure 39. Harmonic Distortion (HD2, HD3) vs. Frequency for the VGA/Preamplifier—See Figure 62

0

–100

IMD

3 (d

Bc)


–40

–20

–60

–80

–120

LOWERUPPER

VOUT = 1V p-pTONES 1MHz APARTEACH TONE 0.5V p-pGAIN CODE = 1011

0719

2-04

0

Figure 40. Third-Order Intermodulation Distortion (IMD3) vs. Frequency for the VGA/Preamplifier

60

10

OIP

3 (d

Bm

)


40

50

30

20

0

LOWERUPPER

GAIN CODE = 1011TONES 1MHz APART

0719

2-04

1

Figure 41. OIP3 vs. Frequency for the VGA/Preamplifier

10

5

0

–5

–10

–15

–20

–25

–30

GAIN SELECT CODE

INPU

T IP

1dB

(dB

m)

1010100110000111011001010001 010000110010 1011

1MHz10MHz

IP1dB LIMITED AT LOW GAIN BY THEDYNAMIC RANGE OF THE PREAMPLIFIER

0719

2-04

2

Figure 42. Input 1 dB Compression (IP1dB) vs. Gain Select Code at 1 MHz and 10 MHz for the VGA/Preamplifier

0719

2-04

3

CH1 2.00VΩM10.0ns A CH4 180µV

1

M

T 27.2000ns

T

MATH 5.00mV 10.0ns

INPUT

OUTPUT50mV/DIV0V

2mV/DIV0V

Figure 43. Small-Signal Pulse Response for the VGA/Preamplifier

0719

2-04

4

CH3 20.0mVΩM10.0ns A CH4 200µV

3

M

T 27.2000ns

T

MATH 50.0mV 10.0ns

INPUT

OUTPUT500mV/DIV0V

20mV/DIV0V

Figure 44. Large-Signal Pulse Response for the VGA/Preamplifier

Data Sheet AD8260


1.5

1.0

0.5

0

–0.5

–1.0

–1.5–3 –2 –1 0 1 2 3 4 5 6 7 8

TIME (ns)

OU

TPU

T VO

LTA

GE

(V)

0719

2-04

5

VS = +3V, +5V, AND ±5V

Figure 45. Large-Signal Pulse Response for Various Values of Supply Voltage for the VGA/Preamplifier

0719

2-04

6

CH1 1.00VΩ CH2 20.0mVΩ

MATH 100mV 200nVCH2 20.0mVΩ

M200ns A CH1 760mV

1

M

4

T 595.200ns

CH1 AMPL3.28V

CH2 AMPL1.20mV

MATH AMPL117mV

T

Figure 46. Gain Response for the VGA/Preamplifier, Yellow: Gain Code Select, Red: VGA Differential Output, Blue/Green: VGAP and VGAN

0

1

OU

TPU

T VO

LTA

GE

(V)

TIME (ns)800700600

–1

–200 1000 300–100 200 500400–2

2

0719

2-04

7

Figure 47. Overdrive Recovery of the VGA/Preamplifier—Gain Code = 1011

FREQUENCY (Hz)

PSR

R (d

B)

1M100k 5M

–10

–20

–30

–40

–50

–60

–70

–SUPPLY HIGH CURRENT DRIVER

+SUPPLY HIGH CURRENT DRIVER+SUPPLY VGA/PREAMPLIFIER

–SUPPLY VGA PREAMPLIFIER

VS = ±3.3VGAIN CODE = 1011

0719

2-04

8

Figure 48. PSRR vs. Frequency for Dual Supplies for the High Current Driver and the VGA/Preamplifier

QU

IESC

ENT

SUPP

LY C

UR

REN

T (m

A)

0

40

30

–55

10

TEMPERATURE (C)5 25 45

20

65 85 105 125–15–35

5

15

35

25

FULLY ENABLEDVGA/PREAMPLIFIER ENABLEDHIGH CURRENT DRIVER ENABLED

0719

2-04

9

Figure 49. Quiescent Supply Current vs. Temperature for Three Operating States

STA

ND

BY

QU

IESC

ENT

SUPP

LY C

UR

REN

T (µ

A)

–55 –35 –15TEMPERATURE (°C)

5 25 45 65 85 105 125

80

70

60

50

40

30

20

10

0

0719

2-05

0

Figure 50. Standby Quiescent Supply Current vs. Temperature

AD8260 Data Sheet


TEST CIRCUITS

INRP

–

+

NETWORK ANALYZER

VOCM

453Ω

INRN

50Ω INOUT

0.1µF

5pF

0.1µF

50Ω

AD8260—HIGH CURRENT DRIVER

TXFB

TXOP

VMDO

50Ω0.1µF

+

–

0719

2-15

1

Figure 51. Test Circuit for Frequency Response of the High Current Driver

IN

50ΩINRP

–

+

VOCM

INRN

0.1µF

0.1µF0.1µF

TXFB

TXOP–

+

VMDO

SPECTRUMANALYZER

0719

2-15

2


Figure 52. Test Circuit for Input-Referred and Output-Referred Noise of the High Current Driver

NETWORK ANALYZERWITH S-PARAMETER MODE

IN

50Ω

INRP

VOCM

INRN

0.1µF

0.1µF

TXFB

TXOP

+3.3V

–3.3V

–

+

0719

2-15

3

AD8260—HIGHCURRENT DRIVER

Figure 53. Test Circuit for Output Impedance of the High Current Driver

SIGNALGENERATOR

50Ω

LPFILTER

IN

50ΩINRP

VOCM

INRN0.1µF

0.1µF

0.1µF

TXFB

TXOP

VMDO

SPECTRUMANALYZER

50Ω

50Ω

RLOAD

CLOAD

1:1

0719

2-15

4


–

+

Figure 54. Test Circuit for Harmonic Distortion of the High Current Driver

Data Sheet AD8260


SIGNALGENERATORS

50Ω

IN

50ΩINRP

VOCM

INRN0.1µF

0.1µF

0.1µF

TXFB

TXOP

VMDO

SPECTRUMANALYZER

453Ω

1kΩ

1kΩ1:1

0719

2-15

5


50Ω

–

+

Figure 55. Test Circuit for IMD3 and OIP3 of the High Current Driver

OSCILLOSCOPE

IN

50Ω

50ΩINRP

–

+

VOCM

INRN

0.1µF

0.1µF

0.1µF

TXFB

TXOP

VMDO

50Ω

12.5Ω

RLOAD

CLOAD

0719

2-15

6


Figure 56. Test Circuit for Pulse Response of the High Current Driver

OSCILLOSCOPE

IN 50Ω

50Ω

453Ω

453Ω

VMDO

0.1µF0.1µF

0.1µF100Ω

SIGNALGENERATOR

50Ω

+

–

100Ω

PREAMP

0719

2-15

7

AD8260—VGA/PREAMPLIFIER

Figure 57. Test Circuit for Gain Step Size and Error of the VGA/Preamplifier

DMM

VMDO

0.1µF

100Ω

+

–

100Ω

PREAMP

0719

2-15

8


Figure 58. Test Circuit for Output-Referred Offset Voltage of the VGA/Preamplifier

AD8260 Data Sheet


VMDO

0.1µF

100Ω

+

–

100Ω

PREAMP

IN

NETWORK ANALYZER

0.1µF 453Ω

0.1µF 453Ω

50Ω

50Ω

0719

2-15

9


Figure 59. Test Circuit for Frequency Response and Group Delay of the VGA/Preamplifier

+3.3V

–3.3V

0.1µF

100Ω

+

–

100Ω

PREAMP

IN

NETWORK ANALYZERWITH S-PARAMETER

CAPABILITY

50Ω

0719

2-16

0


Figure 60. Test Circuit for Output Resistance of the VGA/Preamplifier

0.1µF

1kΩ

1kΩ

100Ω

100Ω

VMDO

VMDO

SPECTRUMANALYZER

50Ω

+

–PREAMP VGA

0.1µF

0.1µF

0.1µF

AD8129

×10

0719

2-05

1


Figure 61. Test Circuit for Input-Referred and Output-Referred Noise Measurements of the VGA/Preamplifier

Data Sheet AD8260


0.1µF 475Ω

475Ω

100Ω

100Ω

VMDO

+

–PREAMP

0.1µF

0.1µF

0719

2-05

2

SPECTRUMANALYZER

50Ω1:1

LPFILTER

50Ω50Ω

SIGNALGENERATOR

IN


Figure 62. Test Circuit for Harmonic Distortion Measurements of the VGA/Preamplifier

VMDO

0.1µF

100Ω

+

–

100Ω

PREAMP

OSCILLOSCOPE

50Ω

50Ω IN 50Ω

0719

2-16

3


Figure 63. Test Circuit for IP1dB, Pulse Response, Overdrive Recovery, and Gain Response of the VGA/Preamplifier

AD8260 Data Sheet


THEORY OF OPERATION OVERVIEW The AD8260 is a self-contained transceiver intended for analog communications using a power line as the media. Operating on supplies as low as 3.3 V, it includes a high current driver usable as a transmitter and a low noise digitally programmable variable gain amplifier (DGA), usable as a receiver (see Figure 64). An uncommitted current-feedback high frequency op amp acts as a preamplifier and interface to the DGA and is user configured for gains greater than 6 dB. Combined, the VGA and preamplifier are usable at high signal levels from dc to 100 MHz, with a small-signal −3 dB bandwidth of 230 MHz. To implement a high current-output VGA, the VGA output can be connected to the driver-amplifier differential input.

The small-signal −3 dB bandwidth of the driver amplifier is 195 MHz and the large-signal bandwidth is >115 MHz, even when driving a 50 Ω load.

The device is fabricated on the Analog Devices, Inc., high speed (eXtra Fast Complementary Bipolar) XFCB process. The pream-plifier and DGA feature low dc offset voltage, and a nominal gain range of −6 dB to +24 dB, a 30 dB gain span, and a differential output for ADC driving. The power consumption is 93 mW with a single 3.3 V supply. The supply current is typically about 28 mA when all circuits in the device are active. During normal usage, either the driver amplifier is on or the preamplifier and DGA are on and, therefore, the supply current in general is less than 28 mA. The gain of the AD8260 VGA is programmed via a

4-bit parallel interface. Figure 64 shows the circuit block diagram and basic application connections, and illustrates the envisioned external DAC, ADC, and power-line bus interface connections. The diagram shows the connections for single 3.3 V supply operation; if a dual supply is available, the VMID generator can be shut down and Pin VMDI, Pin VMDO, and Pin VOCM need to be grounded. Note that Pin VNCM functions as the negative supply for the bias and VMID cells, plus the logic interfaces, and should always be tied to ground.

For optimal dynamic range, it is important that the inputs and outputs to both the driver amplifier and the preamplifier and the DGA output amplifier be ac-coupled in a single-supply application. In Figure 64, the DAC and ADC are presumed to operate on a 1.8 V or 3.3 V supply with a corresponding limited output and input swing. The DAC outputs are currents that point down and generate a voltage in the 50 Ω resistors that are connected to ground. The maximum voltage with a peak DAC output current of 15 mA is 0.75 V; if a DAC with a 20 mA peak current is used, then the maximum voltage is 1 V per side for a differential input signal of 2 V p-p.

The driver amplifier supports a 3 V p-p output swing on a 3.3 V supply. Because of its gain of 1.5, the maximum input swing is 2 V p-p. The corresponding maximum output swing for the DGA is 2.4 V p-p differential; the input to the preamplifier can be a maximum of 0.6 V p-p.

http://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdf

Data Sheet AD8260


32

2

3

6

31 301.5kΩ 1kΩ

29 27 26 251kΩ 1.5kΩ

GM

9

24

23

22

21

VMID4

×1

1

AD8260

VMDO

TXEN

VMDI

VNCM

VPSB

ENBL

VGAP

VGAN

VNG

R

VPSR

GN

S3

GN

S2

GN

S1

GN

S0

PRA

O

VNG

R

VOCM INPP INR

P

INR

N

INPN

TXFB

VNEG

VNEG

TXOP

TXOP

VPOS

VPOS

VPSR

VMDO

PRAI

FDBK

0719

2-05

3

50Ω

0.1µF

0.1µF

0V, 1.8V/3.3V

0V, 1.8V/3.3V

53.3V

7

8

0.1µF

0.1µF

1.8V OR 3.3V

ADCFS INPUT

2V p-p

INP

INN

10

3.3V

11 12 13 14 1615

17

18

19

RFB1100Ω

RFB2100Ω

0.1µF

20 3.3V

0.1µF

0.1µF

POWERLINECABLE, ETC.

OPTIONAL CLAMP DIODESAND SNUBBING RESISTORS

0.1µF0.1µF50Ω

1.8V OR 3.3V

20mA DAC

1V MAX WITH200mA pk

BIAS

ATTENUATOR

GM STAGES

LOGIC

28

CFB

OPTIONAL USER SELECTEDCFB REDUCES HF PEAKINGWITH CAPACITIVE LOADING

LOW-PASSAA FILTER

+ –

Figure 64. Block Diagram and Basic Application Connections

HIGH CURRENT DRIVER AMPLIFIER The high current driver amplifier can deliver very large output currents suitable for driving complex impedances, such as a power line, a 50 Ω line, or a coaxial cable. The input of the amplifier is fully differential and intended to be driven by a differential current-output DAC, as shown in Figure 64. The differential input signal is amplified by 1.5× and produces a 2.25 V p-p single-ended output signal from a 1.5 V p-p input signal. A DAC with 15 mA maximum output current into a 50 Ω load provides 1.5 V p-p of input voltage and results in 2.25 V p-p at the output. A DAC whose output is 20 mA produces an output swing of 3 V p-p (neglecting a small gain error when driving the parallel combination of the 50 Ω load-resistor and the internal 1 kΩ gain resistor of the AD8260).

For a 3.3 V supply rail, the maximum limit of the output voltage is 3 V p-p and distorts severely if exceeded. The recommended output for optimum distortion is 2 V p-p for a 3.3 V supply. Correspondingly, larger output swings are accommodated for higher supply voltages such as +5 V or ±5 V.

For optimum distortion, the input drive must be controlled such that the output swing is well within saturation levels established by the supply rail. The output swing can be reduced by using load resistors with values less than 50 Ω or by reducing the amplifier gain by connecting external resistors in parallel with the internal 1 kΩ and 1.5 kΩ resistors between Pin 27, Pin 28, and Pin 29, and between Pin 30, Pin 31, and Pin 32. Coincidently, noise is reduced because the gain setting resistors are the primary noise sources of the high current driver amplifier.

The output-referred noise is 14 nV/Hz, of which 11 nV/Hz is due to the gain setting resistors. Matching of the gain setting resistors is important for good common-mode rejection and the accuracy of the differential gain. If external resistors are used, their accuracy should be at least ±1%. How low the resistor values can be is primarily determined by the quality of the ac ground at Pin VOCM; as the gain setting resistors decrease in value, the dynamic current increases, and the quality of the decoupling capacitors needs to increase correspondingly.


AD8260 Data Sheet


PRECAUTIONS TO BE OBSERVED DURING HALF-DUPLEX OPERATION During receive, when the high current driver-amplifier is disabled, its gain setting resistors provide a signal path from input to output. To prevent inadvertent DAC signals from being transmitted while receiving via the preamplifier and DGA, the DAC in Figure 64 must have no output signal.

During transmit, the preamplifier and VGA should be disabled through any of the nongain-setting codes (see Table 4).

VMID BUFFER The VMID buffer is a dc bias source that generates the voltage on Pin 1 and Pin 19, VMDO. Node VMDO cannot accommodate large dynamic currents and requires excellent ac decoupling to ground. A high quality 0.1μF capacitor located as close as possible to Pin 1 and Pin 19 (see Figure 64) is normally sufficient to decouple the high values of current from Node VMDO.

When operating with dual power supplies, the buffer is disabled by connecting Pin VMDI, Pin VOCM, and Pin VMDO to ground. Because the logic decoder in the DGA (GNSx inputs) requires 3.3 V of headroom, the positive supply rails must be 3.3 V or greater whether single-ended or dual. If a dual supply is used, the negative rails are the same magnitude (opposite polarity) as the positive, that is, −3.3 V when VPOS, VPSB, and VPSR are +3.3 V.

PREAMPLIFIER The AD8260 includes an uncommitted current feedback op amp to buffer the resistive attenuator of the DGA. External resistors are used to adjust the gain. The preamplifier is characterized with a noninverting gain of 6 dB (2×) and both gain resistor values of 100 Ω. The preamplifier gain can be increased using different gain ratios of RFB1 and RFB2, trading off bandwidth and offset voltage. The sum of the values of RFB1 and RFB2 should be ≥200 Ω to maintain low distortion. RFB2 should be ≥100 Ω because it and an internal compensation capacitor

determine the −3 dB bandwidth of the amplifier. Smaller resistor values may compromise preamplifier stability.

Because the AD8260 is internally dc-coupled, larger preamplifier gains increase its offset voltage. The circuit contains an internal bias resistor and some offset compensation; however, if a lower value of offset voltage is required, it can be compensated by connecting a resistor between the FDBK pin and the supply voltage. If the offset is negative, the resistor value connects to the negative supply; otherwise, it connects to the positive supply.

For larger gains, the overall noise is reduced if a low value of RFB1 is selected. For values of RFB1 = 20 Ω and RFB2 = 301 Ω, the preamplifier gain is 16× (24.1 dB) and the input-referred noise is about 1.5 nV/√Hz. For this value of gain, the overall gain range increases by 18 dB so that the absolute gain range is 12 dB to 42 dB.

PREAMPLIFIER NOISE The total input-referred voltage and current noise of the positive input of the preamplifier is about 2.4 nV/Hz and 5 pA/Hz, respectively. The DGA output referred noise is about 25 nV/Hz at low gains and 39 nV/Hz at the highest gain. The 25 nV/Hz divided by the DGA fixed gain of 8× results in 3.12 nV/Hz referred to the DGA input. Note that this value includes the noise of the DGA gain setting resistors as well. If this voltage is divided by the preamplifier gain of 2×, the DGA noise referred all the way to the preamplifier input is about 1.56 nV/Hz. From this, it can be determined that the preamplifier, including the 100 Ω gain setting resistors, contributes about 1.8 nV/Hz. The two 100 Ω resistors each contribute 1.29 nV/Hz at the output of the preamplifier and 0.9 nV/Hz referred to the input. With the gain resistor noise subtracted, the preamplifier noise alone is about 1.6 nV/Hz.

Equation 1 shows the calculation that determines the output-referred noise at maximum gain (24 dB or 16×).

2,2,21

2,

2,

2,

2, )()()()()( VGAVGAnVGARFB2nVGA

FB

FBRFB1nSPrAntPrAntRSnoutn AeAeAR

ReRiAeAee (1)

where: At is the total gain from preamplifier input to the VGA output. en,RS is the noise of the source resistance. en,PrA is the input-referred voltage noise of the preamplifier. in,PrA is the current noise of the preamplifier at the PRAI pin. RS is the source resistance. AVGA is the VGA gain. en,RFB1 is the voltage noise of RFB1. en,RFB2 is the voltage noise of RFB2. en,VGA is the input-referred voltage noise of DGA (low gain output-referred noise divided by a fixed gain of 8×).


Data Sheet AD8260


Assuming RS = 0, RFB1 = RFB2 = 100 Ω, At = 16, and AVGA = 8, the noise simplifies to

Hz/nV39

)812.3()829.1(2)166.1( 222 outne (2)

Taking this result and dividing by 16 gives the total input-referred noise with a short-circuited input as 2.4 nV/Hz. When the preamplifier is used in the inverting configuration with the same RFB1 = RFB2 = 100 Ω as in the previous example, then en-out does not change; however, because the gain decreases by 6 dB, the input-referred noise increases by a factor of 2 to about 4.8 nV/Hz. The reason for this is that the noise gain to the DGA output of all the noise generators stays the same, but the preamp inverting gain is (−1×) compared to the (+2×) in the noninverting configuration. This doubles the input-referred noise.

DGA Referring to Figure 64, the signal path consists of a 30 dB programmable attenuator followed by a fixed gain amplifier of 18 dB for a total DGA gain range of −12 dB to +18 dB. With the preamplifier configured for a gain of 6 dB, the composite gain range is −6 dB to +24 dB from single-ended preamplifier input to differential DGA output.

The DGA plus preamplifier with 6 dB of gain implements the following gain law:

)dB(01.3)dB( ICPTCodeCode

dBGain

where: ICPT is the nominal intercept, −9 dB. Code values are decimal from 1 to 11.

The ICPT increases as the gain of the preamplifier is increased. For example, if the gain of the preamplifier is increased by 6 dB, then ICPT increases to −3 dB.

GAIN CONTROL To change the gain, the desired four bits are programmed on Pin GNS0 to Pin GNS3, where GNS0 is the LSB (D0) and GNS3 is the MSB (D3). The states of Decimal 0 and Decimal 12 through Decimal 15 disable the preamplifier (PrA) and DGA (see Table 4).

Table 4. Gain Control Logic Table D3 D2 D1 D0 Function Comments 0 0 0 0 Disable PrA and DGA powered down 0 0 0 1 −6 The numbers in the function

column are composite gain values in dB for the corresponding code, when the preamplifier gain is 6 dB. For other values of preamplifier gain, the gain is amended accordingly; for example, if the preamplifier gain is 12 dB, the gain values increase by 6 dB. When using the DGA single ended, the composite gain decreases by 6 dB.

0 0 1 0 −3 0 0 1 1 0 0 1 0 0 3 0 1 0 1 6 0 1 1 0 9 0 1 1 1 12 1 0 0 0 15 1 0 0 1 18 1 0 1 0 21 1 0 1 1 24

1 1 0 0 Disable PrA and DGA powered down 1 1 0 1 Disable PrA and DGA powered down 1 1 1 0 Disable PrA and DGA powered down 1 1 1 1 Disable PrA and DGA powered down

OUTPUT STAGE The gain of the voltage feedback output stage is fixed at 18 dB and inaccessible to the user. Otherwise, it is similar to the preamplifier in speed and bandwidth. The overall −3 dB bandwidth of the preamplifier and DGA combination is 230 MHz.

ATTENUATOR The input resistance of the VGA attenuator is nominally 265 Ω. Assuming that the default preamplifier feedback network of RFB1 and RFB2 is 200 Ω, the effective preamplifier load is about 114 Ω. The attenuator is composed of ten 3.01 dB sections for a total attenuation span of −30.10 dB. Following the attenuator is a fixed gain amplifier with 18 dB (8×) gain. Because of this relatively low gain, the output offset is less than 20 mV over the operating temperature range; the offset is largest at maximum gain because the preamplifier offset is amplified. The VMDO pin defines the common-mode reference for the input and output. The voltage at VMID is half the supply voltage for single-supply operation and 0 V when dual supplies are used.

AD8260 Data Sheet


SINGLE-SUPPLY OPERATION AND AC COUPLING When operating the AD8260 from a single supply, there are two bias options for VMDO.

• Use an external low impedance midpoint reference at Pin VMDO and pull VMDI to VNCM to shut down the VMID buffer.

• Use the internal VMID buffer as shown in Figure 64.

In both cases, decoupling capacitors are needed on Pin VMDO to absorb the dynamic currents.

During single-supply operation, the preamplifier input is normally ac-coupled. An internal bias resistor (nominally 1 k Ω) connected between PRAI and VMDO provides bias to the preamplifier input pin. A 50 Ω resistor connected between Pin PRAI and Pin VMDO, in parallel with the internal 1 kΩ, serves as a termina-tion resistor and at the same time reduces the offset; the result is a composite value of about 48 Ω. The VGA input is biased through the attenuator network and the voltage at Pin VMDO. When active, the VMID buffer provides the needed bias currents. When the buffer is disabled, an external voltage is required at Pin VMDO to provide the bias currents. For example, for a single 5 V application, a reference such as the ADR43 and a stable op amp provide an adequate 2.5 V VMDO source.

POWER-UP/POWER-DOWN SEQUENCE For glitch-free power-up operation, the following power-up and power-down sequence is recommended:

1. Enable the bias by pulling the ENBL pin high. Maintain GNS0 to GNS3 and TXEN at ground.

2. It is assumed that after the part wakes up from sleep mode, the receive section (preamplifier and DGA) needs to be

active first to listen to any signals, and the driver needs to be off. Therefore, the gain code should be set to 0001 (−6 dB of gain) first and then the gain adjusted as needed. Note that any code besides 1 to 11 (binary) disables the receive section (see Table 4). During receive, it is also important that the DAC that provides the signal for the high current driver be disabled to avoid interfering with the received signal.

3. After receive, presumably data needs to be transmitted via the high current driver amplifier. At this point, the DAC should still be off. Pull Pin TXEN high and allow the high current driver to settle. Enable the DAC. Although the preamplifier and DGA can remain enabled during the previous sequence, there may be significant preamplifier overdrive, and it is best that the receiver be disabled while transmitting.

4. Pull Pin ENBL low to disable the chip. To achieve the specified sleep current of 35 μA, all logic pins must be pulled low as well.

LOGIC INTERFACES All logic pins use the same interfaces and, therefore, have the same behavior and thresholds. The interface contains a Schmitt trigger type input with a threshold at about 1.1 V and a hystere-sis of ±0.2 V.

Therefore, the logic low is between ground and 0.8 V, and logic high is from 1.4 V to VPOS. Because the threshold is so low, the logic interfaces can be driven directly from 1.8 V or 3.3 V CMOS.

The input bias current is nominally 0.2 μA when the applied voltage is 3.3 V and 18 nA when grounded.


Data Sheet AD8260


APPLICATIONS INFORMATION The AD8260 is ideally suited for compact applications requiring high frequency and large current drive of complex modulation products. Because the driver is capable of providing up to 300 mA (using a 3.3 V supply rail) to very low impedance loads, undefined network impedances are of little consequence. Such applications can include, but are not limited to, local power line wiring found in homes or in automobiles, or low impedance complex filters used in communications. Pulse response performance with loading effects are illustrated by various curves in the Typical Performance Characteristics section.

Figure 65 is an application block diagram showing AD8260 devices configured as transceivers in a small local network. In this figure, consider a small security system consisting of a master controller and four satellite cameras. For example, the master can be a processor-controlled switch that routes data to and from local satellite cameras. The cameras video signals are modulated for transmission over an existing power system such as the wiring found in homes or small businesses. Using the existing power network in this way eliminates the need to install additional cabling, thereby saving cost. Portability is also achieved because the system can be moved to other locations should the need arise, simply by unplugging a satellite and moving it elsewhere. The AD8260 transceivers perform the same function at the master and slave locations; a high frequency current-output DAC converts digital-to-analog data for the high current driver for transmission over a low impedance load. The input of the VGA/preamplifier connects to the same load, functioning as the receiver. In such a system, multiple AD8260 devices are connected to form a network, much like a LAN, except using the power-line wiring in a home or automobile in lieu of a Cat-5 cable, for example.

LOCAL POWER WIRING

COUPLING

DAC ADC

MICROPROCESSOR +MODULATOR



CONTROLLER

SATELLITECAMERAS

COUPLING

DAC ADC

CAMERA

AD8260

AD8260

AD8260

COUPLING

DAC ADC

CAMERA

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5

Figure 65. AD8260 Transceiver Application

Figure 66 shows the AD8260 as a low distortion, high power driver. The VGA and high current driver are combined by simply connecting the differential output of the VGA directly to the input of the driver.

AD8260

DAC

COMPLEX LOWZ FILTER ≥10Ω

VGA/PREAMPLIFIER

HIGH CURRENTDRIVER

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6

Figure 66. AD8260 Used as a VGA Driving a Low Impedance Load

http://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdf

AD8260 Data Sheet


EVALUATION BOARD Analog Devices provides evaluation boards to customers as a support service so that the circuit designer can become familiar with the device in the most efficient way possible. The AD8260 evaluation board provides a fast, easy, and convenient means to assess the performance of the AD8260 before going through the inconvenience and expense of design and layout of a custom board. The board is shipped fully assembled and tested and provides basic functionality as shipped. Connectors enable the user to connect standard types of lab test equipment without having to wait for the rest of the design to be completed. Figure 67 shows a digital image of the top view and Figure 70 shows the schematic.

PCB artwork for all conductor and silkscreen layers is shown in Figure 71 through Figure 76. A description of a typical test setup is explained in the Connecting the Evaluation Board section. The artwork can be used as a guide in circuit layout and parts placement. This is particularly useful for multiple function circuits with many pins, requiring multiple passive components.

The board is shipped with the device fully enabled. Moving the ENABLE jumper to its upper position on the board disables the device. When the TX_EN jumper is in its upper position, the high current driver is disabled.

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Figure 67. Top View of the AD8260-EVALZ

http://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdf

Data Sheet AD8260


CONNECTING THE EVALUATION BOARD Figure 69 shows an evaluation board with typical test connec-tions. The various pieces of test equipment are representative, and equivalent equipment may be substituted.

The AD8260 includes two amplifier channels: a high current driver and a digitally controlled VGA that is independently enabled. The slide switch labeled ENABLE functions as the chip enable, the GNSx switches permit the preamplifier/VGA to operate, and the TX_EN switch enables the high current driver. These independent enable functions permit the device to operate in a send or listen mode when used as a transceiver.

The high current driver features differential inputs and is optimally driven by a differential signal source. The input signal is monitored at the 2-pin header labeled INP, using a differential probe such as the Tektronix P6247 (not shown). Two 49.9 Ω resistors are provided (R12 and R13), either for terminating coaxial cables from a signal generator or to be used as load resistors for a DAC with a current source output. An optional external load resistor is connected at the SMA connector TXOP and the output signal monitored at the 2-pin header labeled TXOP_1.

As shipped, the gain of the high current driver is 1.5×, its default value. The internal differential network with resistor values of 1 kΩ and 1.5 kΩ establishes this value. Other values of gain are realized by connecting external resistors to the device at Pin 23, Pin 24, Pin 27, Pin 28, and Pin 31, as shown in Figure 68, which shows the internal structure for the default gain and how the gain can be modified.

CCOMP

INPP

INRP

VOCM

TXFBINRN

INPN

TXOP

TXOP

VMDO

1kΩ

1kΩ 1.5kΩ

DEFAULT GAIN SETTINGCOMPONENTS ARE SHOWN IN BLACK,

OPTIONAL COMPONENTSARE SHOWN IN GRAY.

1.5kΩ

+

–

29 27

23

2430

32

1

31

28

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Figure 68. Gain-Setting Resistors of the High Current Driver

The VGA/preamplifier is completely independent of the high current driver and features a single-ended input at the SMA connector PRAI. The input signal is monitored at the header VPRE_IN. The output is monitored at the 2-pin header VGA_OUT.

The gain bits, GNS0 through GNS3, must be set before the VGA/preamplifier can operate. Table 4 lists the binary gain codes. The board is shipped with both enables (ENBL and TXEN) engaged and the gain-code switches adjusted for maximum DGA gain (1011). Resistor R5 and Resistor R6 establish the preamplifier gain and are 100 Ω as shipped for a noninverting preamplifier gain of 2×.


AD8260 Data Sheet


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7

POWER SUPPLY

+ 5 V- 5 V

HIGHCURRENTDRIVEROUTPUT

FUNCTIONGENERATOR FOR VGA

INPUT

HIGHCURRENT

DRIVERINPUTS

VGAOUTPUT

(TO SCOPE)

SINGLE-ENDEDVGA INPUT

RLOAD

PULSE GENERATOR WITHDIFFERENTIAL OUTPUT

Figure 69. Typical Evaluation Board Connections

Data Sheet AD8260


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0

–VS+VS

–VS+VS

INPP

VPSR

GN

S3

GN

S2

GN

S1

GN

S0

PRA

O

INR

P

INR

N

INPN

TXFB

VNEG

U1AD8260

29303132 28 252627VOCM VNEG

VPSB

VGAN

VGAP

ENBL

VNCM

VMDO

TXEN

VMDI

8

7

6

5

1

4

3

2

FDBK

VMDO

PRAI

TXOP

VPOS

VPSR

VPOS

TXOP

20

17

18

19

21

22

23

24

14139 121110 15 16VNGR VNGR

GND4GND3GND2

TXOPR90ΩR70Ω

R210Ω

L7120nH

FB–VS

R14DNI

GND6GND5

GND

C190.1µF

C180.1µF

C80.1µF

C170.1µF

C10.1µF

C20.1µF

C90.1µF

INRP INRN

R1249.9Ω

R1349.9Ω

INR

INP

GND1

C310µF

C410µF+

+

VMDOC14

0.1µF

R200Ω

L4120nHFB

C200.1µF

–VS

R3DNI

+VS

L6120nH

FB

L5120nH

FB

C60.1µF

C70.1µF

C50.1µF

R6100Ω

R5100Ω

PRAI

R1049.9Ω

R11453Ω

C110.1µF

C120.1µF

C210.1µF

VPRE_IN

VPRE_OUT

PRAO

GNS0

GNS1

GNS2

GNS3

HL

R190Ω

C220.1µF

C160.1µF

+VS

L3120nH

FB

L2120nH

FB–VSR4DNI

DIS VMDI

L1120nH

FB

EN

TXENVPSB

TX_EN

C150.1µF

C130.1µFVPSB

VPS

DIS

ENENABLE

VGAN

VGAP

R2453Ω

R1453Ω

VGA _ OUT

ENBL

C230.1µF

C100.1µF

R16DNI

R17DNI

R15DNI

R18DNI

TXOP_1

Figure 70. AD8260 Evaluation Board—Schematic Diagram


AD8260 Data Sheet


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Figure 71. AD8260-EVALZ Component Side Assembly

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Figure 72. AD8260-EVALZ Component Side Copper

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Figure 73. AD8260-EVALZ Secondary Side Copper

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Figure 74. AD8260-EVALZ Power Plane

http://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdfhttp://www.analog.com/AD8260?doc=AD8260.pdf

Data Sheet AD8260


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Figure 75. AD8260-EVALZ Ground Plane

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Figure 76. AD8260-EVALZ Component Side Silkscreen


AD8260 Data Sheet


OUTLINE DIMENSIONS

1

0.50BSC

BOTTOM VIEWTOP VIEW

PIN 1INDICATOR

32

916

17

2425

8

EXPOSEDPAD

PIN 1INDICATOR

SEATINGPLANE

0.05 MAX0.02 NOM

0.20 REF

COPLANARITY0.08

0.300.250.18

5.105.00 SQ4.90

0.800.750.70

FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

0.500.400.30

0.20 MIN

2.852.70 SQ2.55

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-2. 08-2

2-20

13-A

PKG

-004

332

Figure 77. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-21)

Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Package Description Package Option AD8260ACPZ-R7 −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-21 AD8260ACPZ-RL −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-21 AD8260ACPZ-WP −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-21 AD8260-EVALZ Evaluation Board 1 Z = RoHS Compliant Part.

©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07192-0-5/16(B)

http://www.analog.com

FEATURESAPPLICATIONSFUNCTIONAL BLOCK DIAGRAMGENERAL DESCRIPTIONTABLE OF CONTENTSREVISION HISTORYSPECIFICATIONSABSOLUTE MAXIMUM RATINGSESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONSTYPICAL PERFORMANCE CHARACTERISTICSTEST CIRCUITSTHEORY OF OPERATIONOVERVIEWHIGH CURRENT DRIVER AMPLIFIERPRECAUTIONS TO BE OBSERVED DURING HALF-DUPLEX OPERATIONVMID BUFFERPREAMPLIFIERPREAMPLIFIER NOISEDGAGAIN CONTROLOUTPUT STAGEATTENUATORSINGLE-SUPPLY OPERATION AND AC COUPLINGPOWER-UP/POWER-DOWN SEQUENCELOGIC INTERFACES

APPLICATIONS INFORMATIONEVALUATION BOARDCONNECTING THE EVALUATION BOARD

OUTLINE DIMENSIONSORDERING GUIDE

high current driver amplifier and digital vga/preamplifier with 3 … · 2019. 9. 14. · the...

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