High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

A. C. Fischer, S. J. Bleiker, N. Somjit, N. Roxhed, T. Haraldsson, G. Stemme and F. NiklausKTH Royal Institute of Technology

Osquldas väg 10, 100 44 Stockholm, Swedenemail: andreas.fischer@ee.kth.se

Abstract

Three-dimensional (3D) integration is an emerging technol-ogy that vertically interconnects stacked dies of electronics and/orMEMS-based transducers using through silicon vias (TSVs).TSVs enable the realization of devices with shorter signal lengths,smaller packages and lower parasitic capacitances, which can re-sult in higher performance and lower costs of the system. Inthis paper we demonstrate a new manufacturing technology forhigh-aspect ratio (> 8) through silicon metal vias using magneticself-assembly of gold-coated nickel rods inside etched through-silicon-via holes. The presented TSV fabrication technique en-ables through-wafer vias with high aspect ratios and superior elec-trical characteristics. This technique eliminates common issues inTSV fabrication using conventional approaches, such as the metaldeposition and via insulation and hence it has the potential to re-duce significantly the production costs of high-aspect ratio state-of-the-art TSVs for e.g. interposer, MEMS and RF applications.

Introduction

During the past decades, hybrid integration of IC and MEMStechnology has been dominated by 2-D approaches, resulting inMulti-Chip Modules (MCM) where different dies are integratedon a single substrate, and System-on-Chip (SoC) solutions wheredifferent functionalities are merged onto one die. CMOS andMEMS processing are both well-established and cost-efficientbase technologies that are characterized by short developmenttimes, low fabrication costs and high yields. Separate manu-facturing of CMOS integrated circuit dies and MEMS dies andtheir subsequent integration into a System-in-Package (SiP)offers high versatility and low process costs, and thus is anattractive alternative to SoC solutions. Especially 3D-integratedSystem in Package (3D-SiP) solutions, which are based onvertical chip stacking, are a general trend in many integrationapproaches. Not only do 3D-SiPs decrease costs by reducing thevolume and weight of the package, but they also improve systemperformance through enhanced signal transmission speed andlower power consumption which is of importance for variousdemanding applications [1, 2]. This is due primarily to theshorter signal path lengths and lower capacitive, resistive andinductive parasitic components that are enabled by TSVs [3].3D-SiP implementations require vertical interconnects throughselected dies in the stack in order to connect their functionallayers. Large development efforts for the realization of reliableand cost-efficient TSVs are currently ongoing and the firstcommercially available devices such as MEMS inertial sensorsand microphones, CMOS imagers and power LEDs successfullyincorporate TSV technology [4–6].

The structure and hence the fabrication of TSVs can beroughly divided into three major elements: a vertical hole throughthe substrate, a conductive core and a dielectric layer acting as aninsulator between conductor and substrate. The exact design ofthe via and the fabrication process flow depends very much onthe application.

Typical TSV diameters vary between a few microns [2, 7]and several hundreds of microns [8, 9]. Basic via designs areeither based on solid or lined metallizations for the verticalconductor. TSVs can have either straight [7–11] or taperedsidewall profiles [12, 13] as well as combinations of both [1, 14].Various methods for the formation of via holes exist and can becategorized into dry etching [1, 7, 8, 10–14], wet etching [14] anddrilling processes [4]. The majority of TSVs have an aspect ratiobetween 1 and 10. The most common techniques and challengesfor the fabrication of the main TSV structures are discussed inthe following sub-sections.

Via Holes — Deep Reactive Ion Etching (DRIE) is byfar the most commonly used technology to form the TSV hole.DRIE has an excellent process controllability and is capable ofcreating high aspect ratio vias with specific sidewall profiles andtopographies. The etch rate of DRIE is aspect ratio dependent(ARDE) and may cause several topographic imperfections onthe sidewalls such as scalloping, caused by alternating etch-and passivation-steps, which results in corrugated sidewalls.By using state-of-the-art DRIE equipment, these effects canbe minimized [12] and adopted to the demands of subsequentinsulation, barrier and seed-layer deposition steps.Laser ablation is an emerging low-cost and high-speed processfor drilling TSV holes as it benefits from the absence of any litho-graphic process steps and is agnostic to different materials. Thisresults in high process and design flexibility and thus, potentiallylower overall costs compared to DRIE [4, 15]. Laser ablationhowever suffers from a high local thermal load, introduction ofcrystal defects and particle generation around the perimeter of thedrilled via hole. Additional cleaning steps are therefore requiredand reliability issues may arise due to induced stresses on poresand micro-cracks [15, 16].

Via Insulator — Chemical Vapour Deposition (CVD) isa well-established CMOS process with moderate temperaturerequirements [1, 2, 7, 13] and is therefore the most commonlyused method for a direct deposition of silicon dioxide or siliconnitride on the sidewalls of the via holes. The use of organicdielectrics such as Benzocyclobutene (BCB) [9, 13, 17], epoxy-

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based polymers [8, 13], silicone [13] or Parylene [11] is alsoconsidered as viable option. Polymers, especially low-k typeswith a lower relative permittivity compared to silicon dioxide,are very attractive for the realization of TSVs with improvedelectrical characteristics [8]. In addition, polymers can further actas a buffer for thermo-mechanical stresses caused by coefficientof thermal expansion (CTE) mismatches [11, 18] as their Young’smodulus is approximately two orders of magnitude lower ascompared to silicon dioxide or silicon nitride.

Via Conductor — The via metallization step is the most crit-ical and often most costly part of the via fabrication. Establishedprocesses are electrodeposition of copper [7, 8, 11, 13, 14, 18],CVD of tungsten [2, 19], CVD of polysilicon [2, 12] and theuse of low-resistivity silicon [10]. Especially electrodeposition ofcopper, being a very well-established semiconductor process, isused by many research groups and implemented in most commer-cialized devices containing TSVs. Electrodeposition of copperbenefits from widely available tool vendor support and processmaturity as well as being amenable to processing at close to roomtemperature, but suffers due to its complexity in terms of processcontrollability, reliability and throughput [4]. In particular, highaspect ratio TSVs with void-free conductive metal cores are diffi-cult to implement [7]. Alternative approaches to plating processeshave therefore been investigated, such as filling with conductivemetal pastes [1, 20, 21], solder [22, 23] as well as the use of wire-bonded gold [9].

Concept of Self-Assembled TSVs

In this work we present the magnetic self-assembly of con-ductive via cores into through-silicon via holes. Magnetism as anon-contact force enables a controlled manipulation of ferromag-netic features over long-distances and is insensitive to the sur-rounding medium and independent of details of the surface chem-istry. Magnetic fields can have high energy densities and can in-fluence feature sizes from macro- to nano-scale. These advanta-geous characteristics are very attractive and have been reportedin various assembly approaches [24]. A proof-of-concept of self-assembled pure nickel-TSVs has been shown by the authors ear-lier [17]. As depicted in figure 1 a and b, pre-formed ferromag-netic nickel rods are magnetically assembled into deep etched viaholes. For the via insulation the thermosetting polymer Benzo-cyclobutene (BCB) is used, as shown in figure 1 c. This low-kinsulator material has excellent electrical characteristics and canbe filled void-free into trenches with high aspect ratios [25]. Thismethod enables high aspect ratio vias with an inherently void-freeconductor and insulator. This method has also been adopted forthe assembly of SMD capacitors into through-silicon holes [26].

Even though the DC resistances of commonly used conduc-tive materials such as copper, gold, aluminum, or tungsten, arewithin a very close range to those of ferromagnetic materials likecobalt, nickel, or iron, there is an enormous discrepancy regard-ing their performance for high-frequency signal transmission asdepicted in figure 2. Ferromagnetic materials show very poor RF

(a) (b)

Nickel

SiO2

Silicon BCBBeln

(c)

Figure 1: Via formation concept [17]: a) The via hole is formedby DRIE stopping on a silicon dioxide layer. b) A conductive,ferromagnetic nickel core is placed in the via hole by magneticassembly. c) The remaining hollow space in the via cavity is filledwith the thermosetting polymer Benzocyclobutene (BCB).

conductibility characteristics with sheet resistances that are twoorders of magnitude greater than common TSV conductor mate-rials.

0 20 40 60 80 100 12010

−3

10−2

10−1

100

101

102

Frequency [GHz]

Sheet R

esis

tance [Ω

/square

]

Iron

Nickel

Cobalt

Tungsten

Aluminium

Gold

Copper

Figure 2: Simulated sheet resistances for various conductive ma-terials in dependence of the frequency. The values for ferromag-netic materials, such as Iron, Nickel, and Cobalt are almost twoorders of magnitude bigger than the values for Tungsten, Alu-minium, Gold, and Copper.

In this work we present an automated magnetic assembly pro-cess for the fabrication of TSVs that are adopted for the transmis-sion of high frequency RF signals. Two materials are thereforecombined for the conductive via core. Ferromagnetic nickel isused for the assembly process and a gold layer that is coated onthe nickel wire serves as conductor for the RF signal. Due tothe skin-effect the current density of high-frequency signals in a

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conductor is largest close to the surface and hence most of the cur-rent flows along the outer perimeter of a circular TSV conductor.Therefore it is sufficient to coat a thin layer of gold on a nickelcore in order realize a TSV with good electrical characteristicsfor RF signals.

Wire preparation

The conductive cores of the TSVs are fabricated previous tothe assembly. The electric and mechanical quality of the final viaconnection as well as the manufacturability of the wire assemblyis strongly dependent on a thorough preparation of the conductivevia cores. The preparation is divided in two steps, first the coat-ing of a nickel wire with gold by electroplating and second thecutting of the gold-coated nickel wire to a defined length. Crucialrequirements are perfectly straight nickel wires and a very precisecontrol of the gold layer thickness. A too thick gold layer wouldresult in an enlarged diameter of the nickel rods which would thennot fit into the via holes anymore. A distortion of the wires wouldhave a similar effects since the wires would get stuck half wayinto the holes.

In order to ensure a defined fixation and a reliable electri-cal contact of the wire for the electrodeposition process, a carrierframe for the wire was manufactured, as depicted in figure 3 a.The carrier is made of chemically resistant polypropylene (PP)and holds approximately 2.5 m of nickel wire. The wire that wasused for this experiment was Nickel 270 with a purity of 99.97 %and a diameter of 35 µm. Prior to the gold-electroplating step,the native oxide on the surface of nickel wire was removed by a10 % HCl dip. The gold-coating was performed with the elec-troplating agent Aurotron H 200 (Atotech GmbH, Germany) at adeposition rate of approximately 0.3 µm/min.

In order to cut the gold-coated nickel wire into rods of a de-fined length, a wire cutting process was developed. The carrierframe with the gold-coated nickel wires was therefore placed ona carrier wafer. As shown in figure 3 b, the wires were fixatedwith blue tape at the outer perimeter of the carrier wafer beforethe frame and the excess wire was removed. In order to fixate thewires on the carrier wafer and protect them from any deformationand burr creation during the cutting process a layer of AZ R 4562photoresist was spin-coated on the carrier wafer at 1000 rpm for30 s. As depicted in figure 3 c, the nickel wires were fully embed-ded in the photoresist matrix. A DAD 320 (DISCO Cooperation,Japan) wafer dicing tool was used to cut the wires to a length of350 µm. The accurate alignment of the dicing machine allowedfor perfectly perpendicular cuts and the length of the rods couldbe precisely controlled by the step size of the dicing blade. Sub-sequently the gold-coated nickel rods could easily be released bydissolving the resist layer with acetone. Since this process allowsfor a very precise cutting of many wires in parallel, a large num-ber of nickel rods can be manufactured in a short time, e.g. oneprocess run of plating, mounting, cutting and releasing producesapproximately 4000 nickel rods.

TSV Fabrication

The detailed fabrication process for the TSVs is depictedin figure 4 and starts with 350 µm thick double-sided polished,p-type silicon wafers with a diameter of 100 mm and a resistivityof 5000−8500 Ωcm. A 2 µm thick silicon dioxide layer wascreated by thermal wet oxidization at 1100C on both sides. Thesilicon dioxide acts both as a hard mask for the DRIE step andas an electrical insulator for the metal lines, which will finallyconnect the via on the front- and back-side of the substrate. Astandard lithography on the front-side of the substrate defines thecircular openings for the vias. The silicon dioxide is dry-etchedby RIE (figure 4 b). As depicted in figure 4 c, a Bosch DRIEprocess creates via holes with a diameter of 42 µm and straightside walls. The etch stops at the silicon dioxide on the bottom ofthe cavity. A subsequent thermal oxidation ensures an electricalinsulation of the via sidewalls.

As depicted in figure 4 e, an excess amount of the gold-coated nickel wires is then randomly placed on the front-sideof the substrate. By magnetic manipulation with a permanentmagnet from the back-side, the nickel wires are aligned normal tothe surface (figure 4 f). A lateral movement of the magnet dragsthe wires along the surface and forces them into the via cavities(figure 4 g). For this magnetic assembly process a robotic setupwas devised and constructed based on a wafer handler robot.

Wafer

Photo-

resist

Ni

Wire

Dicing

Groove

Blue TapeNi Wire

c)

a) b)

Figure 3: After the gold plating (a), the wires are cut by transfer-ring the nickel wires to a dummy wafer (b). The wafer is then spin-coated with photoresist (c). Embedded in this protective layer ofphotoresist, the wires can be cut with a dicing tool, without therisk of bending or loosing the wires. (c) shows the top and cross-sectional views of a cut nickel wire, still embedded in photoresist.By dissolving the resist layer the wires can then be released.

543

(a) (b) (c)

(e) (g)(f)

Silicon Silicon Oxide

Nickel

BCB

Gold

(j)(i)

(h)

Via

Fo

rma

tio

n

Via

Fillin

g b

y

Ma

gn

etic A

sse

mb

ly

Via

Co

nta

cts

N

S

(d)

(k)

N

S

N

S Magnet

Figure 4: The TSV fabrication in three main steps: (a - d) Formation of via holes by DRIE. (e - h) Autonomous magnetic assembly ofgold-coated nickel TSV cores and the application of BCB as an insulation layer. (i - k) Opening of the vias on back-side as well asdeposition and patterning of the transmission lines.

Figure 5 shows a schematic depiction of the robot arm that wasmodified in order to mount the cubic permanent magnet with anedge length of 5 mm. This device enables a free movement ofthe magnet with three degrees of freedom which can be utilizedto program an assembly motion to drag the nickel wires intothe cavities. Also depicted in figure 5 is a camera which ismounted directly above the magnet and faces the front-side of thesubstrate. It is used to optically inspect the substrate surface andto monitor the assembly process.

x

y

z

Permanent

Magnet

Wires

Robot Arm

Camera

Wafer

Figure 5: Assembly robot setup: The assembly arm consists of apermanent magnet mounted on an aluminum sheet and a cameraabove the magnet.

The via cavities are subsequently filled with the thermoset-ting polymer BCB CYCLOTENE R 3022-46 (figure 4 g). Inorder to reduce the viscosity of the polymer, the substrate isplaced on a hotplate with a temperature of 60C before thepolymer is manually applied with a syringe. As the polymer isnot spin-coated the resulting polymer layer has a non-uniformthickness on the order of 100−150 µm. The subsequenthard-curing of the BCB is performed on a hotplate using thetemperature profile according to the manufacturer’s standardprocess procedures [27]. The curing procedure was performed ina vacuum environment at 0.02 mbar in order to prevent any voidformation in the polymer. A grinding and polishing step removesremaining nickel and BCB from the surface of the substrate(figure 4 i). A subsequent lithography and RIE of the silicondioxide and BCB residues opens the contact area of the via on theback-side of the wafer, as depicted in figure 4 j. Two consecutiveTiW / Au depositions (50 / 500 nm) on both sides of the waferinterconnects the nickel/gold core of the via. A lithography,wet Au etch and dry TiW etch define the transmission lines(figure 4 k) of the RF test structures.

Experimental Results

Figure 6 shows a scanning electron microscope (SEM) imageof a gold-coated nickel wire. In order to evaluate the thickness ofthe electroplated gold layer, a small pit was formed on the wiresurface by focused ion beam (FIB) milling. The gold thicknesswas measured to be 1.7 µm. The surface of the gold film has arough surface, which is characteristic for electro-deposited layers.

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Gold Nickel

Au-coated Ni wire

Figure 6: SEM image of a gold-coated nickel wire. Inset: Cross-section of the Ni/Au interface, generated by focused ion beam(FIB) milling.

A first unsuccessful fabrication run of non-functional TSVswas investigated by cross-section grinding and subsequent inspec-tion with a scanning electron microscope (SEM). As depicted inFigure 7, the lower part of the conductive via core is not in contactwith the metallization on the back-side. The failure was caused bythe DRIE that produced a slightly closing profile of the via side-walls. As a result, the diameter of the lower part of the via wassmaller than the diameter of the gold-coated nickel rods. This pre-vented the conductive via core from a complete assembly down tothe silicon oxide membrane. This issue was addressed by an in-creased etch time and subsequent fabrication runs were success-ful. Figure 7 indicates that the filling with BCB could be success-fully conducted without any visible air-voids or defects after thecomplete hard curing procedure. Also, the nickel wire is inher-ently void-free.

Au

SiO2

BCB

Au

Ni

SiO2

Au

Figure 7: SEM image of a cross section of a TSV with an aspectratio of 8. It shows both, a void-free via core and a void-freeBCB-filling.

For evaluating the RF performance of the gold-coatednickel wire TSV, the proposed via structures are employed asvertical through-wafer interconnections of the micromachinedcoplanar-waveguide (CPW) transmission lines implemented onthe front- and back-side of a high-resistivity silicon substrate(5000-8500 Ωcm) as shown in figure 8. The gold CPW has asignal line width of 120 µm and a gap of 60 µm, while the lengthof the transmission is 2400 µm, thus the unwanted signal cou-pling between the input and output port is avoided. To extractthe transmission loss from the test structure, a reference CPWtransmission line without any interconnections was fabricated onthe front-side of the wafer. The RF measurement results indi-cate that the CPW integrated with gold-coated nickel wire inter-connections offers an excellent RF performance for a very wideband from DC to 66 GHz, which is a much larger operation fre-quencies as compared to other reported TSVs for RF applica-tions [8, 28, 29]. The measured maximum return loss at 66 GHzis lower than −10 dB, while the maximum insertion loss is betterthan −4.62 dB. As compared to the reference CPW transmissionwith the same length, a single section of the gold-coated nickelwire interconnection has an insertion loss of only −0.75 dB.

Si

Front-Side Back-Side TSV

SiO2 Au

Ni

BCB

Signal Trace

Ground

Trace

a)

b)

Figure 8: Cross section (a) and top-view (b) of the micromachinedcoplanar-waveguide (CPW).

Conclusions

We demonstrated a novel manufacturing technology for high-aspect ratio (> 8) through silicon metal vias based on the magneticself-assembly of gold-coated nickel wires. The presented TSVapproach offers an excellent RF performance up to 66 GHz.

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Acknowledgements

This work has been funded by the European Research Coun-cil (ERC) through the Starting Grant (277879). The authors alsowould like to thank Umer Shah and Nora Heinig for their collab-oration and technical support.

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