High Abstraction ModelingHigh Abstraction Modeling

Rafi Spigelman - IntelRafi Spigelman - Intel

High Level ModelsHigh Level Models Should describe & model the Arch and the uArch Should describe & model the Arch and the uArch

“from 20000 feet”“from 20000 feet” Fast & Lean. Should Include only what’s required for Fast & Lean. Should Include only what’s required for

Arch & uArch “concept” exploration and validationArch & uArch “concept” exploration and validation

Can be used for early validation of Arch & uArch Can be used for early validation of Arch & uArch concepts and configurations.concepts and configurations. Performance, Functionality, Formal Property Performance, Functionality, Formal Property

validationvalidation Building verification infrastructureBuilding verification infrastructure

HLM is for architects. It can be later used as a HLM is for architects. It can be later used as a reference model for RTL reference model for RTL

Can HLM replace RTLCan HLM replace RTL Nop – HLM is not detailed enoughNop – HLM is not detailed enough

Make it as detailed as RTL and you get an RTL…Make it as detailed as RTL and you get an RTL…

We need RTL details for the designWe need RTL details for the design The gap between HLM and gate level netlist is too The gap between HLM and gate level netlist is too

high (for both practical manual and synthesis design)high (for both practical manual and synthesis design) RTL is “just right”RTL is “just right”

We need RTL models for functional silicon We need RTL models for functional silicon debug and for functional production testingdebug and for functional production testing Gate Level simulations too slow and “too detailed” for Gate Level simulations too slow and “too detailed” for

efficient debugefficient debug HLM models are not detailed enoughHLM models are not detailed enough