hierarchical t est approaches for digital systems
DESCRIPTION
Hierarchical T est Approaches for Digital Systems. REASON Autumn School Sinaia, Romania, Oktober 9, 2004. Raimund Ubar Tallinn Technical University D&T Laboratory Estonia. Abstract. H ow to improve the testing quality at increasing complexities of today's systems? - PowerPoint PPT PresentationTRANSCRIPT
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
1
Raimund Ubar
Tallinn Technical UniversityD&T Laboratory
Estonia
Hierarchical Test Approaches for Digital Systems
REASON Autumn School Sinaia, Romania, Oktober 9, 2004
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
2
Abstract
• How to improve the testing quality at increasing complexities of today's systems?
• Two main trends: defect-oriented test and high-level modelling – Both are caused by the increasing complexities of systems based on deep-
submicron technologies
• The complexity problems in testing digital systems are handled by raising the abstraction levels from gate to register-transfer level (RTL) instruction set architecture (ISA) or behavioral levels
• To handle defects in circuits implemented in deep-submicron technologies, new fault models and defect-oriented test methods should be used
• Trends to high-level modelling and defect-orientation are opposite • As a promising compromise and solution is: to combine hierarchical
approach with defect orientation • Decision Diagrams serve as a good tool for hierarchical modelling of
defects in digital systems
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Outline
• Introduction to Digital Test• How to improve test quality at increasing complexity of
systems• High-level modelling and defect-orientation• Decision Diagrams - beyond BDDs • Hierarchical test generation
– General concepts
– Test generation for RT Level systems
– Test generation for Microprocessors
• Hierarchical fault simulation• Overview of tools developed at D&T Lab
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
4
Introduction: Quality Policy
Quality policyYield (Y)
P,n
Defect level (DL)
Pa
Design for testability
TestingP - probability of a defectn - number of defectsPa - probability of accepting a bad product
nPY )1( - probability of producing a good product
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Introduction: Defect Level
DL
T(%)
Y
1000
1 Y(%)
T(%)10
10
50
90
50 90
8 5 1
45 25 5
81 45 9
)1(1 TYDL
DL T
Paradox: Testability DL
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Introduction: the Problem is Money?
Cost oftesting
Quality
Cost of qualityCost
Cost ofthe fault
100%0% Optimumtest / quality
How to succeed? Try too hard!How to fail? Try too hard!(From American Wisdom)
Conclusion:
“The problem of testingcan only be containednot solved” T.Williams
Test coverage function
Time
100%
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Introduction
Paradox 1:Digital world is finite, analog world is infinite.
However, the complexity problemwas introduced by Digital World
Paradox 2:If I can show that the system works,then it should be not faulty.But, what does it mean: it works?
32-bit accumulator has 264 functions which all should work.
So, you should test all the 264 functions !
All life is an experiment.The more experiments you make,the better (American Wisdom)
System
Stimuli
Y
Response
X
Y
X
Analog case
(samples)
Digital case (“continuous”)
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Introduction: How Much to Test?
Paradox:264 input patterns (!) for 32-bit accumulator will be not enough.
A short will change the circuit into sequential one,and you will need because of that 265 input patterns
Paradox:Mathematicians counted that Intel 8080
needed for exhaustive testing 37 (!) yearsManufacturer did it by 10 secondsMajority of functions will never activated during the lifetime of the system
Time can be your best friendor your worst enemy (Ray Charles)
& &x1
x2
x3
yState q
Y = F(x1, x2, x3,q)
*1
1
Y = F(x1, x2, x3)Bridging fault
0
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Two Approaches to Testing
Testing of functions:12
n
Combinational circuit
under test
Truth table:
Patterns
00…000 00…001 00…010
…
11…111
Functions
01 01 01…101 00 11 00…011 00 00 11…111
…
00 00 00…111
22nn
1
1 22nn22
Number of patterns
Number of functions
22nn-122tested
50%!
0%
Faulty functions
covered by 1.
pattern
Faulty functions
covered by 2. pattern
50%
75%3. pattern
4. pat. 87,5%
93,75%
100%
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Two Approaches to Testing
Testing of structural faults: 12
n
Combinational circuit
under test
Fault coverage
100%
Number of patterns
4
4. pat.
Not tested faults
Faults covered by
1. pattern
2. pattern
3. patttern
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Two Approaches to Testing
Testing of functions:
100% will be reached only after 2n test patterns
Testing of faults:
100% will be reached when all faults from the fault list are covered
0%
Faulty functions
covered by 1.
pattern
Faulty functions
covered by 2. pattern
50%
75%3. pattern
4. pat. 87,5%
93,75%
100%
100%
Testing of faults
Testing of functions
4. pat.
Not tested faults
Faults covered by
1. pattern
2. pattern
3. patttern
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Introduction: Hierarchy
Paradox:
To generate a test for a block in a system,
the computer needed 2 days and 2 nights
An engineer
did it by hand with 15 minutes
So, why computers?
The best place to start iswith a good title.Then builda song around it. (Wisdom of country music)
System
16 bit counter
&
1Sequence
of 216 bits
Sea of gates
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Outline
• Introduction to Digital Test
• How to improve test quality at increasing complexity of systems
• High-level modelling and defect-orientation• Decision Diagrams (beyond BDDs)• Hierarchical test generation
– General concepts– Test generation for RT Level systems– Test generation for Microprocessors
• Hierarchical fault simulation• Overview of tools developed at D&T Lab
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Complexity vs. QualityProblems:• Traditional low-level test generation and fault simulation methods and tools for digital systems have lost
their importance because of the complexity reasons
• Traditional Stuck-at Fault (SAF) model does not quarantee the quality for deep-submicron technologies
New solutions:• The complexity can be reduced by raising the abstraction levels from gate to RTL, ISA, and behavioral
levels– But this moves us even more away from the real life of defects (!)
• To handle adequately defects in deep-submicron technologies, new fault models and defect-oriented test generation methods should be used
– But, this is increasing even more the complexity (!)
• To get out from the deadlock, these two opposite trends should be combined into hierarchical approaches
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fault and defect modeling
Defects, errors and faults• An instance of an incorrect
operation of the system being tested is referred to as an error
• The causes of the observed errors may be design errors or physical faults - defects
• Physical faults do not allow a direct mathematical treatment of testing and diagnosis
• The solution is to deal with fault models
System
Component
Defect
Error
Fault
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Transistor Level Faults
Stuck-at-1Broken (change of the function)BridgingStuck-open New StateStuck-on (change of the function)
Short (change of the function)
Stuck-off (change of the function)
Stuck-at-0
SAF-model is not able to cover all the transistor level defects
How to model transistor defects ?
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Mapping Transistor Faults to Logic Level
Shortx1
x2
x3
x4
x5
y
)()(* dydyy d
))(( 53241 xxxxxyd 54321 xxxxxy
Generic function with defect:
Function:
Faulty function:
A transistor fault causes a change in a logic function not representable by SAF model
Defect variable: d =0 – defect d is missing
1 – defect d is present
Mapping the physical defect onto the logic level by solving the equation:
1*
d
y
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Mapping Transistor Faults to Logic Level
Shortx1
x2
x3
x4
x5
y )()(* dydyy d
))(( 53241 xxxxxyd 54321 xxxxxy
Test calculation by Boolean derivative:
1
))(()(*
5432154315421
5324154321
xxxxxxxxxxxxx
d
dxxxxxdxxxxx
d
y
Generic function with defect:
Function:
Faulty function:
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Functional Fault vs. Stuck-at Fault
NoFull SAF-Test Test for the defect
x1 x2 x3 x4 x5 x1 x2 x3 x4 x5
1 1 1 1 0 - 1 0 - 0 1
2 0 - - 1 1 1 - 0 0 1
3 0 1 1 0 1 0 1 1 1 0
4 1 0 1 1 0
5 1 1 0 0 -
Full 100% Stuck-at-Fault-Test is not able to detect the short:
54321 xxxxxy
The full SAF test is not covering any of the patterns able to detect the given transistor defect
))(( 53241 xxxxxyd
Functional fault
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Defect coverage for 100% Stuck-at Test
Results:
• the difference between stuck-at fault and physical defect coverages reduces when the complexity of the circuit increases (C2 is more complex than C1)
• the difference between stuck-at fault and physical defect coverages is higher when the defect probabilities are taken into account compared to the traditional method where all faults are assumed to have the same probability
Probabilisticdefect
coverage, %
Denumerabledefect coverage,
%
Circuit
Tmin Tmax Tmin Tmax
C1 66,68 72,01 81,00 83,00
C2 70,99 77,05 84,29 84,76
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Generalization: Functional Fault Model
Constraints calculation:
yComponent F(x1,x2,…,xn)
Defect
Wd
Component with defect:
Logical constraints
dn dFFddxxxFy ),,...,,(** 21
Fault-free Faulty
1*
d
yW d
Fault model: (dy,Wd), (dy,{Wk
d})
Constraints:
d = 1, if the defect is present
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Fault Table: Mapping Defects to Faults
Input patterns tji Fault di Erroneous function f di pi
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 B/C not((B*C)*(A+D)) 0.010307065 1 1 1 1
2 B/D not((B*D)*(A+C)) 0.000858922 1 1 1 1
3 B/N9 B*(not(A)) 0.043375564 1 1 1 1 1 1 1
4 B/Q B*(not(C*D)) 0.007515568 1 1 1 1 1 1 1 1 1
5 B/VDD not(A+(C*D)) 0.001717844 1 1 1
6 B/VSS not(C*D) 0.035645265 1 1 1
7 A/C not((A*C)*(B+D)) 0.098990767 1 1 1 1
8 A/D not((A*D)*(B+C)) 0.013098561 1 1 1 1
9 A/N9 A*(not(B)) 0.038651492 1 1 1 1 1 1 1
10 A/Q A*(not(C*D)) 0.025982392 1 1 1 1 1 1 1 1 1
11 A/VDD not(B+(C*D)) 0.000214731 1 1 1
12 C/N9 not(A+B+D)+(C*(not((A*B)+D))) 0.020399399 1 1 1 1 1
13 C/Q C*(not(A*B)) 0.033927421 1 1 1 1 1 1 1 1 1
14 C/VSS not(A*B) 0.005153532 1 1 1
15 D/N9 not(A+B+C)+(D*(not((A*B)+C))) 0.007730298 1 1 1 1 1
16 D/Q D*(not(A*B)) 0.149452437 1 1 1 1 1 1 1 1 1
17 N9/Q not((A*B)+(B*C*D)+(A*C*D)) 0.143654713 1
18 N9/VDD not((C*D)+(A*B*D)+(A*B*C)) 0.253382006 1
19 Q/VDD SA1 at Q 0.014386944 1 1 1 1 1 1 1
20 Q/VSS SA0 at Q 0.095555078 1 1 1 1 1 1 1 1 1
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Functional Fault Model for Stuck-ON
Stuck-on
x1 x2
Y
VDD
VSS
x1
x2
NOR gate
Conducting path for “10”
)( NP
NDDY RR
RVV
RN
RP
dZxxxx
Zxxxxdxxdy
2121
212121 )()(*
1/* 21 ZxxdyW d
x1 x2 y yd
0 0 1 1
0 1 0 0
1 0 0 Z: VY
1 1 0 0
Condition of the fault potential detecting:
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Functional Fault Model for Stuck-Open
Stuck-off (open)
x1 x2
Y
VDD
VSS
x2
NOR gate
No conducting path from VDD to VSS for “10”
x1
Test sequence is needed: 00,10
x1 x2 y yd
0 0 1 1
0 1 0 0
1 0 0 Y’
1 1 0 0
)'(
)'()(*
12
212121
dyxx
yxxxxdxxdy
1'/* 21 yxxdyW d
t x1 x2 y1 0 0 1
2 1 0 1
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Functional Fault Model
Example:
Bridging fault between leads xk and xl
The condition means that
in order to detect the short between leads xk and xl on the lead xk we have to assign to xk the value 1 and to xl the value 0.
lkkd
lkkd
kkk
xxdxW
xxdxdxdxdx
/*
)()()()(*
1 lkd xxW
xk
xl
x*k
d
Wired-AND model
xk*= f(xk,xl,d)
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Functional Fault Model
Example:
x1
x2
x3
y&&
x1
x2 x3
y&&
&
321
321321
)'(
)'()(*
xydxx
xyxxdxxxdy
Equivalent faulty circuit:
Bridging fault causes a feedback loop:
1'/* 321 yxxxdyW d
Sequential constraints:
A short between leads xk and xl changes the combinational circuit into sequential one
t x1 x2 x3 y
1 0 1 02 1 1 1 1
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First Step to Quality
How to improve the test quality at the increasing complexity of systems?
First step to solution:Functional fault model
was introduced
as a means
for mapping physical defects
from the transistor or layout level
to the logic level
System
Component Low level
kWFk
WSk
Environment
Bridging fault
Mapping
Mapping
High level
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Outline
• Introduction to Digital Test
• How to improve test quality at increasing complexity of systems
• High-level modelling and defect-orientation
• Decision Diagrams (beyond BDDs)
• Hierarchical test generation – General concepts– Test generation for RT Level systems– Test generation for Microprocessors
• Hierarchical fault simulation
• Overview of tools developed at D&T Lab
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
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Register Level Fault Models
K: (If T,C) RD F(RS1, RS2, … RSm), NRTL statement:
K - labelT - timing conditionC - logical conditionRD - destination register
RS - source register
F - operation (microoperation) - data transfer N - jump to the next statement
Components (variables) of the statement:
RT level faults:
K K’ - label faultsT T’ - timing faultsC C’ - logical condition faultsRD RD - register decoding faults
RS RS - data storage faults
F F’ - operation decoding faults - data transfer faults N - control faults(F) (F)’ - data manipulation faults
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Fault Models for High-Level Components
Decoder:- instead of correct line, incorrect is activated
- in addition to correct line, additional line is activated
- no lines are activated
Multiplexer (n inputs log2 n control lines):
- stuck-at - 0 (1) on inputs
- another input (instead of, additional)
- value, followed by its complement
- value, followed by its complement on a line whose address differs in 1 bit
Memory fault models:- one or more cells stuck-at - 0 (1)
- two or more cells coupled
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Fault models and Tests
Dedicated functional fault model for multiplexer:– stuck-at-0 (1) on inputs,
– another input (instead of, additional)
– value, followed by its complement
– value, followed by its complement on a line whose address differs in one bit
Functional fault model
Test description
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Faults and Test Generation Hierarchy
Circuit
Module
System
Networkof gates
Gate
Functionalapproach
Fki Test
Fk Test
WFki
WSki
F Test
WFk
WSk
Structuralapproach
Networkof modules
Wdki
Interpretation of WFk:
- as a test on the lower level
- as a functional fault on the higher level
Higher Level Module
Component Lower level
kiWFki
WSki
Environment
Bridging fault
k
WFk
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Physicaldefect
analysis
Defect
Complex gate
Gate-level fault analysis
Module
System
Functionalfault
detected
High-levelfault analysis
High-levelsimulation
Gate-level simulation
YyMyGd
Functional fault activated
Hierarchical Defect-Oriented Test Analysis
BDDsDDs
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34
Outline
• Introduction to Digital Test• How to improve test quality at increasing complexity of
systems• High-level modelling and defect-orientation
• Decision Diagrams (beyond BDDs)• Hierarchical test generation
– General concepts– Test generation for RT Level systems– Test generation for Microprocessors
• Hierarchical fault simulation• Overview of tools developed at D&T Lab
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
35
Binary Decision Diagrams
x1
x2
y
x3
x4 x5
x6 x7
0
1
7654321 )( xxxxxxxy Simulation:
7654321 xxxxxxx0 1 1 0 1 0 0
1y
Boolean derivative:
15427613
xxxxxxx
y
1
0
Functional BDD
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Elementary Binary Decision Diagrams
Elementary BDDs:
1
x1x2x3
y x1 x2 x3&
x2x3
y x1
x1
x2
x3
1x1x2x3
y x1 x2 x3
+x1x2x3
y
x1
x2
x3
y x2 x3
Adder
NOR
AND
OR
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Building a SSBDD for a Circuit
&
1
1x1
x2
x3
x21
x22y
a
b
))((& 322211 xxxxbay
a by
a x1
x21
b x22
x3
ay x22
x3
y x22
x3
x1
x21
DD-library:
Superposition of DDs
Superposition of Boolean functions:
Given circuit:
Compare to
SSBDD
Structurally Synthesized BDDs:
b a
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Representing by SSBDD a Circuit
&
&
&
&
&
&
&
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Macro
6 73
1
2
5
7271
y
0
1
y = cyey = cy ey = x6,e,yx73,e,y deybey
y = x6x73 ( x1 x2 x71) ( x5 x72)
Structurally synthesized BDDfor a subcircuit (macro)
To each node of the SSBDD a signal path in the circuit corresponds
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Fault modeling on SSBDDs
The nodes represent signal paths through gates
Two possible faults of a DD-node represent all the stuck-at faults along the signal path
&
&
&
&
&
&
&
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Macro
6 73
1
2
5
7271
y
0
1
Test pattern:
1 2 3 4 5 6 7 y
1 1 0 0 1 1
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High-Level Decision Diagrams
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
y4
y3 y1 R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
Superposition of High-Level DDs:
A single DD for a subcircuit
R2
R2 + M3
Instead of simulating all the components in the circuit, only a single path in the DD should be traced
M1
M2
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High-Level Decision Diagrams
ABC
M
ADR
MUX1
MUX2
CC
COND
Control Path
Data Path
/
FF
yx
z
z1
z2
A digital system:A
01
0q
xA
B + C
A + 1
13 xC C + B
04 xA A + B+ C
B
04
1q
xA
B + C
B
C
14
2q
xA
1
0xB A + B
C
0 xC
xA1
xC3 0
3,4
02
q
1
01
0q 1
4xA
2
1
5xB
3System is partitioned into 4 subcircuits, each represented by a DD
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High-Level DDs
Digital system:A
01
0q
xA
B + C
A + 1
13 xC C + B
04 xA A + B+ C
B
04
1q
xA
B + C
B
C
14
2q
xA
1
0xB A + B
C
0 xC
xA1
xC3 0
3,4
02
q
1
01
0q 1
4xA
2
1
5xB
3
Begin
A = B + C
xA
A = A + 1 B = B + C
xA
B = B C = C
xB
C = C
xC
A = A +B + C
xC
C = A + B A = C + B
END
0
0
0
0
0
1
1
1
1
1
s0
s1
s2
s3
s4
s5
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High-Level Vector Decision Diagrams
3,4
02
q
1
01
0q 1
4xA
2
15xB
3
A01
0q
xA
B + CA + 1
13 xC C + B04 xA A + B+ C
B04
1q
xA
B + C
B
C
14
2q
xA
10xB A + B
C
0 xC
xA1
xC3 0
M=A.B.C.q
1
1
q
xA
0qA
i B’ + C’
#1
qB
i B’ + C’
#2
0qA
i A’ + 1
#4
2
1
xB
qC
i C’
#3
0qC
i A’ + B’
#5
3
1
xC
qA
i B’ + C’
#5
0qC
i A’ + B’
#5
4
1
xC
qC
i C’
#5
0
B
Ai A’ + B’+C’xA
0
q#5
B’
qB
i B’
#5
A system of 4 DDs Vector DD
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Fault Modeling on High Level DDs
High-level DDs (RT-level):
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
y4
y3 y1 R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
Terminal nodes represent:
RTL-statement faults: data storage, data transfer, data manipulation faults
Nonterminal nodes represent:
RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding,control faults
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45
Two trends:
• high-level modeling– to cope with
complexity• low-level
modeling– to cope with
physical defects, to reach higher acuracy
Hierarchical Diagnostic Modeling
Physicaldefect
analysis
Defect
Complex gate
Gate-level fault analysis
Module
System
Functionalfault
detected
High-levelfault analysis
High-levelsimulation
Gate-level simulation
YyMyGd
Functional fault activated
Boolean differential algebraBDD-s
High-Level DD-s
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
46
Outline
• Introduction to Digital Test• How to improve test quality at increasing complexity of
systems• High-level modelling and defect-orientation• Decision Diagrams (beyond BDDs)
• Hierarchical test generation – General concepts
– Test generation for RT Level systems
– Test generation for Microprocessors
• Hierarchical fault simulation• Overview of tools developed at D&T Lab
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Hierarchical Test Generation
• In high-level symbolic test generation the test properties of components are often described in form of fault-propagation modes
• These modes will usually contain:– a list of control signals such that the data on input lines is reproduced
without logic transformation at the output lines - I-path, or
– a list of control signals that provide one-to-one mapping between data inputs
and data outputs - F-path • The I-paths and F-paths constitute connections for propagating test
vectors from input ports (or any controllable points) to the inputs of the Module Under Test (MUT) and to propagate the test response to an output port (or any observable points)
• In the hierarchical approach, top-down and bottom-up strategies can be distinguished
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Hierarchical Test Generation Approaches
A
B
C
D
a
D
c
A = ax D: B = bx C = cx
A
B
C
D’
a’x
d’x
c’x
A = a’xD’ = d’xC = c’x
a,c,D fixedx - free
a’
c’
a
Bottom-up approach: Top-down approach:
a’,c’,D’ fixedx - free
System System
Module Modulec
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Hierarchical Test Generation Approaches
Bottom-up approach: • Pre-calculated tests for components
generated on low-level will be assembled at a higher level
• It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing
• However, the bottom-up algorithms ignore the incompleteness problem
• The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test
• The approach would work well only if the the corresponding testability demands were fulfilled
A
B
C
D
a
D
c
A = ax D: B = bx C = cx
a,c,D fixedx - free
aSystem
Modulec
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Hierarchical Test Generation Approaches
• Top-down approach has been proposed to solve the test generation problem by deriving environmental constraints for low-level solutions.
• This method is more flexible since it does not narrow the search for the global test solution to pregenerated patterns for the system modules
• However the method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied
Top-down approach: A
B
C
D’
a’x
d’x
c’x
A = a’xD’ = d’xC = c’x
a’
c’
a’,c’,D’ fixedx - free
System
Module
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Hierarchical Test Generation with DDs
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
y4
y3 y1 R1 + R2
IN + R2
R1 * R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
Single path activation in a single DDData function R1* R2 is testedData path
Decision Diagram
Hierarhical test generation with DDs: Scanning test (defect-oriented)
Control: y1 y2 y3 y4 = x032
Data: For all specified pairs of (R1, R2)
Test program:
Low level test data (constraints W)
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Test Generation with High Level DDs
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
y4
y3 y1 R1 + R2
IN + R2
R1 * R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
Multiple paths activation in a single DDControl function y3 is tested
Data path
Decision Diagram
High-level test generation with DDs: Conformity test (High-level faults)
Control: For D = 0,1,2,3: y1 y2 y3 y4 = 00D2
Data: Solution of R1+ R2 IN R1 R1* R2
Test program:Activating high-level faults:
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Gate-level Test Generation
Structural gate-level testing:
Path activation
&
&
&
&
&
&
&
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Macro
DDD
D D
11
1
1
Fault sensitisation:
x7,1= DFault propagation:
x2 = 1, x1 = 1, b = 1, c = 1
Line justification:
x7= D = 0: x3 = 1, x4 = 1
b = 1: (already justified)
c = 1: (already justified)
1))(( 721212,753,761,7
xxxxxxxxxx
y
))(( 2,751,7213,76 xxxxxxxy Symbolic fault modeling:D = 0 - if fault is missingD = 1 - if fault is present
11
11
Test pattern
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Defect-Oriented Test Generation
Test generation for a bridging fault:
&
&
&
&
&
&
&
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Macro
DDD
D D
11
1
1
Fault manifestation:
Wd = x6x7= 1: x6 = 0, x7 = 1,
x7 = DFault propagation:
x2 = 1, x1 = 1, b = 1, c = 1
Line justification:
b = 1: x5 = 0
1
)())((
76521
76212,753,761,7
xxxxx
xxxxxxxxWx
y d
yComponent
F(x1,x2,…,xn)
Defect Wd
Activate a path
Bridge between leads 73 and 6
Wd
0
1
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Test Generation with SSBDDs
&
&
&
&
&
&
&
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Macro
6 73
1
2
5
7271
y
0
1
Test pattern for the node 71 at the constraint
Wd = x6x7= 1: 1 2 3 4 5 6 7 y
1 1 0 0 1 1
Defect: dx7 =1: x7=0
No fault: dx7 =0: x7=1
Defect Wd manifestation:
Wd = x6x7= 1: x6 = 0, x7 = 1, x7 = D
Functional Fault dx7 propagation:
x1 = 1, x2 = 1, x5 = 0
Bridge between leads 7 and 6: (dx7,Wd)
(dx7,Wd)
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Test Generation for RTL Digital Systems
y3 0
C R’2
C
y2
2A
2R’2
y1
R’1
R’3 B
F(B,R’3)
A
A
A R’1
0
0
0
R’2
Y,R3 R20
1 1
0
0
22
0
3
R1
C
R’1
R’1
1
0
0
1
02
01
0 1
1
C+R’2
R’3 R’2
R’1
+ R3
R2
F R1
A
BC
Y
y2
A
y3
y1 s
System model Data path
Control pathq’ 1001q y1 y2 y3
4200
1
2
0
R’2=01
0#2120
3021
4211
0112
3
4
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Test Generation for RTL Digital Systems
y3 0
C R’2
C
y2
A
2R’2
y1
R’1
R’3 B
F(B,R’3)
A
A
AR’1
0
0
0
R’2
Y,R3 R2
0
1 1
0
0
2
3
R1
C
R’1
R’1
1
0
0
1
02
01
0 1
1
C+R’2
R’3 R’2
R’1
Transparency functions on Decision Diagrams:
Y = C y3 = 2, R3’ = 0C - to be testedR1 = B y1 = 2, R3’ = 0R1 - to be justified
+ R3
R2
F R1
A
BC
Y
y2
A
y3
y1 s
High-level path activation on DDs0
2
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Test Generation for RTL Digital Systems
Test generation steps:
• Fault manifestation• Fault-effect propagation• Constraints justification
y3 =2
R’ 2 =0
y2 = 0
0 R 3 = D
A R’ 1
A = D 1
R’ 1 = D 2 B = D 2
R’3
=0
y1
=2
y3
= 0
0
C = D
q’=4
Fault manifestation
q’=2 q’=1 q’=0
R’2
= 0 y2
= 0
q’=1
q’=2
Constraints justification
Faultpropagation
t t-1 t-2 t-3Time:
0
+ R3
R2
F R1
A
BC
Y
y2
A
y3
y1 s
High-level test generation for data-path (example):
DD1
D2
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Test Generation for RTL Digital Systems
Test generation step:
• Fault-effect propagation
y3 = 2
R’2 = 0
y2 = 0
0 R 3 =D
A R’ 1
A =D 1
R’ 1 =D 2 B =D 2
R’3
= 0
y1
= 2y
3 = 0
0
C =D
q’=4
Fault manifestation
q’=2 q’=1 q’=0
R’2
= 0 y2
= 0
q’=1
q’=2
Constraints justification
Faultpropagation
t t-1 t-2 t-3Time:
0
+ R3
R2
F R1
A
BC
Y
y2
A
y3
y1 s
y3 0
C R’2
CR’2
Y,R3
1
0
0
2
0
C+R’2
R’3
q’ 1001
q y1 y2 y3
4200
1
2
0
R’2=01
0#2120
3021
4211
0112
3
4
D
D
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Test Generation for RTL Digital Systems
y3 0
C R’2
CR’2
Y,R30
1
0
0
2
0
y1
R’1
R’3 B
F(B,R’3)
0R1
1
02
0
C+R’2
R’3y2
2A
2R’2
0R20
1
2
3
R’2
Path activation procedures on DDs:
y3 =2
R’ 2 =0
y2 = 0
0 R 3 =D
A R’ 1
A =D 1
R’ 1 =D 2 B =D 2
R’3
=0
y1
=2
y3
= 0
0
C =D
q’=4
Fault manifestation
q’=2 q’=1 q’=0
R’2
= 0 y2
= 0
q’=1
q’=2
Constraints justification
Faultpropagation
t t-1 t-2 t-3Time:
0 q’ 1001q y1 y2 y3
4200
1
2
0
R’2=01
0#2120
3021
4211
0112
3
4
Test generation step: • Line justification Time: t-1
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Test Generation for RTL Digital Systems
t q’ y1 y2 y3 A B C R1 R2 R3 Y
1 0 0 0 1 0
2 1 1 2 0 0
3 2 2 0 0 D2 D2 0
4 4 1 1 2 D1 D D D
Symbolic test sequence:
y3 =2
R’ 2 =0
y2 = 0
0 R 3 =D
A R’ 1
A =D 1
R’ 1 =D 2 B =D 2
R’3
=0
y1
=2
y3
= 0
0
C =D
q’=4
Fault manifestation
q’=2 q’=1 q’=0
R’2
= 0 y2
= 0
q’=1
q’=2
Constraints justification
Faultpropagation
t t-1 t-2 t-3Time:
0
High-level test generation example:
+ R3
R2
F R1
A
BC
Y
y2
A
y3
y1 s
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Test Generation for Microprocessors
I1: MVI A,D A IN
I2: MOV R,A R A
I3: MOV M,R OUT R
I4: MOV M,A OUT A
I5: MOV R,M R IN
I6: MOV A,M A IN
I7: ADD R A A + R
I8: ORA R A A R
I9: ANA R A A R
I10: CMA A,D A A
High-Level DDs for a microprocessor (example):
Instruction set:
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
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Test Generation for Microprocessors
High-Level DD-based structure of the microprocessor (example):
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
OUT
R
A
IN
I
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Test Generation for Microprocessors
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Scanning test program for adder:
Instruction sequence T = I5 (R)I1 (A)I7 I4for all needed pairs of (A,R)
OUT I4
A I7
A
R
I1
IN(2)
IN(1)
R I5
Time:t t - 1 t - 2 t - 3
Observation Test Load
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Test Generation for Microprocessors
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Conformity test program for decoder:
Instruction sequence T = I5 I1 D I4
for all DI1 - I10 at given A,R,IN
Data generation:IN 0A 101DataR 110
I1, I6 IN 0I2, I3 I4, I5 A 101
I7 A + R 1011I8 A R 111I9 A R 0
Functions
I10 A 0
Data IN,A,R are generated so that the values of all functions were different
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Outline
• Introduction to Digital Test• How to improve test quality at increasing complexity of
systems• High-level modelling and defect-orientation• Decision Diagrams (beyond BDDs)
• Hierarchical test generation – General concepts– Test generation for RT Level systems– Test generation for Microprocessors
• Hierarchical fault simulation• Overview of tools developed at D&T Lab
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67
Deductive Fault Simulation
&
&
1
1
1
2
3
45 a
c
b1
1
0
00
0
0
11
y
Fault list calculation:
La = L4 L5
Lb = L1 L2
Lc = L3 La
Ly = Lb - Lc
-----------------------------------------------------------
Ly = (L1 L2) - (L3 (L4 L5))
Gate-level fault list propagation
La – faults causing
erroneous signal on the node a
Ly – faults causing erroneous signal
on the output node y
Library of formulas for gates
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Deductive Fault Simulation with DDs
Macro-level fault propagation:
&
&
1
1
1
2
3
45 a
c
b1
1
0
00
0
0
11
y
Fault list propagated:
Ly = (L1 L2) - (L3 (L4 L5))
1 2
3 4
5
y
Fault list calculation on the DD
Ly = (L1 L2)
Ly = (L1 L2) - L3
Ly = (L1 L2) - (L3 (L4 L5))
Faults on the activated path:
First order fault masking effect:
Second order masking effect (tradeoff):
There is a tradeoff possibility between the speed and accuracy When increasing the speed of simulation the results will be not accurate (pessimistic): less fault detected than in reality
Activated faults
Masking faults
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Hierarchical fault simulation
High-Levelcomponent
High-Levelcomponent
High-Levelcomponent
Sequenceof patterns
P: First Pattern
R: Faults
Set of patternsWith faults
P; P1(R1)…Pn( Rn)
Set of patternswith faults
P; P1(R1)…Pm( Rm)
P: Pattern
Set of patternswith faults
P; P1(R1)…Pn( Rn)
System
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P20 1010
P21 1100 R21 2,4,9P22 0110 R22 1,3P23 1011 R23 6,10P24 1110 R24 5,8P25 0010 R25 7,11,12
Low-level fault simulation
P30 0100
P31 1000 R31 2,4,9P32 1100 R32 1,3P33 0110 R33 6,10P34 1100 R34 5,8P35 0100 R35 7,11,12
High-level fault propagation
P30 0100
P31 1000 R31 2,4,9P32 1100 R32 1,3,5,8P33 0110 R33 6,10
Updated complex patternP10 1100 To be fault simulatedP11 0010 R11 3P12 1001 R12 2,4,8
To be simulated atgiven faults
Gate-levelblock
Register-levelblock
Target blockunder fault
analysis
Hierarchical fault simulation
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Hierarchical fault simulation
Definition of the complex pattern:
• D = {P, (P1,R1), …, (Pk, Rk)}
• P is the fault-free pattern (value)
• Pi (i = 1,2, ..., k) are faulty patterns, caused by a set of faults Ri
• All the faults simulated causing the same faulty pattern Pi are put together in one group Ri
• R1- Rk are the propagated fault groups, causing, correspondingly, the faulty patterns P1- Pk
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Fault Simulation with DD-s
Fault propagation through a complex RT-level component
q
xA
xc
BC
A
Dq = {1, 0 (1,2,5), 4 (3,4)}, DxA = {0, 1 (3,5)}, DxC = {1, 0 (4,6)}, DA = {7, 3 (4,5,7), 4 (1,3,9), 8 (2,8)}, DB = {8, 3 (4,5), 4 (3,7), 6 (2,8)},
DC = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}.
Decision diagram
New DA to be calculated
Sub-system
for A
A01
0q
xA
B + C
A + 1
13xC A + C
04xA A
0xC
2
1
0
A - 1
A + B
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Fault Simulation with DD-s
Fault propagation through a complex RT-level component
Dq = {1, 0 (1,2,5), 4 (3,4)}, DxA = {0, 1 (2,5)}, DxC = {1, 0 (3,4)}, DA = {7, 3 (3,4,5,7), 4 (1,9), 8 (2,8)}, DB = {8, 3 (4,5), 4 (3,7), 6 (2,8)},
DC = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}.
q’ xA
1 (1,2,3,4,5) 0 (1,2,3,4,5)
A’+1
8 ()9 (8)5 (9)B’+C’
0 (1,2,5)
8() + 1(1) = 9(1)6(2) + 2(2) = 8(2)3(5) + 4() = 7(5)
xA xC
A’
4 (3,4) 0 (4)
1 (3) 0 (4)
2
3
3 .4)
1
1
New complex vector for A:
DA = {8, 3(4), 4(3,7), 5(9), 7(5), 9(1,8)}
This fault is masked8(2)
4 (7)
A’
4(3)
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Outline
• Introduction to Digital Test• How to improve test quality at increasing complexity of
systems• High-level modelling and defect-orientation• Decision Diagrams (beyond BDDs)
• Hierarchical test generation – General concepts– Test generation for RT Level systems– Test generation for Microprocessors
• Overview of tools developed atD&T Lab
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75
DECIDER: Hierarchical ATPG
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
y4
y3 y1 R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3Modules or subcircuits are represented as word-level DD structures
Logic Synthesis Scripts
Design Compiler(Synopsys Inc.)
Gate LevelDescriptions
SSBDD Synthesis
SSBDD Modelsof FUs
Hierarchical ATPG
RTL Model(VHDL)
FULibrary(VHDL)
FULibrary(DDs)
RTL DD Synthesis
Test patterns
RTL DDModel
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ATPG: Experimental Results
Reference ATPGs:HITEC - T.M. Nierman, J.H. Patel, EDAC, 1991
GATEST - E.M.Rudnick et al., DAC, 1994
TTU:
DET/RAND - hierarchical deterministic- random ATPG
GENETIC - gate-level ATPG based on genetic algorithms
HITEC GATEST DET/RAND GENETIC
Circuit Gates Faults States %Time
s %Time
s %Time
s %time
sgcd 227 844 8 89.3 196 92.2 90 92.2 3.4 93.0 702Mult 1058 3915 8 63.5 2487 77.3 3027 79.4 13.6 80.5 19886Diffeq 4195 15386 6 95.1 >4h 96.0 4280 96.0 80.0 97.9 53540Huffm 2100 2816 21 12.5 16200 27.6 3553 12.5 8460 52.8 >10h
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TURBO-TESTER: Low-Level TPG Tools
Test Generation
BIST Simulation
Methods:DeterministicRandomGenetic
Methods:BILBOCSTPStore/Generate
Design Test
Levels:GateMacro
Fault Simulation
Methods:Single faultParallelDeductive
Fault Table
Fault models:Stuck-at-faultsStuck-opensDelay faults
Test Optimization
Fault Diagnosis
Fault Location
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Conclusions
• Physical defects can be formally mapped to the logical level by Boolean differential calculus
• Functional fault model is a universal means for mapping test results from lower levels to higher levels, giving a formal basis for hierarchical approaches to test generation and fault simulation
• Decision diagrams is a suitable tool which can be used successfully both, on the logic level, and also on higher register transfer or behavioral levels
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References
1. S.Mourad, Y.Zorian. Principles of Testing Electronic Systems. J.Wiley & Sons, Inc. New York, 2000, 420 p.
2. M.L.Bushnell, V.D.Agrawal. Essentials of Electronic testing. Kluwer Acad. Publishers, 2000, 690 p.
3. M. Abramovici et. al. Digital Systems Testing & Testable Designs. Computer Science Press, 1995, 653 p.
4. S. Minato. Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publishers, 1996, 141 p.
5. R.Ubar. Test Synthesis with Alternative Graphs. IEEE Design and Test of Computers. Spring, 1996, pp.48-59.
6. J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. JETTA: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000.
7. R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED’02, San Jose, California, March 26-28, 2001, pp.365-371.
8. T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation with Real Defects Coverage. Pergamon Press. J. of Microelectronics Reliability, Vol. 42, 2002, pp.1141-114.
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80
References
• European Projects: – EEMCN, FUTEG, ATSEC, SYTIC, VILAB, REASON, eVIKINGS II
• Special thanks to: – EU project IST-2000-30193 REASON – Cooperation partners: IISAS Bratislava, TU Warsaw– Colleagues: J.Raik, A.Jutman, E.Ivask, E.Orasson a.o. (TU Tallinn)
• Contact data: – Tallinn Technical University– Computer Engineering Department– Address: Raja tee 15, 12618 Tallinn, Estonia– Tel.: +372 620 2252, Fax: +372 620 2253– E-mail: [email protected]– www.ttu.ee/ˇraiub/