HDL-Based Layout Synthesis Methodologies

HDL-Based Layout Synthesis Methodologies

Allen C.-H. Wu

Department of Computer Science

Tsing Hua University

Hsinchu, Taiwan, R.O.C

{Email: chunghaw@cs.nthu.edu.tw}

OutlineOutline

Introduction

Timing analysis

Design planning

RTL timing budgeting

A timing-driven soft-macro placement and resynthesis method

Discussion

Why Needs HDL-based Design Methodologies?Why Needs HDL-based Design Methodologies?

Then Now

Schematic capture

Component mapping & may be some logic optimization

Place & route

Layouts

HDL designspecification

Synthesis

Place & route

Layouts

Design complexity

SW : assembly language => high-level language

An HDL-based Design FlowAn HDL-based Design Flow

HDL coding styles

Layout architectures

Cell libraries

HDL design specification

RTL synthesis

Logic synthesis

Layout synthesis

Layouts

Applications

Top-Down Design MethodologyTop-Down Design Methodology

Bridging the gapbetween RTL,logic, and layoutsynthesis

Preserving designhierarchy

HDL design specification

RTL synthesis

Logic synthesis

Layout synthesis

Layouts

Applications and Layout ArchitecturesApplications and Layout Architectures

Datapath dominated designs : DSPs and processors.

Control dominated designs: controllers and communication chips.

Mixed type of designs.

Bit-sliced stacks.

Standard cells.

Macro-cell-based.

FPGAs.

Layout-driven Design methodologyLayout-driven Design methodology

HDL design specification

RTL synthesis

Logic synthesis

Layout synthesis

Layouts

Backannotation

Multi-levelestimation engine

Design EstimationDesign Estimation

Timing

Area

Power

Statistic VS. quick-synthesis methods

Analytical VS. constructive methods

OutlineOutline

Introduction

=>Timing analysis

Design planning

RTL timing budgeting

A timing-driven soft-macro placement and resynthesis method

Summary

Minimum Cycle TimeMinimum Cycle Time

Critical path delay

Clockskew

Timing AnalysisTiming Analysis

Critical path delay analysis

Clock skew analysis

Timing analysis at different design levels

Delay calculation

Parasitic extraction

Accuracy VS. fidelity

Timing AnalysisTiming Analysis

HDL design spec.

RTL synthesis

Logic synthesis

Layout synthesis

Layouts

HDL specification

Logic equations

Cell-based netlists(Tech. dependent or independent)

Floorplanning and P & R

Acc

urac

yC

ompl

exity

RTL and Logic-level Timing AnalysisRTL and Logic-level Timing Analysis

Macro

Inpu

ts

Out

puts Logic equations

Cell-based netlist

Unit and zero delay models for cells and wires

Macro based

HDL Spec.

Macro Macro

RTL Timing AnalysisRTL Timing Analysis

HDL design spec.

Macro Macro

A

T

Aspect ratio

A

T

Aspect ratio

1

2

3

4

1

2

3

4

Floorplanning Back annotation

Re-synthesis &re-floorplanning

Chip-level Timing AnalysisChip-level Timing Analysis

Taken into account inter-macro wiring delays.

Chip-level path enumeration.

Estimation vs. back annotation.

Macro cells

Floorplanning

Layout extraction

Wiring delay

Macro-level Timing AnalysisMacro-level Timing Analysis

Taken into account intra-macro wiring delays.

Path delay enumeration.

Estimation vs. back annotation.

Netlists

P & R

Layout extraction

Wiring delay information

Accuracy of Timing AnalysisAccuracy of Timing Analysis

Design Stages

Floorplanning

Placement

Global routing

Detailed routing

Accuracy

100+/-25%

100+/-15%

100+/-7%

100+/-0%

Source: DAC’97 Tutorial by Blaauw_Cong_Tsay

RTL 100+/-50%???

OutlineOutline

Introduction

Timing analysis

=> Design planning

RTL timing budgeting

A timing-driven soft-macro placement and resynthesis method

Summary

Design PlanningDesign Planning

Macro definitions

Soft macro generation

Macro placement

Pin assignment

Chip Planning IChip Planning I

Hardmacros

Softmacros

Chip Planning IIChip Planning II

Hardmacros

Softmacros

Design Planning ConsiderationsDesign Planning Considerations

How much timing, area, and power budgets should be assigned to each macro?

How to generate soft macros? - top-down - bottom-up

How to layout clock and power/ground network?

Design BudgetingDesign Budgeting

MacroLoad capacitance

Required arrival time

Driving resistance

Arrival time

RTL & Logic synthesis

Netlists

RTL Spec.

Delay, area,power constraints??????????????

Soft Macro GenerationSoft Macro Generation

Design

SM SM SM

SM SMClustering

Partitioning

Based on design hierarchical information

Soft Macro Generation (Cont.)Soft Macro Generation (Cont.)

Perform clustering techniqueson a flattened netlist

Clustering criteria:. Timing. Interconnect

Design Hierarchy PreservationDesign Hierarchy Preservation

Verilog design spec.

HDL synthesis

Macro formation

Macro placement

Macro to cell placement

Initial placement

HDLsMod1Mod2Mod3

Clock Network StylesClock Network Styles

Mesh: robust, large area and power

Trunk: simple

Tree: min area, many supporting design algorithms

Clock Issues at RTLClock Issues at RTL

Critical path is determined from clock skew andskew cannot be determined until placement iscompleted!

How to incorporate clock skew issues into earlydesign planning????

Still an open problem!

RTL Timing AnalysisRTL Timing Analysis

HDL design spec.

Macro Macro

A

T

Aspect ratio

A

T

Aspect ratio

1

2

3

4

1

2

3

4

Floorplanning Back annotation

Re-synthesis &re-floorplanning

Timing-critical Macro DetectionTiming-critical Macro Detection

HDL Spec.

Macro Macro

HDL spec.

Back annotation

Floorplanning

HDL synthesis

Chip-level timing analysis

Critical macro

RTL Design PlanningRTL Design Planning

HDL Spec.

Macro Macro

Delay & area estimations

Constructive oranalytical method

Cell library

Floorplanning

RTL timing analysis

Back-annotation

Bac

k-an

nota

tion

OutlineOutline

Introduction

Timing analysis

Design planning

=> RTL timing budgeting

A timing-driven soft-macro placement and resynthesis method

Summary

RTL Design BudgetingRTL Design Budgeting

RTL Spec.

RTL/logic Synthesis

Netlists

Chip Layout

Physical-level Synthesis

Loop

LoopLoop

RTL sign-off

HMSM3

HM SM1 SM2

AreaDelayPower

Budget?

Timing BudgetingTiming Budgeting

1 Cycle

Cross-macro timing paths!!!

Timing Budgeting IssuesTiming Budgeting Issues

How to estimate delay and area from RTL specification???

After floorplanning? After RTL/logic synthesis? After placement? After routing?

Run time VS. accuracy?

How to distribute timing budget among macros?

No much work has been done in this area!!!

Timing Budgeting for Design OptimizationTiming Budgeting for Design Optimization

M1 M2 M3

A

Tx

A

Tx

A

Tx

Minimize total area subject tosatisfying the timing constraints.

OutlineOutline

Introduction

Timing analysis

Design planning

RTL timing budgeting

=> A timing-driven soft-macro placement and resynthesis method

Summary

A Typical Design Flow for Macro-based DesignA Typical Design Flow for Macro-based Design

HDL Description

HDL Synthesis

Floorplanning

P & R

Timing Analysis

OK?

Chip Layout

Back-annotation

Yes

No

Design Hierarchy PreservationDesign Hierarchy Preservation

HDL Description

M1

M_11

M_12

M2

Preserving HDL design hierarchy for soft-macro placement?

A complete chip design methodology?

HM

SM

HMHM

ConsiderationsConsiderations

How to utilize HDL design-hierarchy information to guide soft-macro placement procedure?

How to integrate design tasks and point tools at different design level to form a complete chip design methodology?

How to exploit the interaction between different design tasks.

Design Flow for Design Hierarchy PreservationDesign Flow for Design Hierarchy Preservation

HDL Description

HDL Synthesis

Floorplanning &Area Extraction

P & R Pre-layoutTiming Analysis

Chip Layout

Back-annotation

Post-layoutTiming Analysis

SM Placement

Structural-tree Construction

SM Formation

Structural-tree ConstructionStructural-tree Construction

The main objective is to preserve the design structural information from an HDL design description for macro formation.

Top

HM1

HM2SM1 SM2 SM3 SM4 SM5

SM4,5SM1,2

Soft macro FormationSoft macro Formation

Decomposition of large soft macros. - A large macro is too rigid for macro placement.

Clustering of small soft macros. - Many small macros increase the computational complexity.

Soft Macro PlacementSoft Macro Placement

Inputs: a set of software macros and the available area for soft macros.

Outputs: the relative location of each soft macro on the layout plane.

1st step: force-directed-based placement.

2nd step: Sweeping-based soft-macro assignment.

Floorplanning and Soft-Macro Area ExtractionFloorplanning and Soft-Macro Area Extraction

HM

HM

SM

HM

Force-directed-based PlacementForce-directed-based Placement

HMHM

HM

HM

SM1

SM2 SM3

SM4

Soft-macro PlacementSoft-macro Placement

SM1

SM2

SM3

SM4X

Y

SM1

SM4SM2

SM3

The Experimental procedure: Design SynthesisThe Experimental procedure: Design Synthesis

HDL Description

Synopsys(Design Compiler)

Netlist

Structural-tree Construction

SM Formation

The Experimental Procedure: Floorplanning and P&RThe Experimental Procedure: Floorplanning and P&R

Netlist

Cadence(Silicon Ensemble)

SM Placement Cadence (HLDS)

Cadence(Silicon Ensemble)

Chip Layout

The Experimental Procedure: Timing AnalysisThe Experimental Procedure: Timing Analysis

Chip Layout

Cadence(HyperExtract)

AVANT!(STAR-DC)

Synopsys(Design Time)

Timing

Benchmarking DesignsBenchmarking Designs

EX Nets #IO #HM #SM G(SM) G(Total)

Ind1 15,373 83 13 157/22 38,240 75,000

Ind2 27,404 155 8 150/28 75,361 95,000

Ind3 53,344 73 31 292/50 124,180 230,000

ResultsResults

EX Area Method 1 Our %

Ind1 5,025X5,025 22.5ns 18.3ns -19

Ind2 5,300X5,275 47.2ns 35.9ns -24

Ind3 7,300X7,200 27.6ns 19.8ns -29

The Most Critical Path without Preserving Design Hierarchy The Most Critical Path without Preserving Design Hierarchy

The Most Critical Path with Preserving Design HierarchyThe Most Critical Path with Preserving Design Hierarchy

Resynthesis for Area/Delay MinimizationResynthesis for Area/Delay Minimization

HMSM3

HMSM1 SM2

HMSM3

HM SM1 SM2Resynthesis forarea minimization

Resynthesis fordelay minimization

HMSM3

HM SM1 SM2

Resynthesis-based Design FlowResynthesis-based Design Flow

HDL Description

HDL Synthesis

Floorplanning

SM Placement

Timing Analysis

Chip Layout

P & R

Yes

No

Resynthesis

OK?

Slack Computation for Resynthesis SelectionSlack Computation for Resynthesis Selection

Macro

FF

p1p2

p3

POS(SM_i) = Slack(p_j), for all Slack(p_j) > 0.

NEG(SM_i) = Slack(p_j), for all Slack(p_j) < 0.

The Experimental Design FlowThe Experimental Design Flow

HDL Description

HDL SynthesisSynopsys (Design Compiler)

RC extractionAVANT! (STAR-RC)

Timing analysisSynopsys (Design Time)

Block placementCadence (Silicon Ensemble)

Chip Layout

ResynthesisSynopsys (Design Compiler)

Soft-macro placement

Soft-macro Formation

P & R AVANT!(Aquarious XO)

Delay calculationAVANT! (STAR-RC)

OK?yes

no

Benchmarking DesignsBenchmarking Designs

EX Nets #IO #HM #SM G(SM) G(Total)

Ind1 15,373 83 13 157/22 38,240 75,000

Ind2 27,404 155 8 150/28 75,361 95,000

Ind3 53,344 73 31 292/50 124,180 230,000

Results (Ind2 using 0.5 um tech.)Results (Ind2 using 0.5 um tech.)

I #Gates Delay T_resyn T_eco

1 95,000 38.25ns 9hr 7hr

2 95,140 33.71ns 8hr 5hr

3 95,172 33.30ns 6hr 4hr

Results (Ind2 using 0.25 um tech.)Results (Ind2 using 0.25 um tech.)

I #Gates Delay T_resyn T_eco

1 95,000 27.68ns 10hr 7hr

2 95,249 25.67ns 9hr 5hr

3 95,561 21.67ns 9hr 5hr

4 97,808 19.32ns 8hr 4hr

Results (Ave. Gate Delay VS. Interconnect Delay of Ind2)Results (Ave. Gate Delay VS. Interconnect Delay of Ind2)

Lib. G-delay[A] I-delay[B] [B]/[A]0.5um 0.171ns 0.277ns 1.62

0.25um 0.107ns 0.325ns 3.04

The Initial Critical Path of Ind2 using the 0.5um LibraryThe Initial Critical Path of Ind2 using the 0.5um Library

The Critical Path of Ind2 after 2 Resynthesis IterationsThe Critical Path of Ind2 after 2 Resynthesis Iterations

DiscussionDiscussion

How to perform timing analysis at different design stages?

Timing, area and power budgeting methods for early design planning?

Performance-driven and power-driven chip design methodologies.