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Has Resistive Memory Found Its Place Within the Internet of Things ? Michael N. Kozicki Arizona State University Narbeh Derhacobian Adesto Technologies

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Page 1: Has Resistive Memory Found Its Place Within the Internet ...g-reram.eu/Documents/presentations/Kozicki.pdf · Has Resistive Memory Found Its Place Within ... • 100 µs, 1.5 V write

Has Resistive Memory

Found Its Place Within

the Internet of Things?

Michael N. KozickiArizona State University

Narbeh DerhacobianAdesto Technologies

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•Market

•Technology

•Manufacturability

•Now what?

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•Market

•Technology

•Manufacturability

•Now what?

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https://www.apple.com/pr/products/apple-watch/Apple-Watch.html

Progress through scaling

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Worldwide Device Shipments by Segment (Millions of Units)http://www.gartner.com/newsroom/id/3088221

The rise of mobile

Device Type 2014 2015 2016 2017

Traditional PCs (Desk-Based

and Notebook) 277 251 243 233

Ultramobiles (Premium) 37 49 68 89

PC Market 314 300 311 322

Ultramobiles (Tablets and

Clamshells) 226 214 228 244

Computing Devices Market 540 514 539 566

Mobile Phones 1,879 1,940 2,007 2,062

Total Devices Market 2,419 2,454 2,546 2,628

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Market evolution

Desktops

Gaming

Servers

Routers

Laptops

Cell

Phones Smart

Phones

1990’s

Computing MobilityCommunicationEra of2010’s 2000’s

Wearables

Sensors

IoT

M2M

Autonomy

2020’s

The vast market potential of the Internet of Things (IoT)…“The Internet of things and the technology ecosystem surrounding it are

expected to be a $8.9 trillion market in 2020, according to IDC.” http://www.zdnet.com/internet-of-things-8-9-trillion-market-in-2020-212-billion-connected-things-7000021516/

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Market evolution = new requirements

Then Now Future

Speed & density Low power, integrated,

connected, secure

GHz + Gb pJ + nW

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Technology requirements• Very low power devices

–A CR2032 button cell only holds around 2 kJ» Operations must be low energy (<pJ)

–Device, and circuit limitations» Low voltage (<1V), low current (tens of A)

» Small periphery/high array efficiency (for low density)

• Small form factor

–Small geometry devices and compact design

–Thin and possibly even flexible chips

• Low cost

–Manufacturability is key, small area helps!

• Radiation tolerance

–Medical devices, wearables, mil-aero, soft errors

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Are we there yet?

• Logic devices can already operate under these conditions

–Might not be ideal but they work!

• There is a huge problem with existing memory and storage

–Voltages are high (Flash, SSD)

–Detection of state is difficult in highly scaled devices (DRAM, Flash, SSD)

–Currents are high (HDD, MRAM, PCRAM)

–Form factor is not ideal (HDD)

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IBM: Materials Will Spur Next Wave of

Chip Innovation Electronic News, 11/4/2005

“Innovation in materials has replaced scaling as

the main source of performance and feature

improvements in leading edge CMOS chips.”

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•Market

•Technology

•Manufacturability

•Now what?

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R. Waser, R. Dittmann, G. Staikov, and K. Szot., “Redox-Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges”, Adv. Mater., vol. 21, 2632–2663

(2009).

Resistance change memory taxonomy (circa 2009)

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Glassy solid electrolyte

high resistanceMobile ions added during

processing or via

electroforming

Inert

electrode

Oxidizable

electrode

+

-

M M+ + e-

M+ + e- M

e-

e-

Reverse bias dissolves electrodeposit via oxidation/reduction

Metallic electrodeposit

low resistance M+

M+M+

M+

M+

M+

M+

M+M+

M+

Programmable Metallization Cell (PMC)

Cryo-TEM

image of

filament

within solid

electrolyte 15nm

Note: Programmable Metallization Cell (PMC) is a platform technology for a variety of mass transport

applications. Conductive Bridging Random Access Memory (CBRAM) is the term generally applied to

memory applications of PMC.

Oxidation

Applied bias

Reduction

Ion

cu

rren

t

+

-

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Programming

U. Russo, D. Kamalanathan, D. Ielmini, A.L. Lacaita, and M.N. Kozicki, “Study of Multilevel

Programming in Programmable Metallization Cell (PMC) Memory,” IEEE Transactions on Electron

Devices, Vol. 56, 1040 – 1047 (2009).

1 pJ operating point

Model is based on a Ag/Ag-Ge-S/W 1T-1R cell and

includes transistor load

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D. Mahalanabis, H. J. Barnaby, Y. Gonzalez-Velo, M.N. Kozicki, S. Vrudhula, P. Dandamudi, “Incremental Resistance

Programming of Programmable Metallization Cells for Use as Electronic Synapses,” Solid State Electronics, in press.

Incremental programming

Pulse programming• 100 µs, 1.5 V write pulses• 200 µs, -1.5 V erase pulses• 5 kΩ current limiting resistance• 100 mV read pulses

Program Erase

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On-state resistance vs.programming current

I. Valov, R. Waser, John R. Jameson and M.N. Kozicki, “Electrochemical metallization memories—

fundamentals, applications, prospects,” Nanotechnology, vol. 22 (2011) doi:10.1088/0957-

4484/22/25/254003

“NVM”

range

“Volatile”

range

Why?

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17

Example: Ag12As35S53

Mostly As-S bonds, Ag-S bonds

Techniques:

Full DFT, 500 atom system

X-ray diffraction, neutron

scattering, EXAFS

Jaakko AkolaUniversity of Jyväskylä and

Tampere Technological University,

Finland

Bob JonesJülich Research Center, Germay

Tomas WagnerUniversity of Pardubice, Czech

Republic

Where do the metallic filaments form?

Cavities comprise 24% of the volume of Ag12As35S53, (SiO2 is 32% but cavities are more dispersed?)

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Filament morphology

J.R. Jameson, N. Gilbert, F. Koushan, J. Saenz, J. Wang, S. Hollmer, M. Kozicki, and N. Derhacobian., “Quantized

Conductance in Ag/GeS2/W Conductive-Bridge Memory Cells,” IEEE Elec. Dev. Lett., vol. 33, 256-259 (2012).

µ

Data show resistance quantization (12.9kW) in programmed devices

µ

µ

µ

Continuous filament forms for iprog > VtGo

= 20 to 50 µA

Filament

branch

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S. Rajabi, M. Saremi, H.J. Barnaby, A. Edwards, M.N. Kozicki, M. Mitkova, D. Mahalanabis, Y. Gonzalez-Velo, A. Mahmud,

“Static impedance behavior of programmable metallization cells”, Solid-State Electronics, vol. 106, 27–33 (2015).

Impedance spectroscopy

Ion source/sink

High ρ, low D

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Electrolyte-oxide layered structure

“A dual-layered electrolytic resistance memory has been demonstrated

for the first time. Complete nanosecond switching of all cells in the

4kbit array, satisfactory retention, scalability down to 20nm, endurance

up to 1E7 cycles, and preliminary 4-level operation ...”

Cu-Te electrolyte

on

GdOx dielectric

K. Aratani et al., “A Novel Resistance Memory with High Scalability and Nanosecond

Switching,” IEDM Tech. Digest, 2007.

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P. Dandamudi, H. J. Barnaby, M. N. Kozicki, Y. Gonzalez-Velo, K. E. Holbert, “Total Ionizing

Dose Tolerance of the Resistance Switching of Ag-Ge40S60 based Programmable

Metallization Cells”, 2013 Conference on Radiation Effects on Components and Systems

(RADECS), September 23rd – 27th, 2013, Oxford, UK

Gamma exposure to 10 Mrad

No impact of TID on the LRS or HRS

of Ge-S devices

Cumulative Distribution Function

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•Market

•Technology

•Manufacturability

•Now what?

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Forming Switching

Cross-

point

device

SiO2 cap(400nm)

Cu-SiO2-W devices, 15 nm deposited SiO2, 500 °C anneal

Cu-SiO2 devices

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Rser

R1=355ohm, L1=6.06 x 10-6H

Impedance spectroscopy

frequency

Off state

frequency

On state

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Incremental programmingProgramming from

0.45 to 0.75 V

Erase from -0.40 to -1.00 V

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Integrated diode isolation - write

n+ Si

Sarath C. Puthentheradam, Dieter K. Schroder, and Michael N. Kozicki, “Inherent diode isolation in

programmable metallization cell resistive memory elements,” Appl. Phys. A (2011) 102: 817–826.

Cu top electrode - 35 nm

Cu doped SiO2 - 15 nm

Al - 200 nm

Dielectric

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n+ Si

Cu top electrode - 35 nm

Cu doped SiO2 - 15 nm

Al - 200 nm

Dielectric

Integrated diode isolation - erase

Sarath C. Puthentheradam, Dieter K. Schroder, and Michael N. Kozicki, “Inherent diode isolation in

programmable metallization cell resistive memory elements,” Appl. Phys. A (2011) 102: 817–826.

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Rfilament

Relectrolyte

On state

Saturation current scales

with programming current

- depends on filament area

Diode device characteristics

Sarath C. Puthentheradam, Dieter K. Schroder, and Michael N. Kozicki, “Inherent diode isolation in

programmable metallization cell resistive memory elements,” Appl. Phys. A (2011) 102: 817–826.

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Gamma exposure to 7.1 Mrad

Multi-level resistance

programming is maintained

following gamma exposure

W. Chen, H. J. Barnaby, M. N. Kozicki, A. H. Edwards, Y. Gonzalez-

Velo, R. Fang, K. E. Holbert, S. Yu, W. Yu, “ Study of Gamma –Ray

Exposuure of Cu-SiO2 Programmable Metallization Cells”, IEEE

Trans. Nuc. Sci., in press.

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The CBRAM Advantage

Conductive Bridging RAM (CBRAM®) is a

breakthrough technology platform that

overcomes a critical power barrier to

widespread innovation. Adesto’s Mavriq™

memory, built on CBRAM technology, is

adaptable for a broad range of

applications–from medical devices and

appliances to wearables and

smartphones. It enables 100 times less

energy consumption than today’s leading

memory technologies without sacrificing

performance and reliability.

Memory for the

Internet of Things

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CBRAM in battery operated wearable device

Heart monitor:

Recording of an

ECG on a serial

NVM device.

Low energy memory allows

10x longer operational life

CBRAMStd. EEPROM #1Std. EEPROM #2

CBRAMStd. EEPROM #1Std. EEPROM #2

After 1 hour

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Memory for medical applications

Storage of code and data in medical equipment

and devices.

Examples: Orthopedics, blood bags, catheters, glucose

meters, wireless patient monitoring

Data integrity of serial non

volatile memory devices after

gamma and e-beam irradiation

Pass – Full Data Integrity and Functionality Preserved

Fail – Data Loss

Tests performed by several medical device companies and

Typical

Dose for

Medical

Sterilization

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• Minimal resistance change with time, independent of initial resistance value

• Minimal resistance change with respect to temperature, independent of initial resistance value

R vs. time at 200C R vs. temperature at 60mins

CBRAM® retention

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•Market

•Technology

•Manufacturability

•Now what?

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VLSI Symposia, Kyoto, June 2013

0.6 V, 1 pJ operation!

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Embedded ReRAM product

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With 3D XPoint, Micron Technology,

Inc. Is Predicting Memory RevolutionBY NEHA GUPTA · OCTOBER 9, 2015

According to Micron’s Todd Farrell, stagnation in new

memory development has resulted in multiple

computing challenges, which have been

compounded by the rapid processor advancements.

…the ideal memory design needs to fit into the

existing manufacturing infrastructure. In some cases,

Farrell noted, memory designs have perished

because they cannot be produced in scale using

existing manufacturing systems.

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HP and SanDisk partner on new

memory chips to counter Intel-Micron

alliancePublished: Oct 8, 2015 12:15 p.m. ET

Hewlett-Packard Co. and SanDisk Corp. are collaborating on a

new breed of memory chips... The companies… predicted that

their forthcoming chips will be 1,000 times faster than flash

memory. The new chips also will be able to replace the widely

used chips known as DRAMs at much lower cost...

The goals they described mirror some of those laid out in late

July by chip makers Intel Corp.and Micron Technology Inc. which

announced a new memory technology they call 3D Xpoint.

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Final thoughts

• The semiconductor industry is embracing

the requirements of low energy mobile

and autonomous systems.

• PMC/CBRAM is a low voltage/low energy

technology that is manufacturable.

• Products are already in the marketplace

and momentum is growing.

• The Internet of Things (IoT) will likely

drive further growth in the applications of

low energy resistive memories.

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Thank you!

Support provided by:

Axon Technologies (memory)DTRA and AFRL (radiation research)

And thanks to Adesto for all the cool toys!