hardware implementation issues on viterbi decoder
DESCRIPTION
Hardware Implementation Issues on Viterbi Decoder. Speaker : Meng-Hau Wu Advisor : Tzi-Dar Chiueh Date : May 31, 2004. Outline. Review of Viterbi algorithm Hardware implementation issues Branch Metric Computation (BMC) Add-Compare-Select (ACS) - PowerPoint PPT PresentationTRANSCRIPT
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Hardware Implementation Issues on Hardware Implementation Issues on Viterbi DecoderViterbi Decoder
Speaker : Meng-Hau Wu Advisor : Tzi-Dar Chiueh Date : May 31, 2004
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OutlineOutline
• Review of Viterbi algorithm• Hardware implementation issues
– Branch Metric Computation (BMC)– Add-Compare-Select (ACS)– Survivor Memory Management (SMM)
• Conclusion• Reference
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Review of Viterbi algorithmReview of Viterbi algorithm
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Encoding ProcessEncoding Process
• Take convolutional code as an example n=2
k=1
m=2
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Decoding ProcessDecoding Process
• Maximum Likelihood Sequence Estimator (MLSE)
K
k
ik
K
k
ikk
K
k
ikk
i
BM
srP
srPPM
1
)(
1
)(
1
)()(
)|(log
)|(
(Euclidian distance, Hamming distance)
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Viterbi AlgorithmViterbi Algorithm
K
k
ik
i BMPM1
)()(
1. There are only 2mk paths will survive
2. All survivor paths will merge at the same state about 5m stages ago
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Implementation of Viterbi Implementation of Viterbi DecoderDecoder
Branch Metric Computation
(BMC)
Add-Compare-Select (ACS)
Survivor Memory
Management (SMM)
Buff
er
Decoder Input
Decoder Output
K
k
ik
i BMPM1
)()(
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Hardware implementation issuesHardware implementation issues
-Branch Metric Computation (BMC) -Add-Compare-Select (ACS) -Survivor Memory Management (SMM)
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Hard-DecisionHard-Decision
• Branch metric is irrelative to modulation and architecture used• Use Hamming distance as branch metric
K
k
ik
i BMPM1
)()(
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Soft-Decision (1/3)Soft-Decision (1/3)
• Branch metric depends on modulation and architecture
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Soft-Decision (2/3)Soft-Decision (2/3)
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Soft-Decision (3/3)Soft-Decision (3/3)
[1]
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ComparisonComparison
• Hard decision– Branch metric is irrelative to modulation
and architecture used– Use Hamming distance as branch metric
• Soft decision– Branch metric depends on modulation
and architecture– By definition
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Hardware implementation issuesHardware implementation issues
-Branch Metric Computation (BMC) -Add-Compare-Select (ACS) -Survivor Memory Management (SMM)
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Basic ConceptBasic Concept
Overflow problem!!
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Overflow PreventionOverflow Prevention• Modulo normalization
– The output of Viterbi decoder only depends on difference of metrics
– The difference between metrics is bounded– Two’s complement arithmetic [2]
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Bounded Difference Between Bounded Difference Between MetricsMetrics
decisionhardfornB
decisionsoftfornBtPMtPM
qntPMqntPMtPMtPM
qntPMtPM
ordermemoryencoderisntPMtPMBBMAssume
ss
ssss
ss
ssik
,
,2|)()(|
])([)()()(0
)()(
),()(,||
12
12
1212
22
21)(
[2]
0 tt-n
s1
s2
q1
q2
s
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Modulo normalization (1/2)Modulo normalization (1/2)
Modular arithmeticmj = (mj+C/2)(mod C)-C/2We allow overflow and transform PM from one domain (straight line) to another domain (circle), such that we can use finite-length register
Given |m1-m2|<C/2, then m1<m2 if and only if
Concept :
[3]
=>This keeps the relative relationship between m1 and m2, though loses the absolute information of them
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Modulo normalization (1/2)Modulo normalization (1/2)Implementation :
We use “2’s complement arithmetic” to replace unsigned arithmetic and comparison=> Given |m1-m2|<C/2, then m1<m2 if and only if m1-m2<0 (in 2’s complement sense) 0001 (1)-) 1111 (-1) 0010 (2)
1001 (-7)-) 0111 (7) 0010 (2)
-1 10 0-7 7
[3]
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Modulo Normalized ACSModulo Normalized ACS
[3]
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Other Overflow Prevention Other Overflow Prevention MethodsMethods
• Reset• Variable shift• Fixed shift
[3]
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Hardware implementation issuesHardware implementation issues
-Branch Metric Computation (BMC) -Add-Compare-Select (ACS) -Survivor Memory Management (SMM)
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Register ExchangeRegister Exchange
[4]
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Trace-back Basic ConceptTrace-back Basic Concept
[4]
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Trace-back Algorithm (1/3)Trace-back Algorithm (1/3)
• K-pointer even
[4]2k memory block
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Trace-back Algorithm (2/3)Trace-back Algorithm (2/3)
• K-pointer odd
[4]2k-1 memory block
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Trace-back Algorithm (3/3)Trace-back Algorithm (3/3)
• One-pointer
[4]s+1 memory block
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Comparison (1/2)Comparison (1/2)
• Exchange register– Simple (advantage)– Large interconnection area (disadvantage)
• Trace-back– Smaller area when storage element are many– More complicated– Large RAM access power
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Comparison (2/2)Comparison (2/2)• K-pointer
– Harmonic clock rate– Larger area
• One-pointer– Smaller area– Different clock rate
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Conclusion & ReferenceConclusion & Reference
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ConclusionConclusion
• Viterbi decoder can be divided into three parts– Branch Metric Computation (BMC)
• Hard decision• Soft decision
– Add-Compare-Select (ACS)• Modulo normalized
– Survivor Memory Management (SMM)• Register exchange• Trace back
– K-pointer even– K-pointer odd– One-pointer
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ReferenceReference• [1] Modified Viterbi Algorithm and 802.11a Codec Design
Te-Wei Chang, MS thesis, 2002• [2] An alternative to metric rescaling in Viterbi decoders
Hekstra, A.P.;Communications, IEEE Transactions on , Volume: 37 , Issue: 11 , Nov. 1989 Pages:1220 – 1222
• [3] VLSI architectures for metric normalization in the Viterbi algorithmShung, C.B.; Siegel, P.H.; Ungerboeck, G.; Thapar, H.K.;Communications, 1990. ICC 90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conference Record., IEEE International Conference on , 16-19 April 1990 Pages:1723 - 1728 vol.4
• [4] FPGA Realization of the Viterbi Decoder for HDSL2 SystemsFeng Lo, MS thesis, 2000