hardcopy debug 2-4-13

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Applications Note

1020 pin SoC Step-By-Step Test

Development and Debug


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Observations

n the white experimental:

1. Jeff's generates fat STROBEIO (ASTROBE-DTRSOBE-ASTROBE) Beginning of his State 5 till the end of State 7

2. HC's REPLYIO gets fat in the middle of Jeff's State D six XB clocks after fat STROBEIO

3. RDCON* fires Lo in State A and D

4. REPYIO gets fat on 1st rising edge of RDCON* after RDCON* fires LO the first time

n the Reference:

1. REPYIO also gets fat on 1st rising edge of RDCON* after RDCON* fires LO the first time

2. Fat STROBEIO applied for 3 clocks at proper Address 9FFFCF3 and HC responds with REPLYIO fat (DSENs-READY-DSENs-READY...) six-sevenclocks after Fat STROBEIO

White is experimental, black is reference.


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ect is the individual TLAs for CF3 and CFB and a composite drawing with those plus the reference lined up. The reads are working correctly!


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IDEN


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Raceway Hardcopy


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1. Hardcopy Raceway Top


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2. raceway_top_tb.vhd


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3. Hardcopy Compare


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4.LED Driver


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5. Hardcopy Ident Read


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6. Clock Module


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16.6 33.3 49.9 66.6 83.2 99.9

66 MHz

20 MHz

33 MHz 0 1 0 1

75% Duty Cycle

--------------------------------------------------------------------------------

-- Copyright 2011

-- At-Spex

-- All Rights Reserved

--

-- Project : MERCURY_COMPUTER_STRATIX

-- Filename : clocks.vhd

-- Title : Clock Generator Module

--

--------------------------------------------------------------------------------

-- Functional Description:

-- This module synchronizes RESET_OUT_N to XCLKI. It also generates XSYNCI_N

-- for the Board on the falling edge of XCLKI when the control phase is low for

-- the Interlink. The Board will use this to generate its own control phase that

-- is 180 degrees out of phase with the Interlink (master).


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--

-- To do:

-- None

--

-- Tool issues and dependencies:

-- None

--

-- Technology issues and dependencies:

-- None - Technology Independent

--

-- Design issues and limitations:

-- None

--

-- Baseline or reference:

-- None

--

--------------------------------------------------------------------------------

-- Date: 2011-11-09

-- Revision: 1.0

-- Authors: JPP/DMO

--------------------------------------------------------------------------------

--

-- Entity: clocks

-----------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

-- synopsys translate_off

use ieee.VITAL_Timing.all;

library proasic3;

use proasic3.all;

-- synopsys translate_on


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entity clocks is

port (

--LMO500 outputs:

XCLKI : in std_logic; -- 66 MHz clock to tester FPGA and DUT

RESET_IN_N : in std_logic; -- Synchronous Reset from tester

--RACEway interface:

RESET_OUT_N : out std_logic; -- Synchronized reset

PHASE : out std_logic; -- Control Phase, divde by 2 of XCLKI

XSYNCI_N : out std_logic -- synchronization output for Board

);

end entity clocks;

---------------------------------------------------------------------------

--

-- Entity: ident_read

-- Architecture: rtl

--

---------------------------------------------------------------------------

architecture rtl of clocks is

------------------------------------------------

signal ctl_phase : std_logic; -- phase at master

signal clk_count : std_logic_vector(1 downto 0); -- clock count to generate sync pulse for slave

signal reset_q : std_logic; -- for reset synchronizer

signal reset_n : std_logic;

---------------------------------------------------------------------------

-- Begin

---------------------------------------------------------------------------

begin


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p_synchronizer:

process (RESET_IN_N, XCLKI)

begin

if RESET_IN_N = '0' then

reset_q


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Test bench state machine.

isio-slave_state_machine.pdf


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Ident State Machine. All state transitions on XCLKI

WAIT_FOR_GOROUTE_1

ROUTE=DATA

REQO=1

GO=0 OR REQI=1 OR 0

ROUTE_2

ROUTE=DATA

REQO=1astrobe=1

SH_ROUTE

SHIFTED_ROUTE=DATA

REQO=1

astrobe=1

ADDR_1

DATA=ADDRESS

REQO=1astrobe= 1

ADDR_2

DATA=ADDRESSREQO=1

dstrobe=1

REPLYIO=0

FINAL_ASTROBE

REQO=1

astrobe=1

WAIT4RDY_1

REQO=1

WAIT4RDY_2

REQO=1

WAIT4RDY_3

REQO=1

0 & REPLYIO=1

WAIT4READ

REQO=1

READ_WD1

REQO=1

RESULTS(63 downto 32)

= DATA

READ_WD2

REQO=1

RESULTS (31 downto 0) = DATA

DATA_RDY=1

error_asserted=RDCONIO

GO=1 & REQI=0 & 1

0 & REPLYIO=11 & REPLYIO=1

Power on

1OR REPLYIO=0


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hardcopy debug 2-4-13

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