Handbook of 3D Integration

Related Titles

Garrou, P., Bower, C., Ramm, P. (eds.)Handbook of 3D IntegrationVolumes 1 and 2: Technology and Applications of 3D Integrated Circuits2012Print ISBN: 978-3-527-33265-6

Garrou, P., Koyanagi, M., Ramm, P. (eds.)Handbook of 3D IntegrationVolume 3: 3D Process Technology2014Print ISBN: 978-3-527-33466-7

Handbook of 3D Integration

Design, Test, and Thermal Management

Edited byPaul D. Franzon, Erik Jan Marinissen, and Muhannad S. Bakir

Volume 4

Volume Editors:

Paul D. FranzonNorth Carolina State UniversityElectrical and Computer Engineering2410 Campus Shore DriveRaleigh, NC 27606USA

Erik Jan MarinissenIMECKapeldreef 753001 LeuvenBelgium

Muhannad S. BakirGeorgia Institute of TechnologyElectrical and Computer Engineering791 Atlantic Drive NWAtlanta, GA 30318USA

Series Editors:

Philip GarrouMicroelectronic Consultants ofNorth Carolina3021 Cornwallis Road27709 Res. Triangle Park, NCUSA

Mitsumasa KoyanagiTohoku UniversityNew Industry Creation Hatchery Center6-6-10 Aza-Aoba, Aramaki980-8579 SendaiJapan

Peter RammFraunhofer EMFTDevice and 3D IntegrationHansastr. 27d80686 MünchenGermany

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v

Contents

Introduction to Design, Test and Thermal Managementof 3D Integrated Circuits xv

Part I Design 1

1 3D Design Styles 3Paul D. Franzon

1.1 Introduction 31.2 3D-IC Technology Set 31.3 Why 3D 61.4 Miniaturization 71.5 Memory Bandwidth 81.6 3D Logic 101.6.1 Power-Efficient Computing and Logic 111.6.2 Modular Partitioning: FFT Processor 121.6.3 Circuit Partitioning 131.6.4 3D Heterogeneous Processor 141.6.5 Thermal Issues 151.7 Heterogeneous Integration 161.8 Conclusions 18

References 18

2 Ultrafine Pitch 3D Stacked Integrated Circuits: Technology,Design Enablement, and Application 21Dragomir Milojevic, Prashant Agrawal, Praveen Raghavan, Geert Van der Plas,Francky Catthoor, Liesbet Van der Perre, Dimitrios Velenis, Ravi Varadarajan,and Eric Beyne

2.1 Introduction 212.2 Overview of 3D Integration Technologies 232.2.1 Integration Granularity 232.2.2 Stacking Orientation 232.2.3 TSV Formation 242.3 Design Enablement of Ultrafine Pitch 3D Integrated Circuits 252.3.1 Design Flow Overview 25

vi Contents

2.3.2 3D Integration Backbone Tool 272.3.3 3D Design Flow Add-Ons 282.3.3.1 Interconnect Delay and Power Models 292.3.3.2 Repeater Area Model 302.3.3.3 Cost Model 312.4 Implementation of Mobile Wireless Application 322.4.1 Application Driver 322.4.2 Architecture Template 322.4.3 MPSoC Instance 342.4.4 Multiple Memory Organization and Bus Structure 342.4.5 Experimental Setup 352.4.6 Experimental Results 362.4.6.1 Private vs. Hybrid Memory Architecture 362.4.6.2 Interconnect Technology Comparison 362.4.6.3 Impact of System Architecture 372.4.6.4 System Parameter vs. Design Choices 382.5 Conclusions 38

References 39

3 Power Delivery Network and Integrity in 3D-IC Chips 41Makoto Nagata

3.1 Introduction 413.2 PDN Structure and Integrity 413.3 PDN Simulation and Characterization 433.4 PDN in 3D Integration 49

References 52

4 Multiphysics Challenges and Solutions for the Design ofHeterogeneous 3D Integrated System 53Alexander Steinhardt, Dimitrios Papaioannou, Andy Heinig,and Peter Schneider

4.1 Introduction 534.1.1 Example: Stent 574.1.2 Example Interposer 594.2 Data Handling for the System View 614.3 Electrical Challenges 624.3.1 Modeling 644.3.2 Simulation 644.3.3 Optimization 654.4 Mechanical Challenges 674.5 Thermal Challenges 684.6 Thermomechanical Challenges 72

Acknowledgments 77References 77

Contents vii

5 Physical Design Flow for 3D/CoWoS® Stacked ICs 81Yu-Shiang Lin, Sandeep K. Goel, Jonathan Yuan, Tom Chen, and Frank Lee

5.1 Introduction 815.2 CoWoS® vs. 3D Design Paradigm 825.3 Physical Design Challenges 835.4 Physical Design Flow 855.4.1 RC Extraction and TSV Modeling 855.4.2 Interposer Connectivity Checking Technique (LVS) 875.4.3 Interposer Interface Alignment Checking 885.4.4 Cross-Die Timing Check 905.4.5 IR Drop Analysis for the Interposer 925.5 Physical Design Guideline 945.5.1 Interposer Wide Bus Routing Guideline 945.5.2 Interposer SI/PI Analysis for HBM Interface 975.5.3 Combo-Bump Design Style 1065.5.4 Chip-Package Co-Design for Stacked ICs 1095.5.5 Interposer Multi-Die ESD Protection Scheme 1105.6 TSMC Reference Flows 1135.7 Conclusion 114

References 114

6 Design and CAD Solutions for Cooling and Power Delivery forMonolithic 3D-ICs 115Sandeep Samal and Sung K. Lim

6.1 Introduction 1156.2 New Thermal Issues in Monolithic 3D-ICs 1176.2.1 Material and Structural Differences 1186.2.2 Temperature Map Comparisons 1196.3 Fast Thermal Analysis with Adaptive Regression 1216.3.1 Initial Experiments 1216.3.2 Modeling Technique 1236.3.3 Sample Generation 1236.3.4 Simulation Results 1246.4 New Power Delivery Issues in Monolithic 3D-ICs 1266.4.1 Design and Analysis Setup 1266.4.2 Impact of PDN 1286.4.3 PDN Analysis Results 1316.5 Power Delivery Network Optimization 1346.5.1 Design Styles 1346.5.2 Full PDN Analysis Results 1356.5.3 PDN Design Guidelines for Monolithic 3D-ICs 1376.6 Conclusions 139

References 139

viii Contents

7 Electronic Design Automation for 3D 141Paul D. Franzon

7.1 Introduction 1417.2 EDA Flows for 3D-IC 1417.3 Commercial EDA Support 1437.4 Modular Partitioning Approaches 1437.5 Circuit Partitioning 1457.6 Conclusions 146

References 147

8 3D Stacked DRAM Memories 149Christian Weis, Matthias Jung, and Norbert Wehn

8.1 3D-DRAM Design Space and DRAM Technology Background 1508.1.1 DRAM Evolution 1508.1.2 Common DRAM Architecture 1528.1.3 Architecture Study of a 22 nm 4GB 3D-DRAM Cube 1558.1.4 DRAM Memory Controller 1588.2 Design Space Exploration of 3D-DRAMs 1608.2.1 3D-DRAM Behavioral Models 1608.2.1.1 Power Model Verification 1628.2.2 3D-DRAM Core Architecture and Technology 1648.2.2.1 Wiring and TSV Considerations 1658.2.3 3D-DRAM Architecture Exploration Results 1678.2.3.1 3D-DRAM Bank Exploration Results 1678.2.3.2 Complete 3D-DRAM Stack Results 1698.2.4 Flexible Burst Length and Bandwidth Interface for 3D-DRAMs 1728.2.4.1 Experimental Results 1738.2.4.2 Subsystem Power and Energy Estimation 1758.3 Architectural 3D Stacked DRAM Controller Optimizations 1768.3.1 Temperature-Aware Refresh Control for 3D Stacked DRAMs 1778.3.2 Advanced 3D Stacked DRAM Power-Down Policies 1788.3.2.1 Staggered Power Down for Standard DDR3 DRAMs 1798.3.2.2 Bankwise Staggered Power Down for WideIO DRAMs 1828.4 Conclusion 183

References 184

Part II Test 187

9 Cost Modeling for 2.5D and 3D Stacked ICs 189Mottaqiallah Taouil, Said Hamdioui, and Erik Jan Marinissen

9.1 Introduction 1899.2 Testing 3D Stacked ICs 1899.2.1 Importance of Testing 1899.2.2 Test Moments and Test Flows 1909.3 Cost Modeling 1919.3.1 Cost Classification 1919.3.2 Design Cost 191

Contents ix

9.3.3 Manufacturing Cost 1919.3.4 Test Cost 1929.3.5 Packaging Cost 1929.3.6 Logistics Cost 1939.4 3D-COSTAR 1939.4.1 Tool Inputs and Outputs 1949.4.2 Tool Flow 1949.5 Case Studies 1969.5.1 Reference Cases 1969.5.2 Experiments 1989.5.2.1 Fault Coverage of Interposer Pre-Bond Testing 1989.5.2.2 Mid-Bond Testing and Logistics 1999.5.2.3 Dedicated Probe Pads vs. Micro-Bump Probing 2009.5.3 Fault Coverage of Interposer Pre-Bond Testing 2029.5.4 Mid-Bond Testing and Logistics 2049.5.5 Dedicated Probe Pads vs. Micro-Bump Probing 2049.6 Conclusion 207

References 207

10 Interconnect Testing for 2.5D- and 3D-SICs 209Shi-Yu Huang

10.1 Introduction 20910.2 Pre-Bond TSV Testing 21110.2.1 General Test Methods for Pre-Bond TSVs 21110.2.2 Leakage Test by Voltage Conversion and Comparison 21310.2.3 Charge-and-Sample-Based Pre-Bond TSV Test 21410.2.4 Input Sensitivity Analysis (ISA)-Based Oscillation Test 21610.2.4.1 Electrical Effect of a Resistive Open Fault 21610.2.4.2 Electrical Effect of a Leakage Fault 21610.2.4.3 Test Structure 21710.2.4.4 Fault Detection Scheme 21810.2.4.5 Impact of Process Variation 21910.3 Post-Bond Interconnect Testing 22010.3.1 Direct Measurement 22010.3.2 Voltage-Divider-Based Test 22110.3.3 Pulse-Vanishing Test (PV Test) 22210.3.4 Characterization-Based Test Method via VOT Scheme 22510.4 Concluding Remarks 227

References 228

11 Pre-Bond Testing Through Direct Probing of Large-ArrayFine-Pitch Micro-Bumps 231Erik Jan Marinissen, Bart De Wachter, Jörg Kiesewetter, and Ken Smith

11.1 Introduction 23111.2 Pre-Bond Testing 23211.3 Micro-Bumps 23411.4 Probe Technology 236

x Contents

11.4.1 Probe Cards 23611.4.2 Probe Station 23811.5 Test Vehicle: Vesuvius-2.5D 23911.6 Experiment Results 24211.6.1 Initial Hurdles 24211.6.2 Probe Marks 24311.6.3 PTPA Accuracy 24511.6.4 Contact Resistance 24711.6.5 Probe Impact on Stack Interconnect Yield 24811.7 Conclusion 249

Acknowledgments 249References 250

12 3D Design-for-Test Architecture 253Erik Jan Marinissen, Mario Konijnenburg, Jouke Verbree, Chun-Chuan Chi,Sergej Deutsch, Christos Papameletis, Tobias Burgherr, Konstantin Shibin,Brion Keller, Vivek Chickermane, and Sandeep K. Goel

12.1 Introduction 25312.2 Basic 3D-DfT Architecture 25412.3 Vesuvius-3D 3D-DfT Demonstrator 25712.3.1 Vesuvius-3D Technology 25712.3.2 3D-DfT Demonstrator Design 25812.3.3 3D-DfT Demonstrator Results 26312.4 Extensions to the Basic 3D-DfT Architecture 26512.4.1 Multi-tower Stacks 26512.4.2 Test Data Compression 26712.4.3 Hierarchical SoCs Containing Embedded Cores 26912.4.4 At-Speed Interconnect Testing 27012.4.5 Memory-on-Logic Stacks 27212.5 Conclusion 276

Acknowledgments 276References 277

13 Optimization of Test-Access Architectures and Test Schedulingfor 3D ICs 281Sergej Deutsch, Brandon Noia, Krishnendu Chakrabarty, and Erik JanMarinissen

13.1 Uncertain Parameters in Optimization of 3D Test Architecture andTest Scheduling 282

13.2 Robust Optimization of 3D Test Architecture 28513.2.1 Mathematical Model for Robust Co-optimization of Test Architecture

and Test Scheduling 28613.2.2 Heuristic Method for Robust Optimization Based on Simulated

Annealing 29013.3 Simulation Results 29413.4 Conclusion 299

References 299

Contents xi

14 IEEE Std P1838: 3D Test Access Standard UnderDevelopment 301Adam Cron, Erik Jan Marinissen, Sandeep K. Goel, Teresa McLaurin, andSandeep Bhatia

14.1 Introduction 30114.2 Overview 30314.2.1 History 30314.2.2 PAR Summary 30314.2.3 Status 30414.3 Scope and Terminology 30414.4 Serial Control 30614.4.1 Initial 1500 vs. 1149.1 Discussion 30614.4.2 1149.1 Serial Data Path 30914.4.3 TLR Hold-Off Bit 31014.5 Die Wrapper Register 31114.5.1 Die Wrapper Requirements 31314.5.2 Shared vs. Boundary Wrapping and Stack Considerations 31414.5.3 Wrapper Cell Options 31614.6 Flexible Parallel Port 31714.6.1 FPP Structure 31814.6.2 FPP Control Signals 31914.6.3 FPP Configurations 32014.6.4 Usage Scenarios 32014.7 Conclusion 322

References 322

15 Test and Debug Strategy for TSMC CoWoS® StackingProcess-Based Heterogeneous 3D-IC: A Silicon Study 325Sandeep K. Goel, Saman Adham, Min-Jer Wang, Frank Lee, Vivek Chickermane,Brion Keller, Thomas Valind, and Erik Jan Marinissen

15.1 Introduction 32515.2 Overview of CoWoS® Stacking Process 32715.3 CoWoS® Chip Architecture 32715.3.1 SoC Die 32915.3.2 JEDEC WideIO DRAM Die 32915.3.3 DRAM Die 32915.4 Test and Diagnosis Architecture 32915.4.1 Known-Good-Die (KGD) Test 33015.4.2 Known-Good-Stack (KGS) Test 33015.4.3 Interconnect Test ATPG 33315.5 Testing of Passive Silicon Interposer 33615.6 Experimental and Silicon Results 34015.6.1 Interconnect Failure Diagnosis 34115.6.2 Cause and Effect Analysis 34315.7 Conclusion 345

References 345

xii Contents

Part III Thermal Management 347

16 Thermal Isolation and Cooling Technologies forHeterogeneous 3D- and 2.5D-ICs 349Yang Zhang, Hanju Oh, Yue Zhang, Li Zheng, Gary S. May, andMuhannad S. Bakir

16.1 Thermal Challenges for Heterogeneous 3D-ICs 34916.1.1 A 3D-IC Architecture for Thermal Decoupling Using Air-Gap

Isolation and Thermal Bridge 35016.1.2 Thermal Evaluation of the Proposed Architecture 35116.1.3 Impact of TSVs on the Proposed Architecture 35416.1.4 Experimental Demonstration 35516.2 Thermal Challenges and Solutions for 2.5D-ICs 35916.2.1 Thermal Comparison of Interposer and Bridge-Chip 2.5D

Integration 35916.2.2 Impact of Die Thickness Mismatch and Die Spacing on 2.5D

Integration 36116.2.3 Thermal Solutions Using Integrated Die-Level MFHS 36216.3 Electrical and Fluidic Micro-Bumps 36316.3.1 Fabrication Flow 36316.3.2 Assembly, Testing, and Characterization 36416.4 High Aspect Ratio TSVs Embedded in A Micropin Fin Heat Sink 36716.4.1 Fabrication and Testing 36916.5 Conclusion 371

References 371

17 Passive and Active Thermal Technologies: Modeling andEvaluation 375Craig E. Green, Vivek Sahu, Yuanchen Hu, Yogendra K. Joshi,and Andrei G. Fedorov

17.1 Introduction 37517.2 Integrated Background Heat Sink Approaches 37617.2.1 Single-Phase 3D-IC Cooling 37617.2.2 Two-Phase (Flow Boiling) Cooling 38317.3 Solid-State Cooling 38417.3.1 Thermoelectric Cooler (TEC) Design Principles 38617.3.2 Thin Film Coolers 38717.3.3 Conventional Thermoelectric vs. Thin Film Coolers 38917.3.4 Modeling of Thin Film Coolers 38917.3.5 Transient Behavior of Thin Film Cooler 39117.4 Passive Cooling: Phase Change Material Regeneration Concerns 39317.4.1 Three-Dimensional Model for a CTC Integrated into a Three-Layer

Stack with SSC Regeneration 39517.4.2 Experimental Setup 39717.4.2.1 Thermoelectric Cooler Regeneration Setup 39917.4.2.2 Fan Cooling Regeneration 40017.4.2.3 Liquid Cooling Regeneration 401

Contents xiii

17.4.3 Device Operation and Characterization Process 40117.4.4 Results 404

References 409

18 Thermal Modeling and Model Validation for 3D StackedICs 413Herman Oprins, Federica Maggioni, Vladimir Cherman, Geert Van der Plas,and Eric Beyne

18.1 Introduction 41318.2 Modeling Methods for the Thermal Analysis of 3D Integrated

Structures 41318.2.1 Package-Level Numerical Simulations (FEM/CFD) 41418.2.2 Compact Thermal Models (CTMs)/Fast Thermal Models (FTMs) 41618.2.2.1 Resistance–Capacitance Networks (White Box) 41618.2.2.2 Analytical and Semi-analytical Solutions (White Box/Gray Box) 41718.2.2.3 Green’s Function-Based Models (White Box/Gray Box) 41818.2.3 Full-Chip Layout-Based Thermal Simulations 41918.3 3D Stacked Thermal Test Vehicles 42118.3.1 Uniform Power Dissipation Measurements 42118.3.2 Hotspot-Based Thermal Test Chip 42218.3.3 Full CMOS Test Chip with Programmable Power Map 42418.4 Experimental Validation of Thermal Models for 3D-ICs 42518.5 Inter-die Thermal Resistance 42818.5.1 Experimental Characterization 42818.5.2 Modeling Study 429

References 430

19 On the Thermal Management of 3D-ICs: From Backside toVolumetric Heat Removal 433Thomas Brunschwiler, Gerd Schlottig, Chin L. Ong, Brian Burg, andArvind Sridhar

19.1 Introduction: Density Scaling Drives Compute Performance andEfficiency 433

19.2 Thermal Management Landscape for 3D-ICs 43419.3 Advances on Thermal Interfaces: Percolating Thermal Underfills 43719.4 Single-Phase Interlayer Cooling: Design Rules Toward

Extreme 3D 43819.4.1 Interlayer Cooling Aware Chip Stack Design 43819.4.2 Extreme 3D Enabled by Interlayer Cooling 44119.5 Applicability of Two-Phase Cooling for 3D-ICs 44319.5.1 Single vs. Two-Phase Cooling Implementations 44419.5.2 3D-ICs Interlayer Cooling 44519.5.3 Thermal Resistance, Pressure Drops, Local Junction, and Fluid

Temperatures 44619.5.4 Novel Radial Hierarchical Fluid Network for Two-Phase Interlayer

Heat Transfer 446

xiv Contents

19.6 Compact Thermal Modeling Framework 44819.6.1 Compact Thermal Modeling for Air-Cooled ICs 44819.6.2 3D-ICE: A Compact Thermal Model for Single-Phase

Liquid-Cooled ICs 44819.6.3 STEAM: A Compact Thermal Model for Two-Phase

Liquid-Cooled ICs 44919.7 Consequence of Fluid Presence for the Package Topology 44919.7.1 Sealing Design 45019.7.2 Additional Loads 45019.7.3 Stress Testing 45219.7.4 System Link and Field Replacement 45319.8 Thermal Laminates Enabling Dual-Side Cooling and Electrical

Interconnects 45319.8.1 Thermal-Power Insert Enabling Dual-Side Cooling 45319.8.2 Thermal Power Plane Enabling Dual-Side Electrical

Interconnects 455References 456

Index 461

xv

Introduction to Design, Test and Thermal Management of3D Integrated Circuits

When we started to work on the first volume of Wiley’s Handbook of 3DIntegration in 2007, we intended these volumes to be an encompassing treatiseon 3D integration – a new technical field of semiconductor technology andelectronic systems packaging. This ambitious goal of Wiley-VCH and the editorswas achieved with the help of Christopher Bower who served as co-editor of thefirst two volumes. We chose to initially focus on 3D-IC process technology, suchas fabrication of through-silicon vias (TSVs) and wafer thinning and temporaryand permanent bonding technologies.

Volume 3, released in 2014, continued coverage of new developments inprocess technology as future production was still on the horizon. We felt thatvolume 4 should be strongly dedicated to design, test, and thermal managementof 3D-IC.

Since the mid-2010s, 3D integration and silicon interposer technologieshave become well-accepted approaches for fabrication of high-performancememory-enhanced products, explicitly stacked DRAMs, which are currentlyin high-volume production at both Samsung and Hynix. Samsung started theproduction of “3D Stacked DDR4 DRAM” with via-middle technology in August2015. So finally, after more than three decades of R&D, 3D-IC integration hasarrived in the electronic industry!

Another application that has gone into volume production is CMOS imagesensors (CIS). In 2017 Sony announced the industry’s first three-layer stackedCIS: a 90 nm generation back-illuminated CIS top chip, 30 nm generation DRAMmiddle chip, and 40 nm generation image signal processor (ISP) bottom chip forsmartphone cameras. All of the other major CIS manufacturers are followingsuite.

On the other hand, there have also been drawbacks. Most significantly, 3Dmemory-on-logic applications, widely predicted by many sources, have beenpostponed several times and will be still not introduced in 2019. While the majorissue, of course, is the high cost of 3D-IC manufacturing, another reason forpostponing the introduction has been the success of TSV interposer technology.These, also called “2.5D” concepts, enable a high interconnection densitybetween side-by-side devices, through TSV and redistribution layers, withoutintroducing “true 3D integration” (i.e., TSV interconnects through stackedactive devices). Considering TSV interposer technologies as well, the market has

xvi Introduction to Design, Test and Thermal Management of 3D Integrated Circuits

exceeded US$ 4 billion in 2016, and the forecast for TSV-based products for thedifferent applications appears to be very promising (Figure 1).

One of the most promising silicon interposer approaches has been TSMC’sCoWoS (Chip-on-Wafer-on-Substrate). The CoWoS technology has been in pro-duction since 2013 with one of the first applications being Xilinx’s FPGAs. TheCoWoS concept opened a new track in the roadmap toward 3D-IC production,such as the Xilinx Virtex-7 product H580T, labeled the “first heterogeneous 3DFPGA”.

In addition to the above developments, industrial consortia have been target-ing 3D integration as a key technology for heterogeneous IC/MEMS products,demanding smart system integration rather than extreme high interconnect den-sities (as early as already established in 2013, the European e-BRAINS platform).Heterogeneous integration technologies are being developed for functionaldiversification systems, for example, integration of CMOS with other devices,such as analog/RF, solid-state lighting, HV power, passives, sensors/actuators,chemical and biological sensors, and biomedical devices. This heterogeneousintegration started with system-in-packaging technology and is expected toevolve into 3D heterogeneous integration. Many R&D activities worldwide arefocusing on heterogeneous integration for novel functionalities. Corresponding3D integration technologies are in evaluation at several companies, researchinstitutions, and industrial-driven research consortia.

Recently, three new relevant international roadmap initiatives have started,highlighting heterogeneous 3D integration as a key element: the InternationalRoadmap for Devices and Systems (IRDS), as follow-up of ITRS, directed byPaolo Gargini (IEEE SSCS, a.o.); the Heterogeneous Integration Roadmap (HIR),initiatively directed by William Chen (Semi, IEEE EPS a.o.); and furthermore

5 000 000Memory cube Si interposer

Imaging deviceALSRF filters

3D SoCAccelerometerFPSOther MEMS and sensors

4 500 000

4 000 000

3 500 000

3 000 000

2 500 000

2 000 000

1500 000

1000 000

500 000

02016 2017 2018 2019 2020 2021 2022

Figure 1 Revenue forecast TSV-based products by application. Source: 3D TSV and 2.5DBusiness Update – Market and Technology Trends Report, Yole Développement, 2017.

Introduction to Design, Test and Thermal Management of 3D Integrated Circuits xvii

NanoElectronics Roadmap for Europe: Identification and Dissemination(NEREID) (funded by the European Commission). Including as well Sensorand MEMS/IC applications, a main subject of HIS and NEREID is clearly onheterogeneous systems. While targeting more on computing applications, theIRDS predicts an area of so-called 3D power scaling with transition to verticaldevice structures and heterogeneous integration to become the key technologydriver in the years 2025–2040.

To summarize, dedicated 3D integration technologies are today in a ramp-upphase toward high volume production. Nevertheless, there is still a huge amountof related problems, e.g. thermal issues, design and test issues, materials opti-mization, robustness of the processes, thermomechanical reliability of the sys-tems, and last but not the least high production costs, which can only be solvedby significant development efforts.

For this volume, we invited Paul D. Franzon (NCSU) for “Design,” Erik JanMarinissen (IMEC) for “Test,” and Muhannad S. Bakir (Georgia Institute of Tech-nology) for “Thermal Management” to serve as co-editors. They succeeded inassembling excellent contributions from both academic and industrial practition-ers in these three key areas of interest. The book is organized into three corre-sponding parts:

Part I: DesignPaul D. Franzon (editor)Contributions from Fraunhofer, Georgia Institute of Technology, IMEC,KaiserslauternUniversity, Kobe University, NCSU, and TSMCPart II: TestErik Jan Marinissen (editor)Contributions from ARM, Cadence Design Systems, Duke University,FormFactor, Google, IMEC, NTHU, Synopsys, TSMC, and TU DelftPart III: Thermal ManagementMuhannad S. Bakir (editor)Contributions from Georgia Institute of Technology, IBM, IMEC

We would like to acknowledge the three co-editors for putting together theirparts of the book, the reviewers, and all authors for their chapters. We are deeplygrateful for their time and efforts they each put into their contributions.

On behalf of all editors and authors, we like to acknowledge the Wiley-VCHteam who greatly supported us, especially Waltraud Wuest and Nina Stadthaus.

July 2018 Philip GarrouMicroelectronic Consultants of NCResearch Triangle Park, NC, USAMitsumasa KoyanagiTohoku UniversitySendai, JapanPeter RammFraunhofer EMFTMunich, Germany

1

Part I

Design

3

1

3D Design StylesPaul D. Franzon

North Carolina State University, 2410 Campus Shore Dr., Raleigh, NC 27606, USA

1.1 Introduction

3D-IC and interposer technologies have demonstrated their capability to reducesystem size and weight, improve performance, reduce power consumption,and even improve cost as compared with baseline 2D integration approaches.Though not a replacement for Moore’s law, 3D technologies can providesignificant improvements in performance per unit of power and performanceper unit of cost. The main purpose of this chapter is to provide an overview ofproduct and design scenarios that uniquely leverage 3D-IC technologies in 3Dspecific ways.

The structure of this chapter is as follows. First, we do a quick review of the 3Dtechnology set. Then we review the main design drivers for using 3D technolo-gies: (i) miniaturization, (ii) provisioning power effective memory bandwidth,(iii) improving performance/power of logic, and (iv) heterogeneous integrationfor cost reduction to enable unique system capabilities.

1.2 3D-IC Technology Set

There are several technology components that can be mixed and matched in the3D technology set. The purpose of this section is not to review these in detail, butto introduce them. Other books in this series focus on the technology.

The main 3D-IC technologies of interest are illustrated together inFigures 1.1–1.4. Interposers (Figure 1.1) are so called because they are placedor posed in between the chip and the main laminate package. Using interposersis often referred to as 2.5D integration. A common way to make interposersis to use silicon processing technologies to create a microscale circuit board.Through-silicon vias (TSVs) are fabricated in a silicon wafer, and multiple metallayers are then fabricated on top. These metal layers can be fabricated withthin film processing, typically giving 3–6 metal layers up to a few micrometers

Handbook of 3D Integration: Design, Test, and Thermal Management, First Edition.Edited by Paul D. Franzon, Erik Jan Marinissen, and Muhannad S. Bakir.© 2019 Wiley-VCH Verlag GmbH & Co. KGaA. Published 2019 by Wiley-VCH Verlag GmbH & Co. KGaA.

4 1 3D Design Styles

Interposer

Micro-bumpWiring layers

Through-silicon vias (TSV)sBumps

Typical dimensions: Interposer thickness : 100 μmMicro-bump pitch : 25 μm +Wiring layers: 4–6 layers; submicron to multi-μm thickness

Typically 1–10 μm width and spaceBump pitch: 150 μm +

Figure 1.1 Interposer or 2.5D integration.

Redistribution layer (RDL)

Micro-bumpWiring layers

Base CMOS wafer

Typical dimensions: Interposer thickness : 100 μmMicro-bump pitch : 25 μm +Wiring layers: 1–3 layers; submicron to multi-μm thickness

Typically 1–10 μm width and space

Bumps

Figure 1.2 Redistribution layer.

thick, or can be fabricated with integrated circuit back-end-of-line (BEOL1)techniques, giving 4–6 thinner but planarized metal layers. The latter approachusually reuses a legacy BEOL process, e.g. from the 65 nm technology node.Micron-scale line width and space can be readily achieved. The interposer isusually thinned to 100 μm. Thus 100 μm long TSVs are used to connect themetal layers to the package underneath. The pitch of the TSVs is also typicallyaround 100 μm. Chips are flipped bumped to the top of the interposer, and theinterposer connects them to each other and the outside world. The bump pitchbetween the chip and the interposer can be relatively tight, down to 25 μm,but the interposer package chip must be at conventional scales, typically in the150+ μm range. The chips on top of the interposer can be single die or multi-chipstacks themselves.

1 The front end of line refers to transistor fab, which is usually done before metal interconnect fab,which is thus called BEOL.

1.2 3D-IC Technology Set 5

3D chip stack

Micro-bumps or direct bondTransistor/wiring layers

Through-silicon vias (TSV)sMicro-bumps to package or

interposer

Typical dimensions: Thinned chip : 25–50 μmUnthinned chip : 300 μmMicro-bump pitch : 25 μm +Direct bond pitch : 3 μm +Through-silicon via (TSV) diameter : 5–10 μmTSV pitch : 25 μm +

Figure 1.3 3D-IC chip stacking technology set.

MetalTransistors

OxideEpi

Buried oxide

Bulk silicon

(1) Oxide–oxide bond (2) Silicon etch (3) Via formation

(4) Repeat

Figure 1.4 3D integration in silicon on insulator technology.

Another interposer technology under active investigation is to use glass as asubstrate rather than silicon. Then potentially large panel processing techniques,such as those used to make television screens, can be used, and price reductionachieved.

A related technology is to create interconnect on top of an already finishedCMOS wafer and use that to connect to chips and inputs/outputs. This is illus-trated in Figure 1.2. Additional thin film wiring layers are processed on top ofa completed CMOS wafer to connect the chips in that wafer to chips that areplaced on top, together with the chip stack IO. It is referred to as a redistribu-tion layer (RDL) as the CMOS wafer IOs are redistributed. Not as many wiringlayers are possible as with interposers. One application of RDL technology is to

6 1 3D Design Styles

make a chip stack of a larger die, e.g. a memory stack, to a smaller die, e.g. aprocessor.

An exemplar 3D chip stack, or 3D-IC, is shown in Figure 1.3. This illustrates athree-chip stack, two of which incorporate TSVs. The top two chips illustrated inthis stack are mated face to face (F2F). That is, the transistor and wiring layersare directly mated. This mating can be done with solder bumps or with a ther-mocompression or direct bonding technology. The latter technologies have beendemonstrated down to 3 μm pitch and have potential for 1 μm pitch. An exampleof a copper direct bond interconnect technology can be found in [1]. This permitsa very high interconnect density between the two chips. These F2F connectionscan be leveraged in multiple ways to enable higher-performance and lower powerlogic stacks.

TSVs can be used to connect the face of one chip, through the back of another tothe transistor/wiring layer, or to connect chip stack IO through a chip backside.Thus they can connect a chip face to back (F2B, shown in Figure 1.3 betweenthe bottom two chips) or even back to back (B2B, not shown). TSVs are madeusing techniques that create very vertical vias through the bulk silicon substrate.They have a lower density than an F2F connection but are important for creat-ing chip stacks. For example, the TSVs shown in Figure 1.3 connect the primaryIO and power grounds at the bottom up through the chip stack. The layers withTSVs have to be thinned. The chip stack often includes one unthinned layer formechanical stability (though this is not a requirement).

A fourth option that is only possible in a silicon on insulator (SOI) technol-ogy is shown in Figure 1.4. In this approach, fabricated wafers are joined F2Fusing an oxide–oxide bond. Since the transistors are built on top of an oxidelayer, a silicon-selective back etch can be used to remove the silicon part of theSOI substrate while not affecting the transistors and interconnect layers. Sim-ple through-oxide vias can then be used to create vertical connections betweenwhat were previously separate chips. An example of this process can be found in[2]. If the first two chips in the stack are fabricated without interconnect, thenone gets two directly connectable transistor layers in what would be considereda monolithic 3D technology.

1.3 Why 3D

Table 1.1 presents a summary of potential drivers for 3D integration. The desirefor thinner smartphone cameras has resulted in the first mainstream high vol-ume use of 3D technologies. However, such miniaturization can also be used forother image sensors and for smart dust sensors. Provisioning large amounts ofpower effective memory bandwidth appears to be the next volume applicationof 3D technologies. In contrast, logic stacking or logic-on-memory stacking hashad strong but unrealized potential for improving system performance/power.Finally, 3D offers unique opportunities for heterogeneous integration of differenttechnologies.

Each of these potential design drivers will be explored in detail in the next foursections.

1.4 Miniaturization 7

Table 1.1 Issues that are potential drivers for 3D integration.

Driving issue Case for 3D Caveats

Miniaturization Stacked memoriesSmart dust sensorsImage sensors

For many smart dustcases, stacking and wirebonding is sufficient

Memorybandwidth

3D memory can dramatically improvememory bandwidth and powerconsumption

Stacking memory onlogic has thermal issues

Interconnectdelay, bandwidth,and power

Length of critical paths can be substantiallyreduced through 3D integration, or benefitcan be made of massive vertical bandwidth

Not all cases have asubstantial advantage

In certain cases, a 3D architecture mighthave substantially lower power orperformance/power over a 2D architecture

Thermal issues can besolved with carefulfloor planning and/orliquid cooling

Mixed technology(heterogeneous)integration

Tightly integrated mixed technology (e.g.III–V on silicon or analog on or next todigital) can bring many system advantagesin performance and cost

1.4 Miniaturization

Obviously, 3D stacking technologies using thinned silicon have direct potentialto reduce system volume. An early application of TSVs was for providing the IOconnections cell phone camera frontside imaging sensor (http://image-sensors-world.blogspot.com/2008/09/toshiba-tsv-reverse-engineered.html; http://www.semicontaiwan.org/en/sites/semicontaiwan.org/files/docs/4._mkt__jerome__yole.pdf). The goal was not to leverage 3D chip stacks – these were singledie – but to reduce the overall sensor height, at least when compared withconventional packaging approaches.

More recently Sony has leveraged a copper–copper direct bonding technol-ogy to create an image sensor as a two-chip stack [3], (http://www.sony.net/SonyInfo/News/Press/201201/12-009E/index.html, http://www.3dic.org/3D_stacked_image_sensor). One chip is a backside-illuminated pixel array thatdoes not include interconnect layers or even complete CMOS transistors. Thesecond chip is a complete CMOS chip on which is built the analog-to-digitalconverters (ADCs) and interconnect for all other functionality required of animage sensor. This approach leverages the high density capability of a directbonding technology since pixel-scale vertical interconnect is required. Sinceonly one of the two chips goes through a full CMOS fab, there is potential forcost reduction in comparison with a 2D sensor of the same total area having togo through a full CMOS fab. In contrast, here, the sensor-only chip should besubstantially smaller per square millimeter. In addition, the volume is reducedsubstantially through a smaller footprint. This image sensor is probably the firsthigh volume application incorporating a full 3D-IC chip stack.

http://image-sensors-world.blogspot.com/2008/09/toshiba-tsv-reverse-engineered.htmlhttp://image-sensors-world.blogspot.com/2008/09/toshiba-tsv-reverse-engineered.htmlhttp://www.semicontaiwan.org/en/sites/semicontaiwan.org/files/docs/4._mkt__jerome__yole.pdfhttp://www.semicontaiwan.org/en/sites/semicontaiwan.org/files/docs/4._mkt__jerome__yole.pdfhttp://www.semicontaiwan.org/en/sites/semicontaiwan.org/files/docs/4._mkt__jerome__yole.pdfhttp://www.sony.net/SonyInfo/News/Press/201201/12-009E/index.htmlhttp://www.sony.net/SonyInfo/News/Press/201201/12-009E/index.htmlhttp://www.3dic.org/3D_stacked_image_sensorhttp://www.3dic.org/3D_stacked_image_sensor

8 1 3D Design Styles

Layouts Die photo

Figure 1.5 Food processing sensor.

In the research domain a number of 3D image sensors have been demon-strated – too many to summarize here. Separating the image and processinglayers leads to the potential for improved performance in terms of sensitivity(larger pixels), frame rate (e.g. faster or more ADCs in the CMOS layer), andintegrated advanced processing (e.g. edge detection for robotics).

Another interesting use of 3D technologies has been to build non-visiblelight sensors, sometimes using a non-silicon technology for the sensing layer.Examples include IR imagers, X-ray imagers [4], and other images for high energyphysics investigations (http://meroli.web.cern.ch/meroli/DesignMonoliticDetectorIC.html).

3D-IC has been explored for non-image sensors. 3D chip stacking can be usedto make such sensors with low integrated volume. Though fabricated using wirebonding, Chen et al. demonstrated an integrated power harvesting data collect-ing sensor with the photovoltaic power harvesting chip mounted on top of thelogic and RF chips [5]. This maximizes the photovoltaic power harvesting areawhile minimizing the volume. TSVs and bonding technologies would permit fur-ther volume reduction. Lentiro [6] describes a two-chip stack aimed at simulatinga particle of meat for the purposes of calibrating a new food processing system.One chip is an RFID power harvester and communication chip, and the second isthe temperature data logger (Figure 1.5). It is a two-chip stack with F2F connec-tions and TSV-enabled IO. It is integrated with a small battery for data collectionpurposes only as the RFID cannot be employed in the actual processing pipes. Thetwo-chip stack permits smaller imitation food particles than otherwise would bethe case.

1.5 Memory Bandwidth

Memory is positioned as the next large volume application of 3D-IC technologies.To date DRAM has relied on one-signal-per-pin signaling using low cost, low pincount, and single chip plastic packaging. As a result, DRAM has continued to laglogic in terms of bandwidth potential and power efficiency. Furthermore, the IOspeed of one-signal-per-pin signaling schemes is unlikely to scale a lot beyond

http://meroli.web.cern.ch/meroli/DesignMonoliticDetectorIC.htmlhttp://meroli.web.cern.ch/meroli/DesignMonoliticDetectorIC.htmlhttp://meroli.web.cern.ch/meroli/DesignMonoliticDetectorIC.html

1.5 Memory Bandwidth 9

what can be achieved today in double data rate DDR4 (up to 3.2Gbps per pin) andgraphics GDDR6 (8Gbps). Beyond these data rates, two-pins-per-signal differen-tial signaling is needed. Furthermore, the IO power consumption, measured asmW/Gbps, is relatively high, even for the LPDDR standards (intended for mobileapplications).

Thus there are multiple 3D-IC enabled memory solutions available in themarket, all of which offer improved data bandwidth and power efficiencyover conventional memories. These include the hybrid memory cube (HMC),high bandwidth memory (HBM), WideIO, and Tezzaron disintegrated RAM(DiRAM). These are summarized in Figure 1.6 and Table 1.2. Note that in thetable, B (byte) and b (bits) are both used. Also note that 1 mW/Gbps is equivalentto 1 pJ/bit.

The HMC is a joint Intel–Micron standard that centers on a 3D stacked partincluding a logic layer and multiple DRAM layers organized as independent verti-cal slices. This 3D chip stack is then provided as a packaged part, so the customerdoes not have to deal with any 3D-IC or 2.5D packaging issues. At the time ofwriting this chapter, Micron offers 2GB and 4GB parts with a maximum memory

DRAM layersVertical sliceLogic layer- Crossbar- Controller - SerDESPackage

Hybrid memory cube

DRAM half bankTSV arrayLogic layer- Controller- 8 x 128 bit channelsMicro-bump IO(48 x 55 μm pitch)

Wide IO

DRAM half bankTSV arrayMicro-bump IO

DRAM subarray layersLogic layer- Global sense amps,

- Defect management

High bandwidth memory

DiRAM

deocoders

Figure 1.6 3D DRAMs.

Table 1.2 Comparison of 2D and 3D memories.

Technology Capacity BW (GBps)Power(W)

Efficiency(mW/GBps)

IO efficiency(mW/Gbps) DQ count

DDR4-2667 4GB 21.34 6.6 309 6.5–39 32LPDDR4 4GB Up to 42 5.46 130 2.3 32HMC 4Gb 128GBps 11.08 86.5 10.8 8 Serdes lanesHBM 16Gb 256GBps 48 1024WideIO 8–32Gb 51.2GBpsa) 42b) 256DiRAM4 64Gb 8Tbps 4096

a) WideIO2. WideIO1 was half of this.b) WideIO1. WideIO2 should be lower.

10 1 3D Design Styles

bandwidth of up to 160GBps (the 128GBps part is used in Table 1.2). The dataIO is organized as an eight high-speed serial channels or lanes. HMC is mainlyaimed at computing applications.

The HBM is a JEDEC (i.e., industry-wide) standard that is intended for inte-gration via an RDL, 3D-IC stacking, or interposer to logic. It has a lot of dataIO (DQ) pins, configured as 8×128-bit wide interfaces with each pin running atup to 2Gbps. Connecting this large number of pins (placed on a 48 μm × 55 μmgrid) is the reason why it has to be integrated via an RDL, interposer, or direct 3Dstacking. It is fabricated as a stack of multibank memory die, connected to a logicdie through a TSV array, the TSV arrays running through the chip centers. Eachchip is F2B mounted to the chip beneath it. The eight channels are operated inde-pendently. Details for a first-generation HBM (operating at 3.8 pJ/bit power levelat 128GBps) can be found in [7]. The use of HBM in graphics module productshas been announced by Nvidia and AMD.

WideIO is also a JEDEC-supported standard, aimed largely at low powermobile processors. While intended to be mounted on top of the logic die in atrue 3D stack, side-by-side integration on an interposer is also possible. WideIOis a DRAM-only stack – there is no logic layer. Instead the DRAM stack isexposed through a TSV-based interface, and the memory controller is designedseparately on the CPU/logic die that is customer designed. An example is theST/CEA WideIO1 test vehicle [8]. It also supports multiple independent mem-ory channels, operating at up 800Mbs/pin. For example, the Samsung WideIO2product supports four channels, each 64-bit wide operating at 800Mbs/pin. Thestandard is currently in its second generation (WideIO2), and a third is beingplanned. WideIO has yet to enjoy commercial success. To date the thermalchallenges of mounting a DRAM on an already hot mobile processor logic diehave been insurmountable, especially as it is desired to operate the DRAM at alower temperature than logic (85 ∘C for DRAM vs. 105 ∘C for logic) to controlleakage and refresh time. One potential solution is side-by-side integration onan interposer. WideIO has potential for employment in mobile processor-basedserver solutions as the thermal issues are easier to manage.

The Tezzaron DiRAM4 is a proprietary memory. It has 4096 data IO organizedacross 64 ports. It is intended only for 3D and interposer integration. It has aunique organization in that the logic layer is not only used for controller and IOfunctions but also houses the global sense amplifiers and addresses decoders thatin other 3D memories are on the DRAM layers. This permits faster operation forthese circuits. The DiRAM4 has potential for a very high bandwidth (up to 8Tbps)and fast random cycles (15 ns) [9]. DiRAM4 is being integrated into a number ofspecialized applications that benefit from its high bandwidth.

1.6 3D Logic

It has always been assumed that the next major employment of 3D-IC, after mem-ories, would be 3D logic, i.e., logic stacks. The argument is simple. On-chip wiringdominates the area, performance, and power consumption of many logic chips.3D logic stacking would shorten many of those wires, leading to power reduction,