half subtractor
DESCRIPTION
vhdl codeTRANSCRIPT
Utkarsh Mishra /101125/ A5 Page 7
Experiment-3
AIM: Design, synthesis and stimulate the half subtractor circuit using Xilinx
Software.
1. Data flow modelling
2. Structural flow modelling
3. Behavioral modelling
4. Mixed modelling
Software used: Xilinx 5.2i.
Activity-1: Write VHDL code using Data Flow Modeling
RTL Schematic
Simulation Result:
Synthesis Result:
Number of Slices: 1 out of 192
Delay: 8.234ns
Device Family: Spatan2
Activity 2: Write VHDL code using Behavioral Modeling.
RTL Schematic
Simulation Result:
Synthesis Result:
Number of Slices: 1 out of 192
Delay: 8.234ns
Device Family: Spatan2
Utkarsh Mishra /101125/ A5 Page 7
Activity 3: Write VHDL code using Structural Modeling .
RTL Schematic
Simulation Result:
Synthesis Result:
Number of Slices: 1 out of 192
Delay: 8.234ns
Device Family: Spatan2
Activity 4: Write VHDL code using Mixed Modeling
RTL Schematic
Simulation Result:
Synthesis Result:
Number of Slices: 1 out of 192
Delay: 8.234ns
Device Family: Spatan2
Conclusion:
Simulation result waveform are shown.
All the modelling is having equal number of slices i.e. 1 out of 192.
All the modelling is having equal amount of Delay i.e. 8.234ns.