gödöllő szabadság tér 12

1

CONTENTS

A. ANALOG PARTSAFETY PRECAUTIONS: ........................................................................................................................................... 3 TV set switched off ...................................................................................................................3 Measurements ...........................................................................................................................3

PERI-TV SOCKET ........................................................................................................................................................3 SCART 1 ..................................................................................................................................3 SCART 2 ..................................................................................................................................3

1. INTRODUCTION ......................................................................................................................................................4 2. SMALL SIGNAL PART WITH STV2248 .........................................................................4 2.1 Vision IF amplifier..............................................................................................................4 2.2 QSS Sound circuit (QSS versions) .....................................................................................4 2.3 FM demodulator and audio amplifier (mono versions) ......................................................4 2.4 Video switching ..................................................................................................................5 2.5 Synchronisation circuit .......................................................................................................5 2.6 Chroma and luminance processing .....................................................................................5 2.7 RGB output circuit ..............................................................................................................6 2.8 µ-Controller ........................................................................................................................7

3. TUNER ........................................................................................................................................................................74- DIGITAL TV SOUND PROCESSOR MSP34X0....................................................................................................85. SOUND OUTPUT STAGE TDA7266L/TDA7266 ...................................................................................................86. VERTICAL OUTPUT STAGE WITH TDA8174A .................................................................................................87. TRIPLE VIDEO OUTPUT AMPLIFIER TDA6107JF ..........................................................................................88. POWER SUPPLY (SMPS) ........................................................................................................................................89. POWER FACTOR CORRECTION .........................................................................................................................810. POWER CARD 11PW04-3, 11PW05..…………………………………………………………811. RGB SWITCHING CARD 11RGB30-3……………………...………………………………...912. SERIAL ACCESS CMOS 8K EEPROM 24C08 ...................................................................................................913. CLASS AB STEREO HEADPHONE DRIVER TDA1308 ................................................................................... 914. SAW FILTERS .........................................................................................................................................................915. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM ............................................................................. 9 ST92195................................................................................................................................10 STV224X ..............................................................................................................................11 UV1315, UV1316, UV1336,TECC2949PG40B,TAEA-G0XXD ,ChongQing QingJia......12 TDA7266/TDA7266L ..........................................................................................................14 TDA8174 ..............................................................................................................................15 TDA6107JF ..........................................................................................................................15 MC44608 ..............................................................................................................................16 MSP34X0G ..........................................................................................................................17 24C08....................................................................................................................................18 TDA1308 ..............................................................................................................................19 PI5V330………………………………………………………………………………….…20 SAW FILTERS.....................................................................................................................21

SERVICE MENU ADJUSTMENTS...........................................................................................................................21OPTIONS ......................................................................................................................................................................31GENERAL BLOCK DIAGRAM of 11AK30 ............................................................................................................. 37CIRCUIT DIAGRAMS................................................................................................................................................38

2

DO NOT CHANGE ANY MODULE UNLESS THE SET IS SWITCHED OFFThe mains supply part of the switch mode power supply’s transformer is live.Use an isolating transformer.The receiver complies with the safety requirements.

SAFETY PRECAUTIONS:The service of this TV set must be carried out by qualified persons only. Components

marked with the warning symbol on the circuit diagram are critical for safety and must only bereplaced with an identical component.- Power resistor and fused resistors must be mounted in an identical manner to the originalcomponent.- When servicing this TV, check that the EHT does not exceed 26kV.TV set switched off:Make short-circuit between HV-CRT clip and CRT ground layer.Short C809 before changing IC800 and IC801 or other components in primary side of the SMPSpart.

Measurements:Voltage readings and oscilloscope traces are measured under the following conditions:Antenna signal’s level is 60dB at the color bar pattern from the TV pattern generator. (100% white,75% color saturation)Brightness, contrast, and color are adjusted for normal picture performance.Mains supply, 220VAC, 50Hz.

PERI-TV SOCKET

- The figure of PERI-TV socket-

SCART 1 PINING

1 Audio right output 0.5Vrms / 1K2 Audio right input 0.5Vrms / 10K3 Audio left output 0.5Vrms / 1K4 Ground AF5 Ground Blue6 Audio left input 0.5Vrms / 10K7 Blue input 0.7Vpp / 75ohm8 AV switching input 0-12VDC /10K9 Ground Green10 -11 Green input 0.7Vpp / 75ohm12 -13 Ground Red14 Ground Blanking15 Red input 0.7Vpp / 75ohm16 Blanking input 0-0.4VDC, 1-3VDC / 75 Ohm17 Ground CVBS output18 Ground CVBS input

19 CVBS output 1Vpp / 75ohm20 CVBS input 1Vpp / 75ohm21 Ground

SCART 2 PINING

1 Audio right output 0.5Vrms / 1K2 Audio right input 0.5Vrms / 10K3 Audio left output 0.5Vrms / 1K4 Ground AF5 Ground Blue6 Audio left input 0.5Vrms / 10K7 Blue input8 AV switching input 0-12VDC /10K9 Ground Green10 -11 -12 -13 Ground Red14 Ground Blanking

3

15 -16 -17 Ground CVBS output18 Ground CVBS input

19 CVBS output 1Vpp / 75ohm20 CVBS input 1Vpp / 75ohm21 Ground

1. INTRODUCTION11AK30 is a 90° chassis capable of driving 20”/21” tubes at the appropriate currents. The chassisis capable of operating in PAL, SECAM and NTSC standards. The sound system is capable ofgiving 5 watts RMS output into a load of 8 ohms. One page, 7 page SIMPLETEXT, TOPTEXT,FASTTEXT and US Closed Caption is also provided. The chassis is equipped with a double-deck42 pin Scart connector.

2. SMALL SIGNAL PART WITH STV2248:STV2248 video processor is essential for realizing all small signal functions for a color TVreceiver.2.1 Vision IF amplifier3The vision IF amplifier can demodulate signals with positive and negative modulation. The PLLdemodulator is completely alignment-free. Although the VCO (Toko-coil) of the PLL circuit isexternal, yet the frequency is fixed to the required value by the original manufacturer thus theToko-coil does not need to be adjusted manually. The setting of the various frequencies (38.9 or45.75 MHz) can be made via changing the coil itself.

2.2 QSS Sound circuit (QSS versions)The sound IF amplifier is similar to the vision IF amplifier and has an external AGC de-couplingcapacitor. The single reference QSS mixer is realised by a multiplier. In this multiplier the SIFsignal is converted to the inter-carrier frequency by mixing it with the regenerated picture carrierfrom the VCO. The mixer output signal is supplied to the output via a high-pass filter forattenuation of the residual video signals. With this system a high performance hi-fi stereo soundprocessing can be achieved. The AM sound demodulator is realised by a multiplier. The modulatedsound IF signal is multiplied in phase with the limited SIF signal. The demodulator output signal issupplied to the output via a low-pass filter for attenuation of the carrier harmonics. The AM signalis supplied to the output via the volume control.2.3. AM DEMODULATORThe AM demodulated signal results from multiplying the input signal by itself, it is available onAM/FM output.2.3 FM demodulator and audio amplifier (mono versions):The FM demodulator is realized as narrow-band PLL with external loop filter, which provides thenecessary selectivity without using an external band-pass filter. To obtain a good selectivity alinear phase detector and constant input signal amplitude are required. For this reason the inter-carrier signal is internally supplied to the demodulator via a gain controlled amplifier and AGCcircuit. The nominal frequency of the demodulator is tuned to the required frequency(4.5/5.5/6.0/6.5 MHz) by means of a calibration circuit that uses the clock frequency of the µ-controller/Teletext decoder as a reference. The setting to the wanted frequency is realized by meansof the software. It can be read whether the PLL frequency is inside or outside the window andwhether the PLL is in lock or not. With this information it is possible to make an automatic searchsystem for the incoming sound frequency. This is realized by means of a software loop thatalternate the demodulator to various frequencies, then select the frequency on which a lock

4

condition has been found. De-emphasis output signal amplitude is independent of the TV standardand has the same value for a frequency deviation of ±25 kHz at the 4.5 MHz standard and for adeviation of ±50 kHz for the other standards. When the IF circuit is switched to positivemodulation the internal signal on de-emphasis pin is automatically muted. The audio controlcircuit contains an audio switch and volume control. In the mono inter-carrier sound versions theAutomatic Volume Leveling (AVL) function can be activated. The pin to which the externalcapacitor has to be connected depends on the IC version. For the 90° types the capacitor isconnected to the EW output pin (pin 20). When the AVL is active it automatically stabilizes theaudio output signal to a certain level.

2.4 Video switchingThe video processor (STV2248C) has three CVBS inputs and two RGB inputs. The first CVBSinput is used for external CVBS from SCART 1, the second is used for either CVBS or Y/C fromeither SCART2 or BAV/FAV, and the third one is used for internal video. The selection betweenboth external video inputs signals is realized by means of software and hardware switches.

2.5 Synchronization circuitThe video processor (STV224X) performs the horizontal and vertical processing. The externalhorizontal deflection circuit is controlled via the Horizontal output pulse (HOUT). The verticalscanning is performed through an external ramp generator and a vertical power amplifier ICcontrolled by the Vertical output pulse (VOUT).The main components of the deflection circuit are:• PLL1: the first phase locked loop that locks the internal line frequency reference on theCVBS input signal. It is composed of an integrated VCO (12 MHz) that requires the chromaReference frequency (4.43MHz or 3.58MHz crystal oscillator reference signal), a divider by768, a line decoder, and a phase comparator.• PLL2: The second phase locked loop that controls the phase of the horizontal output(Compensation of horizontal deflection transistor storage time variation). Also the horizontalposition adjustment is also performed in PLL2.• A vertical pulse extractor.• A vertical countdown system to generate all vertical windows (vertical synchronizationwindow, frame blanking pulses, 50/60Hz identification window...).• Automatic identification of 50/60Hz scanning.• PLL1 time constant control.• Noise detector, video identification circuits, and horizontal coincidence detector.• Vertical output stage including de-interlace function, vertical position control.• Vertical amplitude control voltage output (combined with chroma reference output andXtal 1 indication).

2.6 Chroma and luminance processing:The chroma decoder is able to demodulate PAL, NTSC and SECAM signals.The decoder dedicated to PAL and NTSC sub-carrier is based on a synchronous demodulator,and an Xtal PLL locked on the phase reference signal (burst).The SECAM demodulation is based on a PLL with automatic calibration loop.The color standard identification is based on the burst recognition.Automatic and forced modes can be selected through the I2C bus.NTSC tint, and auto flesh are controlled through I2C bus.Xtal PLL can handle up to 3 crystals to work in PAL M, PAL N and NTSC M for South America.ACC an ACC overload control the chroma sub-carrier amplitude within 26dB range. Both

5

ACC s are based on digital systems and do not need external capacitor.All chroma filters are fully integrated and tuned via a PLL locked on Xtal VCO signal.A second PLL is used for accurate fine-tuning of the SECAM bell filter. This tuning is achievedduring the frame blanking. An external capacitor memorizes the bell filter tuning voltage.A base-band chroma delay-line rebuilds the missing color line in SECAM and removestransmission phase errors in PAL.The base-band chroma delay line is clocked with 6MHz signal provided by the horizontal scanningVCO.The luminance processor is composed of a chroma trap filter, a luminance delay line, a peakingfunction with noise coring feature, a black stretch circuit.Trap filter and luminance delay lines are achieved with the use of bi-quad integrated filters, auto-aligned via a master filter phase locked loop.

2.7 RGB output circuit:The video processor performs the R, G, B processing.There are three sources:1. Y,U,V inputs (coming from luma part (Y output), and chroma decoder outputs (R-Y, B-Y

outputs).2. External R,G,B inputs from SCART (converted internally in Y,U,V), with also the possibility

to input YUV signals from a DVD player, (YUV specification is Y=0.7 V PP , U= 0.7 V PP ,V = 0.7V PP for 100% color bar).

3. Internal R,G,B inputs (for OSD and Teletext display)

The main functions of the video part are:- Y,U,V inputs with integrated clamp loop, allowing a DC link with YUV outputs,- External RGB inputs (RGB to YUV conversion), or direct YUV inputs,- Y,U,V switches,- Contrast, saturation, brightness controls,- YUV to RGB matrix,- OSD RGB input stages (with contrast control),- RGB switches,- APR function,- DC adjustment of red and green channels,- Drive adjustments (R, G, B gain),- Digital automatic cut-off loop control,- Manual cut-off capability with I2C adjustments,- Half tone, oversize blanking, external insertion detection, blue screen,- Blanking control and RGB output stages.

2.8 µ-ControllerThe ST92195 is the micro-controller, which is required for a color TV receiver. ST92195D1 is theversion with one page Teletext and ST92195D7 is the one with 7 page Teletext. The IC has thesupply voltages of 5 V and they are mounted in PSDIP package with 56 pins.µ-Controller has the following features Display of the program number, channel number, TV Standard, analogue values, sleep timer,

parental control and mute is done by OSD Single LED for standby and on mode indication System configuration with service mode 3 level logic output for SECAM and Tuner band switching

6

3. TUNEREither a PLL or a VST tuner is used as a tuner.UV1316 (VHF/UHF) is used as a PLL tuner. For only PALM/N, NTSC M applications UV 1336is used as the PLL tuner. UV 1315 (VHF/UHF) is used as a VST Tuner.

Channel coverage of UV1316:

BANDOFF-AIR CHANNELS

CHANNELS FREQUENCYRANGE (MHz)

CABLE CHANNELSCHANNELS FREQUENCY

RANGE (MHz)Low Band E2 to C 48.25 to 82.25 (1) S01 to S08 69.25 to 154.25Mid Band E5 to E12 175.25 to 224.25 S09 to S38 161.25 to 439.25High Band E21 to E69 471.25 to 855.25 (2) S39 to S41 447.25 to 463.25

(1). Enough margin is available to tune down to 45.25 MHz.(2). Enough margin is available to tune up to 863.25 MHz.

Noise Typical Max. Gain Min. Typical Max.Low band : 5dB 9dB All channels : 38dB 44dB 52dBMid band : 5dB 9dB Gain Taper (of-air channels): 8dBHigh band : 6dB 9dB

Channel Coverage UV1336:

BAND CHANNELS FREQUENCYRANGE (MHz)

Low Band 2 to D 55.25 to 139.25Mid Band E to PP 145.25 to 391.25High Band QQ to 69 397.25 to 801.25

Noise is typically 6dB for all channels. Gain is minimum 38dB and maximum 50dB for allchannels.

Channel Coverage of UV1315:

BANDOFF-AIR CHANNELS

CHANNELS FREQUENCYRANGE (MHz)

CABLE CHANNELSCHANNELS FREQUENCY

RANGE (MHz)Low Band E2 to C 48.25 to 82.25 (1) S01 to S10 69.25 to 168.25Mid Band E5 to E12 175.25 to 224.25 S11 to S39 231.25 to 447.25High Band E21 to E69 471.25 to 855.25 (2) S40 to S41 455.25 to 463.25

(1). Enough margin is available to tune down to 45.25 MHz.(2). Enough margin is available to tune up to 863.25 MHz.

7

Noise Typ. Max. Gain Min. Typ. Max.Low band 6dB 9dB All Channels 38dB 44dB 50dBMid band 6dB 10dB Gain Taper 8dBHigh band 6dB 11dB (off-air channels)

4. DIGITAL TV SOUND PROCESSOR MSP34X0The MSP 34x0D is designed to perform demodulation of FM or AM-Mono TV sound.Alternatively, two-carrier FM systems according to the German or Korean terrestrial specs or thesatellite specs can be processed with the MSP 34x0D. Digital demodulation and decoding ofNICAM-coded TV stereo sound, is done only by the MSP 3410. The MSP 34x0D offers apowerful feature to calculate the carrier field strength which can be used for automatic standarddetection (terrestrial) and search algorithms (satellite).

5. SOUND OUTPUT STAGE TDA7266L/TDA7266TDA7266L is used as the AF output amplifier for mono applications. It is supplied by +12VDCcoming from a separate winding in the SMPS transformer. An output power of 5.5W (THD=0.5%)can be delivered into an 8ohm load.TDA7266 is used as the AF output amplifier for stereo applications. It is supplied by+12VDC coming from a separate winding in the SMPS transformer. An output power of 2*5.5W(THD=0.5%) can be delivered into an 8ohm load.

6. VERTICAL OUTPUT STAGE WITH TDA8174AThe TDA8174A is a power amplifier circuit for use in 90° and 110° colour deflection systems for25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes.

7. TRIPLE VIDEO OUTPUT AMPLIFIER TDA6107JF

The TDA6107JF includes three video output amplifiers and is intended to drive the three cathodesof a colour CRT directly. The device is contained in a plastic DIL-bent-SIL 9-pin medium power(DBS9MPF) package, and uses high-voltage DMOS technology.To obtain maximum performance, the amplifier should be used with black-current control.Inputs and outputs are protected against electrostatic discharge in normal handling. However, to betotally safe, it is desirable to take normal precautions appropriate to handling MOS devices.

8. POWER SUPPLY (SMPS)The DC voltages required at various parts of the chassis are provided by an SMPS transformercontrolled by the IC MC44608 which is designed for driving, controlling and protecting switchingtransistor of SMPS. The transformer produces 115V for FBT input, 14V for audio output IC,S+3.3, S+5V and 8V for ST92195.

9. POWER FACTOR CORRECTIONPassive components are used for the solution of power factor correction.

10. POWER CARD

Power cards are used to supply DC voltages required for DVB boxes inside AK30 TV.11PW05 card produces +3.3V, +2.5V, +5V, +30 V DC voltages for DVB boxes.

8

11. RGB SWITCHING CARD 11RGB30-3

RGB Switching Card is used to switch R_EXT, G_EXT, B_EXT and R_DVDorDVB,G_DVDorDVB, B_DVDorDVB between each other to provide one R_OUT, G_OUT, B_OUT foroutput. PI5V330 Low On-Resistance Wideband/Video Quad 2-Channel Mux/DeMux IC is used toensure switching operation.

10. SERIAL ACCESS CMOS 8K EEPROM 24C08The 24C08 is a 8Kbit electrically erasable programmable memory (EEPROM), organized as 4blocks of 256*08 bits. The memory is compatible with the I²C standard, two wire serial interfacewhich uses a bi-directional data bus and serial clock.11. CLASS AB STEREO HEADPHONE DRIVER TDA1308The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plasticpackage

12. SAW FILTERS

Saw filter type: Model:G1975M: PAL B/G MONOK2966M: PAL SECAM B/G/D/K/I MONOJ1981 : PAL-I MONOK2958M: PAL-SECAM B/G-D/K (38) MONOK2962M: PAL-SECAM B/G/D/K/I/L/L’ MONOL9653M: SECAM L/L’ AM MONO (AUDIO IF)G3967M: PAL-SECAM B/G STEREO (VIDEO IF)G9353M: PAL-SECAM B/G STEREO (AUDIO IF)K3958M: PAL-SECAM B/G/D/K/I/L/L’ STEREO (VIDEO IF)K9356M: PAL-SECAM B/G/D/K/I STEREO (AUDIO IF)K9656M: PAL-SECAM B/G/D/K/I/L/L’ STEREO (AUDIO IF)K3958M: PAL I NICAM (VIDEO IF)K9356M: PAL I NICAM (AUDIO IF)M1962M: PAL M/N NTSC M MONOM3953M: PAL M/N NTSC M STEREO (VIDEO IF)M9370M: PAL M/N NTSC M STEREO (AUDIO IF)

13. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM

ST92195 STV224X TUNER (UV1315, UV1316, UV1336,TECC2949PG40B,TAEA-G0XXD ,ChongQing QingJia) TDA7266L / TDA7266M TDA8174A TDA6107JF MC44608 MSP34X0D 24C08 TDA1308

9

SAW FILTERSG1975M, K2966M, K2962M, L9653M, G3962M, G9353M, K3958M, K9356M, K9656M,K6263K, K9652M,M1962M, M3953M, M9370M

ST92195The ST92195 is a member of the ST9+ family of micro-controllers, completely developed andproduced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. Thenucleus of the ST92195 is the advanced Core, which includes the Central Processing Unit (CPU),the ALU, the Register File and the interrupt controller. The Core has independent memory andregister buses to add to the efficiency of the code. A set of on-chip peripherals form a completesys-tem for TV set and VCR applications:– Voltage Synthesis– VPS/WSS Slicer– Teletext Slicer– Teletext Display RAM– OSDAdditional peripherals include a watchdog timer , a serial peripheral interface (SPI), a 16-bit timerandan A/D converter.

10

STV224X Video processor:

The STV2246/2247/2248 are fully bus controlled ICs for TV including PIF, SIF, luma, Chromaand deflection processing. Used with a vertical frame booster (TDA1771 or TDA8174 for 90°chassis, STV9306 for 110° chassis), they allow the design of multi-standard (BGDKIMNLL, PAL/SECAM/NTSC) sets with very few external components and no manual adjustments.

11

UV1315, UV1316, UV1336,TECC2949PG40B,TAEA-G0XXD ,ChongQing QingJia

General description of UV1315:The UV1315 tuner belongs to the UV 1300 family of tuners, which are designed to meet a widerange of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, Iand I’.Features of UV1315: Member of the UV1300 family small sized UHF/VHF tuners Systems CCIR:B/G, H, L, L’, I and I’; OIRT:D/K Voltage synthesized tuning (VST) Off-air channels, S-cable channels and Hyper-band Standardized mechanical dimensions and pinning

PINNING PIN VALUE

1. Gain control voltage (AGC) :4.0V, Max:4.5V2. Tuning voltage3. High band switch :5V, Min:4.75V, Max:5.5V4. Mid band switch :5V, Min:4.75V, Max:5.5V5. Low band switch :5V, Min:4.75V, Max:5.5V6. Supply voltage :5V, Min:4.75V, Max:5.5V7. Not connected8. Not connected9. Not connected

10. Symmetrical IF output 111. Symmetrical IF output 2

Band switching table:

Pin 3 Pin 4 Pin 5Low band 0V 0V +5VMid band 0V +5V 0VHigh band +5V 0V 0V

General description of UV1316:The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a widerange of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, Iand I’.

Features of UV1316: Member of the UV1300 family small sized UHF/VHF tuners Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K Digitally controlled (PLL) tuning via I²C-bus Off-air channels, S-cable channels and Hyper-band World standardized mechanical dimensions and world standard pinning Complies to “CENELEC EN55020” and “EN55013”

12

PINNING PIN VALUE

1. Gain control voltage (AGC) :4.0V, Max:4.5V2. Tuning voltage3. I²C-bus address select :Max:5.5V4. I²C-bus serial clock :Min:-0.3V, Max:5.5V5. I²C-bus serial data :Min:-0.3V, Max:5.5V6. Not connected7. PLL supply voltage :5.0V, Min:4.75V, Max:5.5V8. ADC input9. Tuner supply voltage :33V, Min:30V, Max:35V

10. Symmetrical IF output 111. Symmetrical IF output 2

General description of UV1336:UV1336 series is developed for reception of channels broadcast in accordance with the M, Nstandard.

Features of UV1336: Global standard pinning Integrated Mixer-Oscillator & PLL function Conforms to CISPR 13, FCC and DOC (Canada) regulations Low power consumption Both Phono connector and ‘F’ connector are available

PINNING PIN VALUE

1. Gain control voltage :4.0V, Max:4.5V2. Tuning voltage3. Address select Max:5.5V4. Serial clock :Min:-0.3V, Max:5.5V5. Serial data :Min:-0.3V, Max:5.5V6. Not connected7. Supply voltage :5.0V, Min:4.75V, Max:5.5V8. ADC input (optional)9. Tuning supply voltage :33V, Min:30V, Max:35V

10. Ground11. IF output

TECC2949PG40B SAMSUNG TUNER

Features:• CCIR standart receiving system•Off- air channels ,s-cable channels , 3 band (UHF,VHFhigh and low)• PAL FST tuner•Tuning system :Frequency synthesized type

Pinning:1- AGC AGC Voltage supply (Typ:5V Max:4.5V)2- NC No pin3- SAS Adress select4- SCL Serial clock5- SDA Serial data6- NC No pin7- BP B+ for internal IC (Min:4.75V Typ:5V Max.5.5V)8- NC No pin9- BT Tuning supply voltage (Min:30V Typ:33V Max: 35V)10- IF2 IF output211- IF1 IF1 output

TAEA-G0XXD LG TUNER

Features:• CCIR+CATV standart receiving channel•Off- air channels ,s-cable channels , 3 band (UHF,VHFhigh and low)•Upper heterodyne Receiving system•Varactor –Tuned(With PLL)

Pinning:1- AGC AGC Voltage supply (Typ:5V Max:4.5V)2- TU Tuning output voltage3- SAS Adress select4- SCL Serial clock5- SDA Serial data6- B+ No pin7- B+ B+ for internal IC (Min:4.75V Typ:5V Max.5.5V)8- NC No pin9- BT Tuning supply voltage (Min:30V Typ:33V Max: 35V)10- IF2 IF output211- IF1 IF1 output

ChongQing QingJia Electronical Co.Tuner

•PAL BG Receiving system•PLL tuning system•Off- air channels ,s-cable channels , 3 band (UHF,VHFhigh and low)

Pinning:1- AGC AGC Voltage supply (Typ:5V Max:4.5V)2- NC No pin3- SAS Adress select4- SCL Serial clock5- SDA Serial data6- NC No pin7- BP B+ for internal IC (Min:4.75V Typ:5V Max.5.5V)8- NC No pin9- BT Tuning supply voltage (Min:30V Typ:33V Max: 35V)10- IF2 IF output211- IF1 IF1 output

13

TDA7266/TDA7266LGeneral Description of TDA7266LThe TDA7266L is a mono bridge amplifier specially designed for TV and Portable Radioapplications. Requires very few external components

WIDE SUPPLY VOLTAGE RANGE (3-18V)MINIMUM EXTERNAL COMPONENTS– NO SVR CAPACITOR– NO BOOTSTRAP– NO BOUCHEROT CELLS– INTERNALLY FIXED GAINSTAND-BY & MUTE FUNCTIONSSHORT CIRCUIT PROTECTIONTHERMAL OVERLOAD PROTECTION

PINNING1 N.C.2 N.C.3 MUTE4 ST-BY5 PW-GND6 S-GND7 IN8 VCC9 OUT+10 OUT -

General Description of TDA7266The TDA7266 is a 2x7 Watt dual power amplifier. It is used for sound amplification at stereo TVsets.WIDE SUPPLY VOLTAGE RANGE (3-18V)MINIMUM EXTERNAL COMPONENTS– NOSWR CAPACITOR– NOBOOTSTRAP– NOBOUCHEROT CELLS– INTERNALLY FIXED GAINSTAND-BY & MUTE FUNCTIONSSHORT CIRCUIT PROTECTIONTHERMAL OVERLOAD PROTECTION

PINNING1. OUT1+2. OUT1 –3. VCC4. IN15. N.C.6. MUTE7. ST-BY8. PW-GND

14

9. S-GND10. N.C.11. N.C.12. IN213. VCC14. OUT2 -15. OUT2+

TDA8174AW

INDEPENDENT VERTICAL AMPLITUDE ADJUSTEMENT. BUFFER STAGE. POWERAMPLIFIER.FLYBACKGENERATOR .THERMALPROTECTION .INTERNAL REFERENCE VOLTAGEDECOU-PLING

General Description:TDA8174Aand TDA8174AWare a monolithic integrated circuits. It is a full performance and veryefficient vertical deflection circuit intended for direct drive of a TV picture tube in Color and B &W television as well as in Monitor and Data displays.

PINNING1. POWER OUTPUT2. OUTPUT STAGE Vs3. TRIGGER INPUT4. HEIGHT ADJUSTMENT5. VOLTAGE REF DECOUPLING6. GROUND7. RAMP GENERATOR8. BUFFER OUTPUT9. INVERTING INPUT10. Vs11. FLYBACK GENERATOR

TDA6107JF

General Description:The TDA6107JF includes three video output amplifiers and is intended to drive the three cathodesof a colour CRT directly. The device is contained in a plastic DIL-bent-SIL 9-pin medium power(DBS9MPF) package, and uses high-voltage DMOS technology.

To obtain maximum performance, the amplifier should be used with black-current control.

FEATURES· Typical bandwidth of 5.5 MHz for an output signal of 60 V (p-p)· High slew rate of 900 V/ms· No external components required· Very simple application

15

· Single supply voltage of 200 V· Internal reference voltage of 2.5 V· Fixed gain of 50· Black-Current Stabilization (BCS) circuit with voltage window from 1.8 to 6 V and currentwindow from -100 mA to 10 mA· Thermal protection· Internal protection against positive flashover discharges appearing on the CRT.

PINNINGSYMBOL PIN DESCRIPTIONVi(1) 1 inverting input 1Vi(2) 2 inverting input 2Vi(3) 3 inverting input 3GND 4 ground (fin)Iom 5 black-current measurement outputVDD 6 supply voltageVoc(3) 7 cathode output 3Voc(2) 8 cathode output 2Voc(1) 9 cathode output 1

MC44608

General description:The MC44608 is a high performance voltage-mode controller designed for off–line converters.This high voltage circuit that integrates the start–up current source and the oscillator capacitor,requires few external components while offering a high flexibility and reliability.

The device also features a very high efficiency stand–by management consisting of an effectivePulsed Mode operation. This technique enables the reduction of the stand–by power consumptionto approximately 1W while delivering 300mW in a 150W SMPS.

• Integrated start–up current source• Loss less off–line start–up• Direct off–line operation• Fast start–up

General Features• Flexibility• Duty cycle control• On chip oscillator switching frequency 40, or 75kHz• Secondary control with few external componentsProtections• Maximum duty cycle limitation• Cycle by cycle current limitation• Demagnetization (Zero current detection) protection• “Over V CC protection” against open loop• Programmable low inertia over voltage protection against open loop• Internal thermal protection

16

GreenLine Controller• Pulsed mode techniques for a very high efficiency low power mode• Lossless startup• Low dV/dT for low EMI radiations

PINNING PIN VALUE1. Demagnetization Zero cross detection voltage: 50 mV typ.2. I Sense Over current protection voltage 1V typ.3. Control Input Min: 7.5V Max.: 18V4. Ground Iout 2Ap-p during scan 1.2Ap-p during flyback5. Driver Output resistor 8.5 Ohm sink 15 Ohm source typ.6. Supply voltage Max:16V (Operating range 6.6V-13V)7. No connection8. Line Voltage Min:50V Max:500V

MSP34X0DThe MSP 34x0D is designed to perform demodulation of FM or AM-Mono TV sound. Two kindsof MSP’s are used. MSP 3400D and MSP 3410D. The MSP 3400D is fully pin and software-compatible to the MSP 3410D, but is not able to decode NICAM. It is also compatible to the MSP3400C.

General description:Demodulator and NICAM Decoder SectionThe MSP 34x0D is designed to perform demodulation of FM or AM-Mono TV sound.Alternatively, two-carrier FM systems according to the German or Korean terrestrial specs or thesatellite specs can be processed with the MSP 34x0D. Digital demodulation and decoding ofNICAM-coded TV stereo sound, is done only by the MSP 3410. The MSP 34x0D offers apowerful feature to calculate the carrier field strength, which can be used for automatic standarddetection (terrestrial) and search algorithms (satellite).

General Features Two selectable analog inputs (TV and SAT-IF sources) Automatic Gain Control (AGC) for analog IF input. Input range: 0.10–3 V pp Integrated A/D converter for sound-IF inputs All demodulation and filtering is performed on chip and is individually programmable Easy realization of all digital NICAM standards (B/G, D/K, I & L) with MSP 3410G. FM demodulation of all terrestrial standards (incl. identification decoding) FM demodulation of all satellite standards No external filter hardware is required Only one crystal clock (18.432 MHz) is necessary FM carrier level calculation for automatic search algorithms and carrier mute function

DSP Section (Audio Base band Processing) Flexible selection of audio sources to be processed Two digital input and one output interface via I 2 S bus for external DSP processors, featuring

surround sound, ADR etc.

17

Digital interface to process ADR (ASTRA Digital Radio) together with DRP 3510A Performance of all de-emphasis systems including adaptive Wegener Panda 1 without external

components or controlling Digitally performed FM identification decoding and de-matrixing Digital base-band processing: volume, bass, treble, 5-band equalizer, loudness, pseudo-stereo,

and base-width enlargement Simple controlling of volume, bass, treble, equalizer etc.

Analog Section four selectable analog pairs of audio base-band inputs (= four SCART inputs) input level: =<2

V RMS , input impedance: >=25 k one analog mono input (i.e. AM sound): input level: =<2 V RMS , input impedance: >=15 k two high-quality A/D converters, S/N-Ratio: >=85 dB 20 Hz to 20 kHz bandwidth for SCART-to-SCART copy facilities

24C08

General description:The 24C16 is a 8Kbit electrically erasable programmable memory (EEPROM), organized as 4blocks of 256 * 08 bits. The memory operates with a power supply value as low as 2.5V.Features: Minimum 1 million ERASE/WRITE cycles with over 10 years data retention Single supply voltage:4.5 to 5.5V Two wire serial interface, fully I²C-bus compatible Byte and Multi-byte write (up to 8 bytes) Page write (up to 16 bytes) Byte, random and sequential read modes Self timed programming cycle

PINNING PIN VALUE

1. Write protect enable :0V2. Not connected :0V3. Chip enable input :0V4. Ground :0V5. Serial data address input/output :Input LOW voltage: Min:-0.3V, Max:0.3*Vcc

:Input HIGH voltage: Min:0.7*Vcc, Max:Vcc+16. Serial clock :Input LOW voltage: Min:-0.3V, Max:0.3*Vcc

:Input HIGH voltage: Min:0.7*Vcc, Max:Vcc+17. Multibyte/Page write mode :Input LOW voltage: Min:-0.3V, Max:0.5V

:Input HIGH voltage: Min:Vcc-0.5, Max:Vcc+18. Supply voltage :Min:2.5V, Max:5.5V

18

TDA1308

Features: Wide temperature range Excellent power supply ripple rejection Low power consumption Short-circuit resistant High performance high signal-to-noise ratio low distortion

PINNING PIN VALUE

1. Output A (Voltage swing) :Min:0.75V, Max:4.25V2. Inverting input A :Vo(clip):Min:1400mVrms3. Non-inverting input A :2.5V4. Ground :0V5. Non-inverting input B :2.5V6. Inverting input B :Vo(clip):Min:1400mVrms7. Output B (Voltage swing) :Min:0.75V, Max:4.25V8. Positive supply :5V, Min:3.0V, Max:7.0V

PI5V330

DescriptionPericom Semiconductor’s PI5V330 is a true bidirectional Quad 2-channelmultiplexer/demultiplexer recommended for both RGB and composite video switchingapplications. The video switch can be driven from a current output RAMDAC or voltage outputcomposite video source.Low On-Resistance and wide bandwidth make it ideal for video and other applications. Also thisdevice has exceptionally high current capability which is far greater than most analog switchesoffered today. A single 5V supply is all that is required for operation.The PI5V330 offers a high-performance, low-cost solution to switch between video sources. Theapplication section describes the PI5V330 replacing the HC4053 multiplier and buffer/amplifier.

Features• High-performance solution to switch between video sources• Wide bandwidth: 200 MHz• Low On-Resistance: 3Ω• Low crosstalk at 10 MHz: –58dB• Ultra-low quiescent power (0.1μA typical)• Single supply operation: +5.0V• Fast switching: 10ns• High-current output: 100mA• Packaging (Pb-free & Green Available):– 16-pin 300-mil wide plastic SOIC (S)

19

– 16-pin 150-mil wide plastic SOIC (W)– 16-pin 150-mil wide plastic QSOP (Q)

Saw filter’s list:

VIDEO AUDIOPAL BG G1975MPSBG DK K2966MPAL II' J1981PSBGDKK' II' K2966MPSBGDKK' LL' K2962M L9653

VIDEO AUDIOPAL BG G3967M G9353MPAL II' K3958M K9356PSBGDKK' II' K3958M K9356PSBGDKK' LL' K3958M K9656

MO

NO

STR

20

PINNING1. Input2. Input-ground3. Chip carrier-ground4. Output5. Output

K9656M, L9653M

PINNING1. Input 4. Output2. Switching Input 5. Output3. Chip carrier-ground

AK30 SERVICE MENU ADJUSTMENTS

ENTERING TO SERVICE MENU:

In order to enter service menu, first enter the main menu and then press the digits 4, 7, 2 and 5respectively.To select adjust parameters, use or buttons. To change the selected parameter, use or buttons. Selected parameter will be highlighted.

Entire service menu parameters of AK30 CHASSIS are listed below. For some of parameters thedefault values are given in this document also.

USING COLOUR BUTTONS ON SERVICE MENU:

- RED BUTTON : It switches the AVL to ON or OFF mode on service menu. AVL word isvisible on service menu when AVL is on.

- GREEN BUTTON : It switches to GEOMETRY adjust menu. Geometry of the picture isadjusted in this menu.

- YELLOW BUTTON : It switches to VERTICAL SCAN DISABLE mode. It is useful toadjust screen voltage.

- BLUE BUTTON : It is used to adjust AGC and IF automatically on service menu.

OSD:

Select OSD parameter on service menu. Adjust the horizontal position of OSD to the middle ofscreen, by using the reference bar on bottom of service menu.

Min. Value: 000Max. Value: 127Recommended Value: 080

21

IF Adjustments:

IF1: IF Coarse Adjustment 003IF2: IF Fine Adjustment 062

IF3: IF Coarse Adjustment for L-prime 002IF4: IF Fine Adjustment for L-prime 071

IF NEGATIVE ADJUSTMENT (WITHOUT L’ SYSTEMS)Set the video pattern to a PAL colour bar pattern with frequency 38.9 MHz. Apply this IF signal toPIN-10 and PIN-11 of tuner. Press PROG-1 and after that BLUE (INSTALL)button from remotecontroller. Select the standard as BG or I. (if BG is not available) Enter service menu. Select IF1parameter from service menu and press BLUE (INSTALL) button from remote controller. IFadjustment will be done automatically by software. See the IF indicator on service menu, it mustbe like on FIGURE-1 shown belove.

IF POSITIVE ADJUSTMENT (WITH L’ SYSTEMS)

Set the video pattern to a SECAM-L colour bar pattern with frequency 33.9 MHz. Apply this IFsignal to PIN-10 and PIN-11 of tuner. Press PROG-1 and after that BLUE (INSTALL)button fromremote controller. Select the BAND VHF-1 (S1 – S4 for PLL tuners) and standard as L’. Enterservice menu. Select IF1 parameter from service menu and press BLUE (INSTALL) button fromremote controller. IF adjustment will be done automatically by software. See the IF indicator onservice menu, it must be like on FIGURE-1 shown below.

AGC: Automatic Gain Control

In order to do AGC adjustment, enter a 60µdBV RF signal level from channel C-12 (224.25 MHz)Select AGC parameter from service menu. Press BLUE (INSTALL) button from remote controller.The adjustment will be done automatically by software. See the AGC indicator on service menu, itmust be 1. Check that picture is normal at 90dBµV signal level.

OSD001IF1071IF2073IF3065IF4066AGC060VLIN040RGBH+10

: 0 1 AVL

FIGURE-

: 1 1

IF INDICATOR AGC INDICATOR NONE

22

Min. Value: 000Max. Value: 063Recommended Value: Automatically, described above.

SCREEN ADJUSTMENT: (FBT Screen)

Enter service menu by pressing “MENU” and “4, 7, 2, 5” or press the mute and info buttons at thesame time from remote controller. Then press yellow button to disable vertical scan. Adjusthorizontal line via screen pot. as thin as possible. Press yellow button again to enable vertical scan.Press “TV” button to leave service menu.

VLIN: Vertical Linearity

Enter a PAL B/G circle test pattern via RF. Change VLIN till you see circle as round as possible.

SCREENADJ.POT.

23

Min. Value: 000Max. Value: 063Recommended Value : 041

RGBH: RGB Mode Horizontal Shift Offset

Enter a RGB circle test pattern via video inputs. Force the TV to RGB mode by pressing AVbutton from remote controller. Change RGB Horizontal Position till the picture is horizontallycentered. Check and readjust RGBH item if the adjustment becomes improper after some othergeometric adjustments are done.

Min. Value: 000Max. Value: 063Default Value : 010

VSOF: Vertical Size Offset for 60 Hz

Enter an NTSC-M circle test pattern via RF or video inputs. Change Vertical Size until thecheckered parts of test pattern on both of upper and lower side disappear. Check and readjustVertical Size item if the adjustment becomes improper after some other geometric adjustments aredone.

Min. Value: -08Max. Value: +55Recommended Value: -20 VPOF: Vertical Position Offset for 60 Hz

Enter an NTSC-M circle test pattern via RF or video inputs. Change Vertical Position till thepicture is vertically centered. Check and readjust Vertical Size item if the adjustment becomesimproper after some other geometric adjustments are done.

Min. Value: -08Max. Value: +55Recommended Value: +08

HSOF: Horizontal Size Offset for 60 Hz

Not Used For This Model

24

HPOF: Horizontal Position Offset for 60 Hz

Enter an NTSC-M circle test pattern via RF or video inputs. Change Horizontal Position till thepicture is horizontally centered. Check and readjust Horizontal Position item if the adjustmentbecomes improper after some other geometric adjustments are done.

Min. Value: -08Max. Value: +55Recommended Value : -06

HTOF: Horizontal Trapezoid Offset for 60 Hz

Not Used For This Model.

GEOMETRY MENU

From the service menu by pressing the green button, geometry menu appears.

To select geometry adjust parameters, use or buttons. To change the selected parameter, useorbuttons. Selected parameter will be highlighted.

Entire geometry menu parameters of AK30 CHASSIS are listed below.

VSIZ: Vertical Size for 50 Hz

Enter a PAL B/G circle test pattern via RF. Change VSIZ (Vertical Size) until horizontal blacklines on both the upper and lower part of the test pattern become very close to the upper and lowerhorizontal sides of picture tube and nearly about to disappear. Check and readjust Vertical Sizeitem if the adjustment becomes improper after some other geometric adjustments are done.

Min. Value: 000Max. Value: 063Recommended Value for 4:3 mode 027Recommended Value for 16:9 mode 063

VPOS: Vertical Position for 50 Hz

Enter a PAL B/G circle test pattern via RF. Change Vertical Position till the test pattern isvertically centered. Horizontal line at the center pattern is in equal distance both to upper andlower side of the picture tube. Check and readjust Vertical Position item if the adjustment becomesimproper after some other geometric adjustments are done.

25


VSCO: Vertical S-Correction for 50 Hz


VCCO: Vertical Corner Correction for 50 Hz


HSIZ: Horizontal Size for 50 Hz


HPOS: Horizontal Position for 50 Hz

Enter a PAL B/G circle test pattern via RF. Change Horizontal Position until the picture ishorizontally centered. Check and readjust Horizontal Position item if the adjustment becomesimproper after some other geometric adjustments are done.


HPIN: Horizontal Pincushion for 50 Hz


HCCO: Horizontal Corner Correction for 50 Hz


HTRP: Horizontal Trapezoid for 50 Hz


VZSZ: Vertical Zoom Size for 50 Hz


26

WHITE BALANCE ADJUSTMENT

The following three parameters are used to make white balance adjustment. To do this, use aColour Analyzer. Using WR (White point adjust for RED), WG (White point adjust for GREEN),WB (White point adjust for BLUE) parameters, insert the + sign in the square which is in themiddle of the screen.

WR: White Point Adjustment for RED

Use this parameter to set the strength of RED in White.


WG: White Point Adjustment for GREEN

Use this parameter to set the strength of GREEN in White.

Min. Value: 000

50 HZ. 4:3 GEOMETRY ADJ.

50 HZ. 16:9 GEOMETRYADJ.

60 HZ. 4:3 GEOMETRY ADJ.

27

Max. Value: 063Default Value : 040

WB: White Point Adjustment for BLUE

Use this parameter to set the strength of BLUE in White.


BR: Bias for RED

Use this parameter to set the strength of RED in BLACK.


BG: Bias for GREEN

Use this parameter to set the strength of GREEN in BLACK.

Min. Value: 000Max. Value: 063Default Value : 028 APR: Automatic RGB Peak Regulation (APR) Threshold

The goal of the APR function (Automatic RGB peak regulation) is to compensate the spread ofcontrast between sources or programs by regulating the peak amplitude of RGB signals. Thisresults in a picture with higher contrast whatever the input signal amplitude. Besides, APRincreases the contrasts of pictures with low contrast and avoids the clipping at RGB output forpictures with high amplitude.

To enable APR, refer to OP3 in Option Bytes.


The following default values are the factory settings of the corresponding items. Except Volume,all values are restored when STANDARD button is pushed during no menu is displayed. Volumeis set to its default value only if the A.P.S. bit is set when the TV is turned on.

28

AVL: Automatic Volume Control

In order to make AVL ON or AVL OFF, press the RED button while in service menu.If AVL is ON, the AVL string occurs on the bottom right of the service menu screen.If AVL is OFF, no string occurs about AVL on the bottom of the service menu.

FMP1: FM Prescaler when AVL is OFF


NIP1: NICAM Prescaler when AVL is OFF


SCP1: SCART Prescaler when AVL is OFF


SEC1: SECAM Prescaler when AVL is OFF


FMP2: FM Prescaler when AVL is ON


NIP2: NICAM Prescaler when AVL is ON

Min. Value: 000Max. Value: 127

29

Recommended Value: 018

SCP2: SCART Prescaler when AVL is ON


SEC2: SECAM Prescaler when AVL is ON


TTuunneerr SSeettttiinnggss Rev No : 00

ELEKTRONİK SAN. VE TİC. A.Ş. AAPPPPLLIICCAATTIIOONN EENNGGIINNEEEERRIINNGG Date : 0 2 . 1 1 . 0 5

UMB DDEEPPAARRTTMMEENNTT Page : 1

Form Rev No: 00 Form No: DENEME

Tuner Settings

Ana Tuner

B1 H -F1H VHF HIGH

crossover high byte

B1 L-F1L VHF LOW

crossover low byte

B2 H -F2H UHF high

crossover high byte

B2 L -F2L UHF low

crossover low byte

BS1 control 2 low

byte

BS2 control 2 mid

byte

BS3 control 2 high

byte CB

control 1 byte 0000 1100 0011 0010 0001 1110 0000 0010 0000 0001 0000 0010 0000 0100 1000 1110

0C 32 1E 02 01 02 04 8E PHILIPS UV1316S MK3 12 32 30 2 1 2 4 142

0000 1001 1001 0010 0001 1011 1000 0010 0000 0011 0000 0110 1000 0101 1000 1110 09 92 1B 82 03 06 85 8E THOMSON CTT5510A 9 146 27 130 3 6 133 142

0000 1101 0001 0010 0001 1110 1000 0010 0000 0001 0000 0010 0000 1000 1000 1110 0D 12 1E 82 01 02 08 8E SAMSUNG TECC2949PG35B 13 18 30 130 1 2 8 142

0000 1011 0101 0010 0001 1101 0000 0010 0000 0001 0000 0010 0000 1000 1000 1110 0B 52 1D 02 01 02 08 8E ALPS TEDE9X226A 11 82 29 2 1 2 8 142

0000 1011 1100 0010 0001 1100 1111 0010 0000 0001 0000 0010 0000 1000 1000 1110 0B C2 1C F2 01 02 08 8E ALPS TEDE-004A 11 44 28 242 1 2 8 142

0000 1011 1100 0010 0001 1101 0000 0010 0000 0001 0000 0010 0000 1000 1000 1110 0D C2 1D 02 01 02 08 8E ALPS TEDE 9X313A 13 44 29 2 1 2 8 142

0000 1011 0101 0010 0001 1101 0000 0010 0000 0001 0000 0010 0000 1000 1000 1110 0B 52 1D 02 01 02 08 8E SAMSUNG TECC2949PG40B 11 82 29 2 1 2 8 142

0000 1011 0101 0010 0001 1101 0000 0010 0000 0001 0000 0010 0000 1000 1000 1110 0B 52 1D 02 01 02 08 8E LG-INNOTEK(TAEM-G081D)

LG TAEM G-041D 11 82 29 2 1 2 8 142

Ref No : ELEKTRONİK SAN. VE TİC. A.Ş. TTEECCHHNNIICCAALL RREEPPOORRTT Date : 0 2 . 1 1 . 0 5

UMB AAPPPPLLIICCAATTIIOONN EENNGGIINNEEEERRIINNGG

Page : 2


0000 1100 0011 0010 0001 1110 0000 0010 0000 0001 0000 0010 0000 0100 1000 1110 0C 32 1E 02 01 02 04 8E PHILIPS MK4 12 32 30 2 1 2 4 142

0000 1011 0101 0010 0001 1101 0000 0010 0000 0010 0000 0001 0000 0100 1000 1110 0B 52 1D 02 02 01 04 8E Thomson CTF5550 11 82 29 2 2 1 4 142

0000 1011 0101 0010 0001 1101 0000 0010 0000 0001 0000 0010 0000 1000 1000 1110 0B 52 1D 02 01 02 08 8E Panasonıc PLL ( ENV57K02G3 ) 11 82 29 2 2 1 8 142

0000 1011 0101 0010 0001 1101 0000 0010 0000 0001 0000 0010 0000 1000 1000 1110 0B 52 1D 02 01 02 08 8E QINGJIA AFT0/5105 (KONKA) 11 82 29 2 2 1 4 142

0000 1001 1001 0010 0001 1011 1000 0010 0000 0011 0000 0110 1000 0101 1000 1110 09 92 1B 82 03 06 85 8E

Golden Dragon EWT-5F3N2-E28FW

9 146 27 130 3 6 133 142 0000 1011 0111 0010 0001 1101 0011 0010 0000 0001 0000 0010 0000 1000 1000 1110

0B 72 1D 32 01 02 08 8E THOMSON CTF5540 11 114 29 50 1 2 8 142

00001011 01010010 00011101 00000010 00000001 00000010 00001000 10001110 0B 52 1D 02 01 02 08 8E GDC EWT-5F3TA2-E02W 11 82 29 2 1 2 8 142

0000 1100 0011 0010 0001 1110 0000 0010 0000 0001 0000 0010 0000 0100 1000 1110 0C 32 1E 02 01 02 04 8E

TCL F01GP-2BP-E ( 30042772 )

12 32 30 1 2 1 4 142

Ref No : ELEKTRONİK SAN. VE TİC. A.Ş. TTEECCHHNNIICCAALL RREEPPOORRTT Date : 0 2 . 1 1 . 0 5

UMB AAPPPPLLIICCAATTIIOONN EENNGGIINNEEEERRIINNGG

Page : 3


Tuner Settings ( NTSC 60 Hz )

Ana Tuner F1H F1L F2H F2L BS1 BS2 BS3 CB

PHILIPS UV1336A 8 180 24 116 1 2 4 142

SAMSUNG TECC1040SG32K 7 244 22 148 1 2 8 142

SAMSUNG TECC1940PG38W 7 244 22 148 1 2 8 142

DÖKÜMAN NO : 04.UMB.13b ELEKTRONİK SAN. VE TİC..A.Ş.

SERVİS VE OPSIYON AYARLARI TARİH : SAYFA NO : 10 / 15

UMB BÖLÜMÜ (SERVICE & OPT. SETTINGS) DEĞ. NO: 83 DEĞ. TAR : 31.08.2006

Form Rev No: 01 Form No: 04.UMB.13b

AK30 (T3X) STANDARD TV

OP1 – SCART OPTIONS DESCRIPTION OP2 – TV STANDART OPTIONS DESCRIPTION 1, Wide Line Blanking is active. 1 – 3-button keyboard (V-, P+, V+)

BIT-7 0, Wide Line Blanking is inactive.

“ 1 “ default value BIT-7 0 – 4/5 button keyboard (V-, V+, P-, P+, Menu)

Value should be “0”

1 – Display “AV-3” as “F-AV” 1 – L/L’ is available BIT-6

0 – Display “AV-3” as “B-AV” FAV IN or BAV IN selection option BIT-6

0 – L/L’ is not available

1 – Turn back TV mode after the last AV (with AV key) “ 1 “ default value 1 – I is available

BIT-5 0 – Turn back first AV mode after the last AV

BIT-5 0 – I is not available

1 – SVHS is available in AV key stream 1 – DK is available BIT-4

0 – SVHS is NOT available in AV key stream “ 1 “ If AV2 or SVHS is available BIT-4

0 – DK is not available

1 – RGB is available in AV key stream 1 – BG is available BIT-3

0 – RGB is NOT available in AV key stream “ 1 “ If AV1 available BIT-3

0 – BG is not available

1 – AV-3 is available in AV key stream 1 – DOLBY VIRTUAL is visible BIT-2

0 – AV-3 is NOT available in AV key stream “ 1 “ If FAV IN or BAV IN is available BIT-2

0 – 3D PANORAMA is visible 1 for virtual dolby model 0 for 3D panorama and other models

1 – AV-2 is available in AV key stream 1 – for SECAM LLP ,EXT MONO INPUT is available 0 – inner demodulation is avaible for SECAM LLP BIT-1

0 – AV-2 is NOT available in AV key stream “1” If SCART-2 is available BIT-1

0 – for SEC L/L’ mono, inner demod. Of MSP Value should be “0”

BIT-0 1 – AV-1 is available in AV key stream “1” If SCART-1 is available BIT-0 1 – LOW POWER is available Value should be “1”

OP3 – VIDEO OPTIONS DESCRIPTION OP4 – TV ÖZELLİKLERİ AÇIKLAMA

Xtal Configuration 00, 1 XTAL PAL 4.43 PAL, W/O 3.58 1 – Headphone is available (for STEREO models)

01, 2 XTAL PAL/NTSC 4.43/3.58 PAL, W 3.58 BIT-7

0 – Headphone is not available

10, 1 XTAL PAL/SEC/NTSC 4.43 PAL and SECAM W/O 3.58 1, Arabic/Persian is Available in Menu Languages (for A, D, E, F, and later)

BIT-7,6

11, 2 XTAL PAL/SEC/NTSC 4.43/3.58 PAL VE SECAM W 3.58 BIT-6

0, Arabic/Persian is NOT Available in Menu Languages

1 – Enable Blue back when no signal in AV modes 1, Hebrew is Available in Menu Languages (for A, D, E, F, and later) BIT-5

0 – No Blue Back in AV modes Value should be “1”

BIT-5 0, Hebrew is NOT Available in Menu Languages

1 – White Insertion is ON 1 – Hotel Mode can be activated BIT-4

0 – White Insertion is OFF Value should be “1”

BIT-4 0 – Hotel Mode can not be activated It is visible in the menu after pressing Menü-1-3-2-5.

1 – Blue Background when no signal 1 – No Signal Timer is enabled BIT-3

0 – Disable Blue Background Value should be “1”

BIT-3 0 – No Signal Timer is disabled Value should be “1”

BIT-2 1 – Semi-transparent background for menu Value should be “1” BIT-2

For PLL Tuner 1, Frequency based search

Value should be “0”





0 – Solid Menu background for menu 0, Channel table based search (No meaning for VST Tuner)

1 – Black Stretch is ON 1, 3-band tuning (VHF1, VHF3, UHF) BIT-1

0 – Black Stretch is OFF Value should be “0”

BIT-1 0, 1-band tuning (only UHF) Value should be “1”

1 – APR is ON 1 – Extra 200 msec blanking for VST BIT-0

0 – APR is OFF Value should be “1”

BIT-0 0 – no-extra blanking Value should be “1”

OP5 – CHANNEL TABLE OPTIONS DESCRIPTION TX1 – TELETEXT AND uCONTROLLER OPTIONS DESCRIPTION

1 – Extra 150msec.blanking for VST (op4 b0 "1" ise), to SECAM color problem) 1, Auto APS after Stand-By

BIT-7 0 – no-extra blanking

" Value should be “0” BIT-7 0, no APS after Stand-By

1, “Programme” item in AUTOSTORE menu is visible 1 – ASD (Auto Sound Detection ) is available BIT-6 0, “Programme” item in AUTOSTORE menu is

invisible Value should be “1” BIT-6

0 – ASD is not available Value should be “1”

1, Force both channel on even no carrier ( carrier mute disable ) Teletext Language Groups

BIT-5 0, Default value after reset

Value should be “1”, 000, Group 1 – West (English, French, Swedish,Czech, German, Portuguese, Italian, Rumanian)

1, French OS Channel Table is available 001, Group 2 – West/East (Polish, French, Swedish, Czech, German, Serbian, Italian, Rumanian) BIT-4

0, French OS Channel Table is not available

Value should be “1” 010, Group 3 – West/Turkish (English, French, Swedish, Turkish, German, Portuguese, Italian, Rumanian)

1, French Channel Table is available 011, Group 4 – East/Cyrillic (English, Cyrillic, Swedish, Czech, German, Serbian, Lettish, Rumanian) BIT-3

0, French Channel Table is not available

Value should be “1” 100,Group 5 --Arabic (English,French,Swedish,Turkish,German,Hebrew,Italien, Arabic)

1, England Channel Table is available 101,Group 6 - West/Greek (English,French,German,Swedish,Dannish,Norwegian,Serbian,Croatian,Lettish,Litvanian, Greek) BIT-2

0, England Channel Table is not available

Value should be “1” 110,Group 7- West/Cyrillic (WEST-LET/RUS/UKR) (English,German,Swedish,Dannish,Norwegian,Finnish,Russian,Ukranian,Bulgarian,Lettish, Litvanian,Greek)

1, East Europe Channel Table is available BIT-1

0, East Europe Channel Table is not available Value should be “1”

BIT-5, 4, 3

111, AUTO Mode. One of the 7 group is selected automatically related to the menu language.

1, West Europe Channel Table is available 101, OSDEPROM M6 R It is used with OTP models. 110, ROM M6 P MASK PXX Series BIT-0

0, West Europe Channel Table is not available Value should be “1” BIT-2, 1, 0

111, Read Auto Gain Table for device from EEPROM MASK OBX Series (It is written on IC)





GEOM – GEOMETRY OPTIONS DESCRIPTIONS OPT8 –PIP OPTIONS DESCRIPTIONS 1 – DYNAMIC BASS is active 1 - DVD is available

BIT-7 0 - DYNAMIC BASS is inactive

SW T3X323 active. BIT-7 0 - DVD is not available

It is set according to DI settings

1 - SVHS audio input in FAV / BAV in 1-Install menüsünde Wide mode seçeneği çıkacak. (Only mono models) BIT-6

0 - SVHS in AV2

It is “1“ if SVHS connector is available BIT-6

0-Install menüsünde Wide mode olmayacak.

1 - AK37 adjustment values are valid 1, WHITE_INSERTION_FORCED is available BIT-5

0 - AK30 adjustment values are valid Value should be “0” BIT-5

0, WHITE_INSERTION_FORCED is not available Value should be “0”

1 - ZOOM Mode is available 1, AVL_DECAY_TIME_CHANGE is available BIT-4

0 - ZOOM Mode is not available BIT-4

0, AVL_DECAY_TIME_CHANGE is not available Value should be “0”

1 - SUBTITLE Mode is available 1, RGB_PEAK_LIMITATION is available BIT-3

0 - SUBTITLE Mode is not available BIT-3

0, RGB_PEAK_LIMITATION is not available Value should be “0”

1 - CINEMA Mode is available 1, SOUND follower is available BIT-2

0 - CINEMA Mode is not available BIT-2

0, SOUND follower is not available

1 - 14 / 9 Mode is available 1, Teletext is available BIT-1

0 - 14 / 9 Mode is not available BIT-1

0, Teletext is not available .

1 - Tube Format is 16 / 9 1, PanEu IDTV BIT-0

0 - Tube format is 4 / 3 BIT-0

0, UK IDTV

37

GENERAL BLOCK DIAGRAM of 11AK30

L

RTDA7266/7266L

I2C

QSS

TDA5112A

IF

TDA8174AW

SCART2 SCART1 FAV/BAV SVHS

115V+12V AUD.+8V+5V+5V St-by

ST92195MICRO

CONTROLLER

MONO

STV2248CVIDEO

PROCESSOR

RGBAMP

VERAMP

CRT

HORIZONTALDRIVEBU808DF

FBT

MSP 34X0D/GSTEREO SOUND

HP. AMP.TDA1308

AU.AMP

SERVICECONNECTOR

NVM

KEYPAD

IR SENSOR

PLL/VST TUNERUV1315/1316

SMPS

MC44608

VIDEOSWITCHING CIRCUITS

DVBBOX

11PW05 CARD

irazk

Text Box

11RGB30-3

irazk

Text Box

CIRCUIT DIAGRAMS OF 11AK30

irazk

Text Box

POWER CARD 11PW05

irazk

Text Box

11AK30A16

irazk

Text Box

AK30S-1

AK30 IDTVDVB-T MODULE

Hardware Specification

16PING08E1

49

B.IDTV PARTDIGITAL TERRESTRIAL MODULE-TV MAINBOARD CONNECTIONS ......................50General Description .......................................................................................................................50General Description .......................................................................................................................51 STi5518 (IC100) .....................................................................................................................51 SDRAM 8MByte (IC300, IC301)...........................................................................................68 Flash Memory 2 MByte (IC302).............................................................................................69 EEPROM 64K 2-wire Serial (IC303) ....................................................................................70 DVB-T COFDM Demodulator + FEC + ADC(IC401) ..........................................................71

USED IC LISTS .............................................................................................................................77Connectors ......................................................................................................................................78 PL100: 5518 JTAG Connectors ............................................................................................78 PL101 UART CONNECTOR.................................................................................................78 PL105 RS232 Serial Port ........................................................................................................78 PL106:POWER connector ......................................................................................................79 PL200 VIDEO SOCKET ........................................................................................................79 PL201 VIDEO SOCKET ........................................................Error! Bookmark not defined. PL202 AUDIO SOCKET........................................................................................................79 PL203 BT-601 DIGITAL VIDEO SOCKET..........................Error! Bookmark not defined. PL600 PCMCIA SOCKET .....................................................................................................80

power Requirements .......................................................................... Error! Bookmark not defined.pcb explanatıons .............................................................................................................................81 MAIN BOARD ( 16PING08E1 )............................................................................................81

schematics............................................................................................Error! Bookmark not defined..

50

DIGITAL TERRESTRIAL MODULE-TV MAINBOARD CONNECTIONS

RF IN

ANTENNA

TVTUNER

DVB-TTUNERPIP OUT

INTERRUPT

UART COMM.

3V3 DC SUPPLY

5V DC SUPPLY

12V DC SUPPLY

2V5 DC SUPPLY

30V DC SUPPLY

RIGHT AUDIO

CVBS

LEFT AUDIO

TV MAINBOARD

DVB-TMAINBOARD

POWER

RS232 (Rx, Tx)

AUDIO&VIDEO

R-G-B

51

General DescriptionMajor functional blocks are discussed briefly in this section. A more detailed description is contained later inthe document.

STi5518 (IC100)

1. IntroductionThe STi5518 integrates in a single chip: a transport demultiplex block; an ST20 32-bit system CPU;

an audio/video MPEG2 decoder; display and graphics features; a digital video encoder; and systemperipherals. The Sti5518 integrates DirecTV and DVB descramblers in the transport demultiplex block,allowing it to be used in both Digital Video Broadcasting (DVB) and Digital Satellite System (DSS) set-topbox applications.

2. Technical SpecificationIntegrated 32-bit host CPU up to 81 MHz

2 Kbytes of Icache, 2 Kbytes of Dcache, and 4 Kbytes of SRAM configurable as Dcache.

Audio decoder

5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputsIEC60958 -IEC61937 digital outputSRS®/TruSurround®DTS® digital out and MP3 decodingAlignment beep for satellite dishes.

Video decoder

Supports MPEG-2 MP@MLFully programmable zoom-in and zoom-outNTSC to PAL conversion.

DVD and SVCD subpicture decoder

High performance on-screen display

2 to 8 bits per pixel OSD optionsAnti-flicker, anti-flutter and anti-aliasing filters.

PAL/NTSC/SECAM encoder

RGB, CVBS, Y/C and YUV outputs with 10-bit DACsMacrovision® 7.01/6.1 compatible (optional).

52

Shared SDRAM memory interface

1 or 2x16-Mbit, or 1x64-Mbit 125 MHZ SDRAM.

Programmable CPU memory interface for SDRAM, ROM, peripherals...

Front-end interface

DVD, VCD, SVCD and CD-DA compatibleSerial, parallel and ATAPI interfacesHardware sector filteringIntegrated CSS decryption and track buffer.

Hardware transport-stream demultiplexor

Parallel/serial inputDES and DVB descramblers32 PID support.

Integrated peripherals

2 UARTs, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timersModem support44 bits of programmable I/OIR transmitter/receiver.

Professional toolset support

ANSI C compiler and libraries.

208 pin PQFP package.

The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-topboxes. It integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transportdemultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3D-surround andMP3 support, advanced display and graphics features, a digital video encoder and all of the systemperipherals required in a typical low-costinteractive receiver. To cover the needs of DVD-capable set-top boxes, STi5518 integration options includea CSS decryption block, a Dolby Digital audio decoder and Macrovision copy protection. An ATAPIinterface is built-in, supporting the glueless connection of standard Hard Disk Drives. In this way, theSTi5518 is ideal for set-top boxes featuring trick modes such as live TV recording, pausing and time-shifting. The STi5518 is backward compatible with the popular STi5500 set-top box decoder, allowing easymigration from the previous generation. The high level of integration in a single PQFP-208 package makesthe STi5518 ideally suited for low-cost, high-volume set-top box applications.

53

3. Architecture overviewThe figure below shows the architecture of the Sti5518.

This chapter gives a brief overview of each of the functional blocks of the STi5518.

4. STi5518 functional modulesa. Central processorThe STi5518 Central Processing Unit is a ST20C2+ 32-bit processor core. It contains instruction processinglogic,

54

instruction and data pointers, and an operand register. It directly accesses the high-speed on-chip SRAM,which can store data or programs and uses the cache to reduce access time to off-chip program and datamemory.The processor can access memory via the Programmable CPU Interface (often referred to as the EMI) or theShared Memory Interface (SMI), which is shared with the video, audio, sub-picture and OSD decoders.

b. MPEG video decoderThis is a real-time video compression processor supporting the MPEG-1 and MPEG-2 standards at videorates up t720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion for display is performed by vertical andhorizontal filters. User-defined bitmaps can be super-imposed on the display picture by using the on-screendisplay function. The display unit is part of the MPEG video decoder, it overlays the four display planesshown in the figure below. The display planes are normally overlaid in the order illustrated, with thebackground color at the back and the sub-picture at the front (used as a cursor plane). The sub-picture planecan alternatively be positioned between the OSD and MPEG video planes where it can be used as a secondon-screen display plane.

c. Audio decoderThe audio decoder accepts: Dolby Digital, MPEG-1 layers I, II and III, MPEG-2 layer II 6-channel, PCM,CDDA dataformats; MPEG2 PES streams for MPEG-2, MPEG-1, Dolby Digital, MP3, and Linear PCM (LPCM). Theaudio decoder supports DTS® digital out (DVD DTS and CDDA DTS). SPDIF input data (IEC-60958 orIEC-61937 standards) is accepted if an external circuitry extracts the PCM clock from the stream. Skipframe, repeat blocks and soft mute frame features can be used to synchronize audio and video data. PTSaudio extraction is also supported. The device outputs up to 6 channels of PCM data and appropriate clocksfor external digital-to-analog converters. Programmable downmix enables 1,2,3 or 4 channel outputs. Datacan be output in either I²S format or Sony format. The decoder can format output data according to IEC-60958 standard (for non compressed data: L/R channels, 16, 18, 20 and 24-bits) or IEC-61937 standard (forcompressed data), for FS = 96 kHz, 48 kHz, 44.1 kHz or 32 kHz. Sampling frequencies of 96 kHz, 48 kHz,44.1 kHz, 32 kHz and half sampling frequencies are supported. A downsampling filter (96 kHz/48 kHz) isavailable. The decoder supports dual mode for MPEG and Dolby Digital. It includes a Dolby surroundcompatible downmix and a ProLogic decoder. A pink noise generator enables the accurate positioning ofspeakers for optimal surround sound setup. PCM beep tone is a special mode used for Set Top Box. Itgenerates a triangular signal of variable frequency and amplitude on the left and right channels. In globalmute mode, the decoder decodes the incoming bitstream normally but the PCM and SPDIF outputs aresoftmuted. This mode is used to prepare a period of decoding mode, to synchronize audio and video datawithouthearing the audio. Slow-forward and fast-forward trick modes are available for compressed and non-compressed data. The control interface of the decoder is activated via memory mapped registers in the ST20address space.

d. IR transmitter/receiverThe STi5518 provides a pulse-position modulated signal for automatic VCR programming by the set-topbox. The

55

signal is output to the IR blast pin and an accessory jack pin, simultaneously. The pulse frequency, number ofpulses (envelope length) and the total cycle time is controlled by registers.

e. Modem analog front-end interfaceThe Modem Analog Front-end interface is used to transfer transmit and receive DAC and ADC samplesbetween the memory and an external modem analog front-end (MAFE), using a synchronous serial protocol.DMA is used totransfer the sample data between memory buffers and the MAFE interface module, with separate transmitand receive buffers and double buffering of the buffer pointers. FIFOs are used to take into account theaccess latency to memory, in a worst case system and to allow the use of bursts for memory bandwidthefficiency improvement. The V22 bis standard is supported.

f. Memory subsystem

On-chipThe on-chip memory includes 2Kbytes of instruction cache, 2Kbytes of data cache and 4Kbytes of SRAMthat can be optionally configured as data cache. The subsystem provides 240M/bytes of internal bandwidth,supporting pipelined 2- cycle internal memory access. The instruction and data caches are direct-mapped,with a write-back system for the data-cache. The caches support burst accesses to the external memories forrefill and write-back. Burst access increases the performance of pagemode DRAM memories.

Off-chipThere are two off-chip memory interfaces:• The external memory interface (EMI) accessed by the ST20 is used for the transfer of data and programsbetween the STi5518 and external peripherals, flash and additional SDRAM and DRAM.• Shared memory interface (SMI) controls the movement of data between the STi5518 and 16, 32 or 64Mbits ofSDRAM. This external SDRAM stores the display data generated by the MPEG decoder and CPU and theC2+code data.The EMI uses minimal external support logic to support memory subsystems, and accesses a 32 Mbytes ofphysicaladdress space (greater if SDRAM or DRAM is used) in four general purpose memory banks of 8 or 16 bitswide, 21 or 22 address lines, and byte select. For applications requiring extra memory, the EMI supports thisextra memory with zero external support logic, even for 16-bit SDRAM devices. The EMI can be configuredfor a wide variety of timing and decode functions by the configuration registers. The timing of each of thefour memory banks can be set separately, with different device types being placed in each bank with no needfor external hardware.

g. Serial communication

Asynchronous serial controllersThe Asynchronous Serial Controller (ASC), also referred to as the UART interface, provides serialcommunication

56

between the STi5518 and other microcontrollers, microprocessors or external peripherals. The STi5518 hasfourASCs, two of which are generally used by the SmartCard controllers.

Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. Parity,framing, andoverrun error detection increase data transfer reliability. Transmission and reception of data can be double-buffered, or 16-deep FIFOs can be used. A mechanism to distinguish the address from the data bytes isincluded for multiprocessor communication. Testing is supported by a loop-back option. A 16-bit baud-rategenerator provides the ASC with a separate serial clock signal.

Two ASCs support full-duplex and 2 half-duplex asynchronous communication, where both the transmitterand thereceiver use the same data frame format and the same baud rate. Each ASC can be set to operate inSmartCard mode for use when interfacing to a SmartCard.

Synchronous serial controllerTwo Synchronous Serial Controllers (SSC) provide high-speed interfaces to a wide variety of serialmemories, remote control receivers and other microcontrollers. The SSCs support all of the features of theSerial Peripheral Interface bus (SPI) and the I2C bus. The SSCs can be programmed to interface to otherserial bus standards. The SSCs share pins with the parallel input/output (PIO) ports, and support half-duplexsynchronous communication.

h. Front-end interfaceThe STi5518 can be connected to a front-end through the following interfaces:• I2S interface;• multi-format serial interface;• multi-format parallel interface;• ATAPI interface (for Hard Disk Drives and DVD-ROMs)

i. On-chip PLLThe on-chip PLL accepts 27 MHz input and generates all the internal high-frequency clocks needed for theCPU,MPEG and audio subsystems.

j. Diagnostic controller (DCU)The ST20 Diagnostic Controller Unit (DCU) is used to boot the CPU and to control and monitor the chipsystems via the standard IEEE 1194.1 Test Access Port. The DCU includes on-chip hardware with ICE (InCircuit Emulation) and LSA (Logic State Analyzer) features to facilitate verification and debugging ofsoftware running on the on-chip CPU in real time. It is an independent hardware module with a private linkfrom the host to support real-time diagnostics.

k. Interrupt subsystemThe interrupt system allows an on-chip module or external interrupt pin to interrupt an active process so thatan

57

interrupt handling process can be run. An interrupt can be signalled by one of the following: a signal on anexternalinterrupt pin, a signal from an internal peripheral or subsystem, software asserting an interrupt in the pendingregister. Interrupts are implemented by an on-chip interrupt controller and an on-chip interrupt-levelcontroller. The interrupt controller supports eight prioritized interrupts as inputs and manages the pendinginterrupts. This allows the nesting of pre-emptive interrupts for real-time system design. Each interrupt canbe programmed to be at a lower or higher priority than the high priority process queue.

l. PAL/NTSC/SECAM encoderThe integrated digital encoder converts a multiplexed 4:2:2 or 4:4:4 YCbCr stream into a standard analogbasebandPAL/NTSC or SECAM signal and into RGB, YUV, Yc and CVBS components. The encoder can performclosed-caption, CGMS encoding, and allows MacrovisionTM 7.01/6.1 copy protection. The DENC is able toencode Teletext according to the “CCIR/ITU-R Broadcast Teletext System B” specification, also known as“World System Teletext”.In DVB applications, Teletext data is embedded within DVB streams as MPEG data packets. It is theresponsibility of the software to handle incoming data packets and in particular to store Teletext packets in abuffer, which then passes them to the DENC on request.

m. SmartCard interfacesTwo SmartCard interfaces support SmartCards compliant with ISO7816-3. Each interface is has a UART(ASC), adedicated programmable clock generator, and eight bits of parallel IO port.

n. PWM and counter moduleThe PWM and counter module provides three PWM encoder outputs, three PWM decoder (capture) inputsand fourprogrammable timers. Each capture input can be programmed to detect rising edge, falling edge, both edgesor neither edge (disabled). These facilities are clocked by two independent clocks, one for PWM outputs andone for capture inputs/timers. The PWM counter is 8-bit, with 8-bit registers to set the output-high time. Thecapture/compare counter and the compare and capture registers are 32-bit. The module generates a singleinterrupt signal.

o. Parallel I/O module44 bits of parallel I/O are configured in 6 ports, and each bit is programmable as output or input. The outputcan beconfigured as a totem-pole or open-drain driver. The input compare logic can generate an interrupt on anychange of any input bit. Many parallel IO have alternate functions and can be connected to an internalperipheral signal such as a UART or SSC.

58

5. Pin list sorted by function

Alternate functions printed in Italic show a suggested use of the PIO; alternate functions not printed in Italicaremultiplexed with a specific hardware.

61

1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration.2. The NRSS_IN and NRSS_OUT pins are swapped around on the STi5518 compared to the STi5508.3. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path.4. Inverted. ATTENTION! the PIO input is also inverted.5. The PIO must be configured in open drain.6. BOOT_FROM_ROM is active during reset.7. Tie low whenever JTAG is not used.

62

6. Pins sorted by pin number

67

1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration.2. The NRSS_IN and NRSS_OUT pins are swapped around on the STi5518 compared to the STi5508.3. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path.4. Inverted. ATTENTION! the PIO input is also inverted.5. The PIO must be configured in open drain.6. Tie low whenever JTAG is not used7. BOOT_FROM_ROM is active during reset.

68

SDRAM 8MByte (IC300, IC301)

IC300 SDRAM is on the Shared Memory Interface (SMI) and decoded picture is stored in this sdram .Thesmi sdram has 121.5Mhz clock input.IC301 SDRAM is on the EMI( external memory interface) andsoftware runs over this sdram.The emi sdram has 81 Mhz clock input.

FEATURES• PC66-, PC100- and PC133-compliant• Fully synchronous; all signals registered on positiveedge of system clock• Internal pipelined operation; column address can bechanged every clock cycle• Internal banks for hiding row access/ precharge• Programmable burst lengths: 1, 2, 4, 8 or full page• Auto Precharge, includes CONCURRENT AUTOPRECHARGE, and Auto Refresh Modes• Self Refresh Modes: standard and low power• 64ms, 4,096-cycle refresh• LVTTL-compatible inputs and outputs• Single +3.3V 0.3V power supply

GENERAL DESCRIPTIONThe 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864

bits. It isinternally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on thepositiveedge of the clock signal, CLK). Each of the x4’s 16,777,216 -bit banks is organized as 4,096 rows by 1,024columns by 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read andwrite accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for aprogrammed number of locations in a programmed sequence. Accesses begin with the registration of anACTIVE command, which is then followed by a READ or WRITEcommand. The address bits registered coincident with the ACTIVE command are used to select the bank androw to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registeredcoincident with the READ or WRITE command are used to select the starting column location for the burstaccess.

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, orthe full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide aself-timed row precharge that is initiated at the end of the burst sequence. The 64Mb SDRAM uses aninternal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2nrule of prefetch architectures, but it also allows the column address to be changed on every clock cycle toachieve a high-speed, fully random access. Precharging one bank while accessing one of the other three

69

banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 64MbSDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided,along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM’soffer substantial advances in DRAM operating performance, including the ability to synchronously burst dataat a high data rate with automatic column-address generation, the ability to interleave between internal banksin order to hide precharge time and the capability to randomly change column addresses on each clock cycleduring a burst access.

Flash Memory 2 MByte (IC302)

• Single 3.0 V read, program and erase• Compatible with JEDEC-standard commands• Compatible with JEDEC-standard world-wide pinouts• Minimum 100,000 program/erase cycles80 ns maximum access time• Sector erase architectureOne 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word modeOne 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte modeAny combination of sectors can be concurrently erased. Also supports full chip erase• Boot Code Sector ArchitectureT = Top sector• Embedded Erase TM AlgorithmsAutomatically pre-programs and erases the chip or any sector• Embedded program TM AlgorithmsAutomatically programs and verifies data at specified address•Data Polling and Toggle Bit feature for detection of program or erase cycle completion• Ready/Busy output (RY/BY)Hardware method for detection of program or erase cycle completion• Automatic sleep modeWhen addresses remain stable, automatically switches themselves to low power mode•Low VCC write inhibit 2.5 V

GENERAL DESCRIPTIONThe MBM29LV160T is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1Mwordsof 16 bits each. The MBM29LV160T is offered in a 48-pin TSOP FBGA packages. The device is designedto be programmed in-system with the standard system 3.0 V VCC supply.The standard MBM29LV160T offers access times of 80 ns and 120 ns, allowing operation of high-speedmicroprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE),writeenable (WE), and output enable (OE) controls.The MBM29LV160T is pin and command set compatible with JEDEC standard E 2 PROMs. Commands arewritten to the command register using standard microprocessor write timings.The MBM29LV160T is programmed by executing the program command sequence. This will invoke the

70

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulsewidthsand verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5seconds.Erase is accomplished by executing the erase command sequence. This will invoke the Embedded EraseAlgorithm which is an internal algorithm that automatically preprograms the array if it is not alreadyprogrammedbefore executing the erase operation. During erase, the device automatically times the erase pulse widths andverifies proper cell margins.Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)The device also features a sector erase architecture. The sector mode allows each sector to be erased andreprogrammed without affecting other sectors. The device features single 3.0 V power supply operation forboth read and write functions. Internally generatedand regulated voltages are provided for the program and erase operations. A low VCC detector automaticallyinhibits write operations on the loss of power. The end of program or erase is detected by Data Polling ofDQ7 ,by the Toggle Bit feature on DQ6 , or the RY/BY output pin. Once the end of a program or erase cycle hasbeencomleted, the device internally resets to the read mode.The MBM29LV160Thas a hardware RESET pin. When this pin is driven low, execution of any EmbeddedProgram Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset totheread mode. The RESET pin is tied to the system reset circuitry. Therefore, if a system reset occurs duringthe Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to thereadmode and will have erroneous data stored in the address locations being programmed or erased.. Resettingthe device enables the system’s microprocessor to read the boot-up firmware from the Flash memory.

EEPROM 64K 2-wire Serial (IC303)

The 24C64is a 64K-bit Serial CMOS E2PROM internally organized as 4096/8192 words of 8 bits each.FeaturesCommercial, Industrial and AutomotiveTemperature Ranges1,000,000 Program/Erase Cycles100 Year Data RetentionZero Standby Current24C64 features a 32-byte page write buffer.The device operates via the I2C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages.400 KHz I2C Bus Compatible*1.8 to 6 Volt Read and Write Operation32-Byte Page Write BufferSelf-Timed Write Cycle with Auto-ClearSchmitt Trigger Inputs for Noise Protection

71

Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each E2PROM device andnegativeedge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain drivenand maybe wire-O Red with any number of other open-drain or open collector devices.DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwiredor left notconnected for hardware compatibility with 24C64. When the pins are hardwired, as many as four 64Kdevices may be addressed on a single bus system (device addressing is discussed in detail under the DeviceAddressing section). When the pins are not hardwired, the default A1 and A0 are zero.WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations.When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP isinternally pulled down toGND. Switching WP to VCC prior to a write operation creates a software write protect function.

Absolute Maximum RatingsOperating Temperature.................................. -55oC to +125oCStorage Temperature ..................................... -65oC to +150oCVoltage on Any Pinwith Respect to Ground .....................................-1.0V to +7.0VMaximum Operating Voltage .......................................... 6.25VDC Output Current........................................................ 5.0 mA

DVB-T COFDM Demodulator + FEC + ADC(IC401)

FeaturesDecodes DVB-T (ETS300744) and NorDig II_Single frequency network (SFN) compliant_Adjacent channel interference canceller (ACI)_Excellent Doppler performance (200 Hz)_Automatic guard interval and mode detection_Accepts 6, 7 and 8 MHz channel bandwidths_Lock indicators and general purpose I/O pins_Supports 2K, 8K modes_Supports QPSK, 16, 64 QAM constellations_1/4, 1/8, 1/16, 1/32 guard interval_Supports hierarchical and non-hierarchical modes_Fully digital demodulation_Impulsive noise rejection feature_Digital timing and frequency correction_Channel equalization through scattered pilots

72

_Common phase error correction_Transmitter parameter signalling decoding (TPS)TPS decoded or automatic FEC modedetection_Inner decoder:- Punctured codes 1/2, 2/3, 3/4, 5/6 and 7/8_Sync word extraction_Convolutive de-interleaver_Outer decoder:- Reed-Solomon decoder for 16 parity bytes;correction of up to 8 byte errors_Integrated signal quality monitors_Parallel and serial output interfaces compliant withDVB common interface_Hierarchical auxiliary FEC input/outputEmbeds PGA for IF level adaptation_High-performance ADC for direct IF (36 MHz)architecture_Dual AGC outputs)_10-bit ADC for RF signal strength indicatorGenerates system clock on-chip from20 to 27-MHz crystal quartz_No external VCXO required_Programmable o/p clock derived from system clockFour I²C addresses available_Easy control/monitoring via fast I²C bus (4 MHz)_Additional private I²C bus (I²C repeater) dedicatedto tuner control for minimum tuner disturbanceAbsolute maximum ratingsMaximum limits indicate where permanent device damages occur. Continuous operation atthese limits is not intended, and should be limited to those conditions specified below,

75

Figure 2- General view of STV0360

76

SAW FILTER(Z400)X6966M is band pass filter at center frequency of 36.125Mhz typically. It is used for 8Mhz bandwidthbroadcast reception.

DIGITAL TERRESTRIAL TUNER(TU400)- PLL TUNER OPTIMIZED FOR LOW PHASE NOISE LO. 5V AND 30V POWER SUPPLY.- LOW OUTPUT IMPEDANCE OF SIMMETRICAL I.F. AMPLIFIER, SPECIFICALLY DESIGNEDFOR DIRECT SAW FILTER DRIVE.- MIXER OSCILLATOR I.C. IMPROVES PERFORMANCE OF SIGNAL HANDLING.- IT COMPLIES WITH EUROPEAN STANDARD EN 55013 AND EN 55020.PLL I²C BUS TUNING SYSTEM.Input frequencies between 474 MHz and 858 Mhz(UHF band)Normal operating voltages+5V:4.75Vmin 5.5Vmax.+33V:30Vmin 35Vmax.Voltage at PİN 2 (agc input) can be max 3.3V to receive low RF signal or a breakdown occurs in thedemodulator or discrete if amplifier section.If tuner and discrete if amplifier circuit is operating properlyabout 400mVp-p baseband signal should be measured at pin 61 and pin62 of IC400.

77

USED IC LISTS

MAINBOARD: 16PING08E1

MAX 232 (IC101) RS232 Driver/Receiver

Sti5518 (IC100) Set Top Box Back-end Decoder With Integrated Host Processor

TSH 22 (IC103) Dual Bipolar Operational Amplifier

M74HCU04 (IC102) Hex Inverter

HY57V641620HG (IC301, IC300) 8 Mbyte SDRAM

29LV160TE (IC302) 2Mbyte(top boot) Flash Memory

ST24C64(IC303) 64Kbit Serial EEPROM

Stv0360 (IC401) COFDM demodulator.

CS4335 (IC201) 8-Pin, 24 Bit, 96 KHz Stereo D/A Converter

DS1811 (IC5) 150msec delay Reset IC.

AAT3524(IC5) Optional (150 msec delay Reset IC. With R59=4k7 R PULL UP )

STV0700 (IC600) 2 independent module capability, CI Standard compliant (CENELECEN-50221) PCMCIA compliance, 8-bit data access, 26-bit address

FMS7000 Five Channel 4th Order Standard Definition Video Filter Driver

78

Connectors

PL100: 5518 JTAG ConnectorsJTAG Connector – PL1Pin Description Pin Description1 ------ 11 TCK2 GND 12 GND3 TRIGOUT 13 TDI4 GND 14 GND5 TRIGIN 15 TDO6 GND 16 GND7 ------ 17 JTAGRESET8 GND 18 GND9 TMS 19 TRST10 GND 20 GND

PL101 UART CONNECTORUARTPin Description1 RXD2 TXD3 GND4 IRQ

PL105 RS232 Serial Port

RS232Pin Description1 NC2 NC3 TXD4 NC5 RXD6 NC7 NC8 NC9 GND10 NC

79

PL106:POWER connector

PİNS DESCRIPTION1 +2V52 +30V3 +12V4 GND5 GND6 +5V7 +3V3

PL200 VIDEO SOCKETVIDEO SOCKET PL200

Pin Description Voltage Rating MeasurementConditions

1 GND - -2 RED 700 mVpp At 75ohm load3 GND - -4 GREEN 700 mVpp At 75ohm load5 GND - -6 BLUE 700 mVpp At 75ohm load7 GND - -8 CVBS 1Vpp At 75ohm load

PL202 AUDIO SOCKETPL202

Pin Description VoltageRating

MeasurementConditions

1AudioRight/LeftOutput

3.7 Vpp@ 1khz 0 dbfspattern for 10 kload

2 GND - -

3AudioLeft/RightOutput

3.7 Vpp@ 1khz 0 dbfspattern for 10 kload

80

PL204 S/PDIF DIGITAL AUDIO SOCKET

Pin Description Voltage Rating MeasurementConditions

1 S/PDIF 3.3V pp Open-end2 GND - -

PL600 PCMCIA SOCKET

This socket is compliant for 2 slot Common Interface module usage for CENELEC EN-50221 - DVB CIstandart. The socket includes right-eject( Optional ) which helps user to attach or detach CI modules easily.There is also a metal bar which is set-to-meet both sides of CI socket.

POWER REQUIREMENTS

Typical Min. Max.2.5V 2.5V 2.4V 2.6V32V 32V 30V 33V12V 12V 11.75V 12.25V5V 5.1V 5V 5.4V3.3V 3.3V 3.2V 3.4V

STBY ACTIVE 1CAM inserted 2 CAM inserted.2.5V 720mam

p720mamp

720mamp 720mamp

32V 1mamp 1mamp 1mamp 1mamp12V 55mamp 55mamp 55mamp 55mamp5V 290mam

p290mamp

340mamp 390mamp

3.3V 350mamp

350mamp

350mamp 350mamp

81

PCB EXPLANATIONS

MAIN BOARD ( 16PING08E1 )

The main board contains two parts: Front-end (sheet4) and Back-end. The digital signal isdemodulated in Front-end and then decoded in Back-end. Analog signals are processed in different part.

The tuner (TU400 Thomson or SAMSUNG) is capable of getting both digital broadcasts. Tuner IFouput is bandpass filtered at Z400 (saw fiter) and pass along the discrete if amplifier circuit (sheet 4 left side)and analogue digital signal is converted to transport stream signals after some filtering, COFDM (codedorthogonal) demodulation (by using 2k or 8k carriers) and correction.The demodulator output is configuredas parallel.The digital data is transported to the sti5518 mpeg-2 decoder(ic100) with fc_clk(clock signal todecoder), fc_valid(indicates valid data bits of transport stream(ts)) and fc_sync (indicates start of a ts ).

The ts has all the multiplexed signals which includes video, audio and data information related toone or more than one program . TS_ERROR signal should be low for valid data and for mpeg-2 decoder todecode properly.stv0360 DEMODULATOR is controlled via I2C by sti5518 decoder and TU400 iscontroled by demodulator(ic400) via sclk and sdata.

At the back-end part, there is a 32-bit CPU ST20 (in Sti 5518 embedded ) that controls all processes.Demultiplexer of the CPU provides the transmission of the desired channel’s information from TS(Transport Stream) to MPEG Decoder section. The program that runs on Sti5518 is in Flash memory(IC302).64Mbits SDRAMs (IC301, IC300) are used for data memory of this program.IC300 is SMI sdram anddecoded data is stored here.It has a clock input of 121.5Mhz. Software is mostly run over IC301 EMI sdram.Some program and status information is stored in eeprom(IC303).

ST20 uses 32- bit data and 22- bit address buses for access to flash, DRAM and MPEG decoder. Ituses RAS, CAS etc. (read, write, enable) signals to activate related IC while accessing them.

The main clock which is needed by Sti 5518 (IC100), is generated at power on mode and at stby by27MHz crystal (X100) and IC102 (74HCU04).

Sti 5518 (IC100) can communicate with any other micro controller via RS232 by the help of IC101(MAX232- RS232 level converter). The RS232 output of receiver is used for debug any problem usingWindows Hyper Terminal program.

MPEG decoder in Sti 5518, is responsible for decoding of MPEG video and audio signals. Thevideo, which is compressed using MPEG2 and audio, which is compressed using MPEG1 Layer 1-2, areprocessed here. After decoding, CCIR 601 formatted 8-bit video and PCM formatted audio, are generated bympeg decoder.

Digital audio which is PCM formatted on Sti 5518’s output, is processed by CS4334 (IC201). Someprogram information is stored in 64Kbits E2PROM (24C64– IC303) via I2C.

irazk

Text Box

SCHEMATIC DIAGRAM DVB BOX 16PING08E1

gödöllő szabadság tér 12

Documents